void CalculateSync()
{
//clc_pvr_scanline=0;
u32 pixel_clock;
float scale_x=1,scale_y=1;
if (FB_R_CTRL.vclk_div)
{
//VGA :)
pixel_clock=PIXEL_CLOCK;
}
else
{
//It is half for NTSC/PAL
pixel_clock=PIXEL_CLOCK/2;
}
//We need to caclulate the pixel clock
u32 sync_cycles=(SPG_LOAD.hcount+1)*(SPG_LOAD.vcount+1);
pvr_numscanlines=SPG_LOAD.vcount+1;
Line_Cycles=(u32)((u64)DCclock*(u64)(SPG_LOAD.hcount+1)/(u64)pixel_clock);
if (SPG_CONTROL.interlace)
{
//this is a temp hack
Line_Cycles/=2;
u32 interl_mode=VO_CONTROL.field_mode;
//if (interl_mode==2)//3 will be funny =P
// scale_y=0.5f;//single interlace
//else
scale_y=1;
}
else
{
if (FB_R_CTRL.vclk_div)
{
scale_y=1.0f;//non interlaced vga mode has full resolution :)
}
else
scale_y=0.5f;//non interlaced modes have half resolution
}
rend_set_fb_scale(scale_x,scale_y);
//Frame_Cycles=(u64)DCclock*(u64)sync_cycles/(u64)pixel_clock;
Frame_Cycles=pvr_numscanlines*Line_Cycles;
}
void CalculateSync()
{
u32 pixel_clock;
float scale_x=1,scale_y=1;
pixel_clock=PIXEL_CLOCK / (FB_R_CTRL.vclk_div?1:2);
//We need to calculate the pixel clock
u32 sync_cycles=(SPG_LOAD.hcount+1)*(SPG_LOAD.vcount+1);
pvr_numscanlines=SPG_LOAD.vcount+1;
Line_Cycles=(u32)((u64)SH4_MAIN_CLOCK*(u64)(SPG_LOAD.hcount+1)/(u64)pixel_clock);
if (SPG_CONTROL.interlace)
{
//this is a temp hack
Line_Cycles/=2;
u32 interl_mode=VO_CONTROL.field_mode;
//if (interl_mode==2)//3 will be funny =P
// scale_y=0.5f;//single interlace
//else
scale_y=1;
}
else
{
if (FB_R_CTRL.vclk_div)
{
scale_y = 1.0f;//non interlaced VGA mode has full resolution :)
}
else
{
scale_y = 0.5f;//non interlaced modes have half resolution
}
}
rend_set_fb_scale(scale_x,scale_y);
//Frame_Cycles=(u64)DCclock*(u64)sync_cycles/(u64)pixel_clock;
Frame_Cycles=pvr_numscanlines*Line_Cycles;
prv_cur_scanline=0;
sh4_sched_request(vblank_schid,Line_Cycles);
}
void CalculateSync(void)
{
/* 00=VGA 01=NTSC 10=PAL, 11=illegal/undocumented */
const int spg_clks[4] = { 26944080, 13458568, 13462800, 26944080 };
float scale_x = 1;
float scale_y = 1;
u32 pixel_clock = spg_clks[(SPG_CONTROL.full >> 6) & 3];
pvr_numscanlines = SPG_LOAD.vcount+1;
Line_Cycles = (u32)((u64)SH4_MAIN_CLOCK*(u64)(SPG_LOAD.hcount+1)/(u64)pixel_clock);
if (SPG_CONTROL.interlace)
{
//this is a temp hack
Line_Cycles /= 2;
u32 interl_mode = VO_CONTROL.field_mode;
//if (interl_mode==2)//3 will be funny =P
// scale_y=0.5f;//single interlace
//else
scale_y=1;
}
else
{
if (FB_R_CTRL.vclk_div)
scale_y = 1.0f;//non interlaced VGA mode has full resolution :)
else
scale_y = 0.5f;//non interlaced modes have half resolution
}
rend_set_fb_scale(scale_x,scale_y);
Frame_Cycles = pvr_numscanlines*Line_Cycles;
prv_cur_scanline = 0;
sh4_sched_request(vblank_sched, Line_Cycles);
}
