u32 res_trk_get_curr_perf_level(u32 *pn_perf_lvl)
{
unsigned long freq;
if (!pn_perf_lvl) {
VCDRES_MSG_ERROR("%s(): pn_perf_lvl is NULL\n",
__func__);
return false;
}
VCDRES_MSG_LOW("clk_regime_msm_get_clk_freq_hz");
if (!res_trk_get_clk_rate(&freq)) {
VCDRES_MSG_ERROR("%s(): res_trk_get_clk_rate FAILED\n",
__func__);
*pn_perf_lvl = 0;
return false;
}
*pn_perf_lvl = res_trk_convert_freq_to_perf_lvl((u64) freq);
VCDRES_MSG_MED("%s(): freq = %lu, *pn_perf_lvl = %u", __func__,
freq, *pn_perf_lvl);
return true;
}
u32 res_trk_set_perf_level(u32 req_perf_lvl, u32 *pn_set_perf_lvl,
struct vcd_dev_ctxt *dev_ctxt)
{
struct vcd_clnt_ctxt *cctxt_itr = NULL;
u32 axi_freq = 0, mfc_freq = 0, calc_mfc_freq = 0;
u8 enc_clnt_present = false;
if (!pn_set_perf_lvl || !dev_ctxt) {
VCDRES_MSG_ERROR("%s(): NULL pointer! dev_ctxt(%p)\n",
__func__, dev_ctxt);
return false;
}
VCDRES_MSG_LOW("%s(), req_perf_lvl = %d", __func__, req_perf_lvl);
calc_mfc_freq = res_trk_convert_perf_lvl_to_freq(
(u64)req_perf_lvl);
if (calc_mfc_freq < VCD_RESTRK_MIN_FREQ_POINT)
calc_mfc_freq = VCD_RESTRK_MIN_FREQ_POINT;
else if (calc_mfc_freq > VCD_RESTRK_MAX_FREQ_POINT)
calc_mfc_freq = VCD_RESTRK_MAX_FREQ_POINT;
cctxt_itr = dev_ctxt->cctxt_list_head;
while (cctxt_itr) {
VCDRES_MSG_LOW("\n cctxt_itr = %p", cctxt_itr);
if (!cctxt_itr->decoding) {
VCDRES_MSG_LOW("\n Encoder client");
enc_clnt_present = true;
break;
} else {
VCDRES_MSG_LOW("\n Decoder client");
}
cctxt_itr = cctxt_itr->next;
}
if (enc_clnt_present) {
if (req_perf_lvl >= VGA_PERF_LEVEL) {
mfc_freq = mfc_clk_freq_table[2];
axi_freq = axi_clk_freq_table_enc[1];
} else {
mfc_freq = mfc_clk_freq_table[0];
axi_freq = axi_clk_freq_table_enc[0];
}
VCDRES_MSG_MED("\n ENCODER: axi_freq = %u"
", mfc_freq = %u, calc_mfc_freq = %u,"
" req_perf_lvl = %u", axi_freq,
mfc_freq, calc_mfc_freq,
req_perf_lvl);
} else {
if (req_perf_lvl <= QVGA_PERF_LEVEL) {
mfc_freq = mfc_clk_freq_table[0];
axi_freq = axi_clk_freq_table_dec[0];
} else {
axi_freq = axi_clk_freq_table_dec[0];
if (req_perf_lvl <= VGA_PERF_LEVEL)
mfc_freq = mfc_clk_freq_table[0];
else if (req_perf_lvl <= WVGA_PERF_LEVEL)
mfc_freq = mfc_clk_freq_table[1];
else {
mfc_freq = mfc_clk_freq_table[2];
axi_freq = axi_clk_freq_table_dec[1];
}
}
VCDRES_MSG_MED("\n DECODER: axi_freq = %u"
", mfc_freq = %u, calc_mfc_freq = %u,"
" req_perf_lvl = %u", axi_freq,
mfc_freq, calc_mfc_freq,
req_perf_lvl);
}
#ifdef AXI_CLK_SCALING
if (req_perf_lvl != VCD_RESTRK_MIN_PERF_LEVEL) {
VCDRES_MSG_MED("\n %s(): Setting AXI freq to %u",
__func__, axi_freq);
clk_set_rate(ebi1_clk, axi_freq * 1000);
}
#endif
#ifdef USE_RES_TRACKER
if (req_perf_lvl != VCD_RESTRK_MIN_PERF_LEVEL) {
VCDRES_MSG_MED("\n %s(): Setting MFC freq to %u",
__func__, mfc_freq);
if (!res_trk_sel_clk_rate(mfc_freq)) {
VCDRES_MSG_ERROR("%s(): res_trk_sel_clk_rate FAILED\n",
__func__);
*pn_set_perf_lvl = 0;
return false;
}
}
#endif
*pn_set_perf_lvl =
res_trk_convert_freq_to_perf_lvl((u64) mfc_freq);
return true;
}
u32 res_trk_set_perf_level(u32 n_req_perf_lvl, u32 *pn_set_perf_lvl,
struct vcd_clnt_ctxt_type_t *p_cctxt)
{
u32 axi_freq = 0, mfc_freq = 0, calc_mfc_freq = 0;
int rc = -1;
if (!pn_set_perf_lvl) {
VCDRES_MSG_ERROR("%s(): pn_perf_lvl is NULL\n",
__func__);
return FALSE;
}
VCDRES_MSG_LOW("%s(), n_req_perf_lvl = %d", __func__, n_req_perf_lvl);
if (p_cctxt) {
calc_mfc_freq = res_trk_convert_perf_lvl_to_freq(
(u64)n_req_perf_lvl);
if (calc_mfc_freq < VCD_RESTRK_MIN_FREQ_POINT)
calc_mfc_freq = VCD_RESTRK_MIN_FREQ_POINT;
else if (calc_mfc_freq > VCD_RESTRK_MAX_FREQ_POINT)
calc_mfc_freq = VCD_RESTRK_MAX_FREQ_POINT;
if (!p_cctxt->b_decoding) {
if (n_req_perf_lvl >= VGA_PERF_LEVEL) {
mfc_freq = mfc_clk_freq_table[2];
axi_freq = axi_clk_freq_table_enc[1];
} else {
mfc_freq = mfc_clk_freq_table[0];
axi_freq = axi_clk_freq_table_enc[0];
}
VCDRES_MSG_HIGH("\n ENCODER: axi_freq = %u"
", mfc_freq = %u, calc_mfc_freq = %u,"
" n_req_perf_lvl = %u", axi_freq,
mfc_freq, calc_mfc_freq,
n_req_perf_lvl);
} else {
if (n_req_perf_lvl <= QVGA_PERF_LEVEL) {
mfc_freq = mfc_clk_freq_table[0];
axi_freq = axi_clk_freq_table_dec[0];
} else {
axi_freq = axi_clk_freq_table_dec[0];
if (n_req_perf_lvl <= VGA_PERF_LEVEL)
mfc_freq = mfc_clk_freq_table[0];
else if (n_req_perf_lvl <= WVGA_PERF_LEVEL)
mfc_freq = mfc_clk_freq_table[1];
else {
mfc_freq = mfc_clk_freq_table[2];
axi_freq = axi_clk_freq_table_dec[1];
}
}
VCDRES_MSG_HIGH("\n DECODER: axi_freq = %u"
", mfc_freq = %u, calc_mfc_freq = %u,"
" n_req_perf_lvl = %u", axi_freq,
mfc_freq, calc_mfc_freq,
n_req_perf_lvl);
}
} else {
VCDRES_MSG_HIGH("%s() WARNING:: p_cctxt is NULL", __func__);
return TRUE;
}
#ifdef AXI_CLK_SCALING
if (n_req_perf_lvl != VCD_RESTRK_MIN_PERF_LEVEL) {
VCDRES_MSG_HIGH("\n %s(): Setting AXI freq to %u",
__func__, axi_freq);
rc = pm_qos_update_requirement(PM_QOS_SYSTEM_BUS_FREQ,
MSM_AXI_QOS_NAME, axi_freq);
if (rc < 0) {
VCDRES_MSG_ERROR("\n Update AXI bus QOS fails,"
"rc = %d\n", rc);
return FALSE;
}
}
#endif
#ifdef USE_RES_TRACKER
if (n_req_perf_lvl != VCD_RESTRK_MIN_PERF_LEVEL) {
VCDRES_MSG_HIGH("\n %s(): Setting MFC freq to %u",
__func__, mfc_freq);
if (!vid_c_sel_clk_rate(mfc_freq)) {
VCDRES_MSG_ERROR("%s(): vid_c_sel_clk_rate FAILED\n",
__func__);
*pn_set_perf_lvl = 0;
return FALSE;
}
}
#endif
*pn_set_perf_lvl =
res_trk_convert_freq_to_perf_lvl((u64) mfc_freq);
return TRUE;
}
