Example #1
0
static MACHINE_RESET( atetris )
{
	/* reset the slapstic */
	slapstic_reset();
	current_bank = slapstic_bank() & 1;
	reset_bank();

	/* start interrupts going (32V clocked by 16V) */
	timer_adjust_oneshot(interrupt_timer, video_screen_get_time_until_pos(machine->primary_screen, 48, 0), 48);
}
Example #2
0
void atetris_state::machine_reset()
{
	/* reset the slapstic */
	m_slapstic_device->slapstic_reset();
	m_current_bank = m_slapstic_device->slapstic_bank() & 1;
	reset_bank();

	/* start interrupts going (32V clocked by 16V) */
	m_interrupt_timer->adjust(m_screen->time_until_pos(48), 48);
}
Example #3
0
static MACHINE_RESET( atetris )
{
	atetris_state *state = machine.driver_data<atetris_state>();

	/* reset the slapstic */
	slapstic_reset();
	state->m_current_bank = slapstic_bank() & 1;
	reset_bank(machine);

	/* start interrupts going (32V clocked by 16V) */
	state->m_interrupt_timer->adjust(machine.primary_screen->time_until_pos(48), 48);
}
Example #4
0
static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col,
			   int page)
{
	struct denali_nand_info *denali = mtd_to_denali(mtd);
	uint32_t addr, id;
	int i;

	switch (cmd) {
	case NAND_CMD_PAGEPROG:
		break;
	case NAND_CMD_STATUS:
		read_status(denali);
		break;
	case NAND_CMD_READID:
	case NAND_CMD_PARAM:
		reset_buf(denali);
		/*sometimes ManufactureId read from register is not right
		 * e.g. some of Micron MT29F32G08QAA MLC NAND chips
		 * So here we send READID cmd to NAND insteand
		 * */
		addr = (uint32_t)MODE_11 | BANK(denali->flash_bank);
		index_addr(denali, (uint32_t)addr | 0, 0x90);
		index_addr(denali, (uint32_t)addr | 1, 0);
		for (i = 0; i < 5; i++) {
			index_addr_read_data(denali,
						(uint32_t)addr | 2,
						&id);
			write_byte_to_buf(denali, id);
		}
		break;
	case NAND_CMD_READ0:
	case NAND_CMD_SEQIN:
		denali->page = page;
		break;
	case NAND_CMD_RESET:
		reset_bank(denali);
		break;
	case NAND_CMD_READOOB:
		/* TODO: Read OOB data */
		break;
	default:
		printk(KERN_ERR ": unsupported command"
				" received 0x%x\n", cmd);
		break;
	}
}
static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col,
			   int page)
{
	struct denali_nand_info *denali = mtd_to_denali(mtd);
	uint32_t addr, id;
	int i;

	switch (cmd) {
	case NAND_CMD_PAGEPROG:
		break;
	case NAND_CMD_STATUS:
		read_status(denali);
		break;
	case NAND_CMD_READID:
	case NAND_CMD_PARAM:
		reset_buf(denali);
		addr = (uint32_t)MODE_11 | BANK(denali->flash_bank);
		index_addr(denali, (uint32_t)addr | 0, 0x90);
		index_addr(denali, (uint32_t)addr | 1, 0);
		for (i = 0; i < 5; i++) {
			index_addr_read_data(denali,
						(uint32_t)addr | 2,
						&id);
			write_byte_to_buf(denali, id);
		}
		break;
	case NAND_CMD_READ0:
	case NAND_CMD_SEQIN:
		denali->page = page;
		break;
	case NAND_CMD_RESET:
		reset_bank(denali);
		break;
	case NAND_CMD_READOOB:
		
		break;
	default:
		printk(KERN_ERR ": unsupported command"
				" received 0x%x\n", cmd);
		break;
	}
}
Example #6
0
static STATE_POSTLOAD( atetris_postload )
{
	reset_bank();
}
Example #7
0
static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col,
			   int page)
{
	struct denali_nand_info *denali = mtd_to_denali(mtd);
	uint32_t addr, id;
	uint32_t pages_per_block;
	uint32_t block;
	int i;

	switch (cmd) {
	case NAND_CMD_PAGEPROG:
		break;
	case NAND_CMD_STATUS:
		read_status(denali);
		break;
	case NAND_CMD_READID:
		reset_buf(denali);
		/*
		 * sometimes ManufactureId read from register is not right
		 * e.g. some of Micron MT29F32G08QAA MLC NAND chips
		 * So here we send READID cmd to NAND insteand
		 */
		addr = MODE_11 | BANK(denali->flash_bank);
		index_addr(denali, addr | 0, 0x90);
		index_addr(denali, addr | 1, col);
		for (i = 0; i < 8; i++) {
			index_addr_read_data(denali, addr | 2, &id);
			write_byte_to_buf(denali, id);
		}
		break;
	case NAND_CMD_PARAM:
		reset_buf(denali);

		/* turn on R/B interrupt */
		denali_set_intr_modes(denali, false);
		denali_irq_mask = DENALI_IRQ_ALL | INTR_STATUS__INT_ACT;
		clear_interrupts(denali);
		denali_irq_enable(denali, denali_irq_mask);
		denali_set_intr_modes(denali, true);

		addr = (uint32_t)MODE_11 | BANK(denali->flash_bank);
		index_addr(denali, (uint32_t)addr | 0, cmd);
		index_addr(denali, (uint32_t)addr | 1, col & 0xFF);
		/* Wait tR time... */
		udelay(25);
		/* And then wait for R/B interrupt */
		wait_for_irq(denali, INTR_STATUS__INT_ACT);

		/* turn off R/B interrupt now */
		denali_irq_mask = DENALI_IRQ_ALL;
		denali_set_intr_modes(denali, false);
		denali_irq_enable(denali, denali_irq_mask);
		denali_set_intr_modes(denali, true);

		for (i = 0; i < 256; i++) {
			index_addr_read_data(denali,
						(uint32_t)addr | 2,
						&id);
			write_byte_to_buf(denali, id);
		}
		break;
	case NAND_CMD_READ0:
	case NAND_CMD_SEQIN:
		denali->page = page;
		break;
	case NAND_CMD_RESET:
		reset_bank(denali);
		break;
	case NAND_CMD_READOOB:
		/* TODO: Read OOB data */
		break;
	case NAND_CMD_UNLOCK1:
		pages_per_block = mtd->erasesize / mtd->writesize;
		block = page / pages_per_block;
		addr = (uint32_t)MODE_10 | (block * pages_per_block);
		index_addr(denali, addr, 0x10);
		break;
	case NAND_CMD_UNLOCK2:
		pages_per_block = mtd->erasesize / mtd->writesize;
		block = (page+pages_per_block-1) / pages_per_block;
		addr = (uint32_t)MODE_10 | (block * pages_per_block);
		index_addr(denali, addr, 0x11);
		break;
	case NAND_CMD_ERASE1:
	case NAND_CMD_ERASE2:
		addr = MODE_10 | BANK(denali->flash_bank) | page;
		index_addr(denali, addr, 0x1);
		break;
	default:
		pr_err(": unsupported command received 0x%x\n", cmd);
		break;
	}
}
Example #8
0
static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col,
			   int page)
{
	struct denali_nand_info *denali = mtd_to_denali(mtd);
	uint32_t addr;

	switch (cmd) {
	case NAND_CMD_PAGEPROG:
		break;
	case NAND_CMD_STATUS:
		addr = MODE_11 | BANK(denali->flash_bank);
		index_addr(denali, addr | 0, cmd);
		break;
	case NAND_CMD_READID:
	case NAND_CMD_PARAM:
		reset_buf(denali);
		/*
		 * sometimes ManufactureId read from register is not right
		 * e.g. some of Micron MT29F32G08QAA MLC NAND chips
		 * So here we send READID cmd to NAND insteand
		 */
		addr = MODE_11 | BANK(denali->flash_bank);
		index_addr(denali, addr | 0, cmd);
		index_addr(denali, addr | 1, col & 0xFF);
		if (cmd == NAND_CMD_PARAM)
			udelay(50);
		break;
	case NAND_CMD_RNDOUT:
		addr = MODE_11 | BANK(denali->flash_bank);
		index_addr(denali, addr | 0, cmd);
		index_addr(denali, addr | 1, col & 0xFF);
		index_addr(denali, addr | 1, col >> 8);
		index_addr(denali, addr | 0, NAND_CMD_RNDOUTSTART);
		break;
	case NAND_CMD_READ0:
	case NAND_CMD_SEQIN:
		denali->page = page;
		break;
	case NAND_CMD_RESET:
		reset_bank(denali);
		break;
	case NAND_CMD_READOOB:
		/* TODO: Read OOB data */
		break;
	case NAND_CMD_ERASE1:
		/*
		 * supporting block erase only, not multiblock erase as
		 * it will cross plane and software need complex calculation
		 * to identify the block count for the cross plane
		 */
		denali_erase(mtd, page);
		break;
	case NAND_CMD_ERASE2:
		/* nothing to do here as it was done during NAND_CMD_ERASE1 */
		break;
	case NAND_CMD_UNLOCK1:
		addr = MODE_10 | BANK(denali->flash_bank) | page;
		index_addr(denali, addr | 0, DENALI_UNLOCK_START);
		break;
	case NAND_CMD_UNLOCK2:
		addr = MODE_10 | BANK(denali->flash_bank) | page;
		index_addr(denali, addr | 0, DENALI_UNLOCK_END);
		break;
	case NAND_CMD_LOCK:
		addr = MODE_10 | BANK(denali->flash_bank);
		index_addr(denali, addr | 0, DENALI_LOCK);
		break;
	default:
		printf(": unsupported command received 0x%x\n", cmd);
		break;
	}
}