static int st_ahci_deassert_resets(struct device *dev)
{
struct st_ahci_drv_data *drv_data = dev_get_drvdata(dev);
int err;
if (drv_data->pwr) {
err = reset_control_deassert(drv_data->pwr);
if (err) {
dev_err(dev, "unable to bring out of pwrdwn\n");
return err;
}
}
st_ahci_configure_oob(drv_data->hpriv->mmio);
if (drv_data->sw_rst) {
err = reset_control_deassert(drv_data->sw_rst);
if (err) {
dev_err(dev, "unable to bring out of sw-rst\n");
return err;
}
}
if (drv_data->pwr_rst) {
err = reset_control_deassert(drv_data->pwr_rst);
if (err) {
dev_err(dev, "unable to bring out of pwr-rst\n");
return err;
}
}
return 0;
}
static int histb_pcie_host_enable(struct pcie_port *pp)
{
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
struct histb_pcie *hipcie = to_histb_pcie(pci);
struct device *dev = pci->dev;
int ret;
/* power on PCIe device if have */
if (gpio_is_valid(hipcie->reset_gpio))
gpio_set_value_cansleep(hipcie->reset_gpio, 1);
ret = clk_prepare_enable(hipcie->bus_clk);
if (ret) {
dev_err(dev, "cannot prepare/enable bus clk\n");
goto err_bus_clk;
}
ret = clk_prepare_enable(hipcie->sys_clk);
if (ret) {
dev_err(dev, "cannot prepare/enable sys clk\n");
goto err_sys_clk;
}
ret = clk_prepare_enable(hipcie->pipe_clk);
if (ret) {
dev_err(dev, "cannot prepare/enable pipe clk\n");
goto err_pipe_clk;
}
ret = clk_prepare_enable(hipcie->aux_clk);
if (ret) {
dev_err(dev, "cannot prepare/enable aux clk\n");
goto err_aux_clk;
}
reset_control_assert(hipcie->soft_reset);
reset_control_deassert(hipcie->soft_reset);
reset_control_assert(hipcie->sys_reset);
reset_control_deassert(hipcie->sys_reset);
reset_control_assert(hipcie->bus_reset);
reset_control_deassert(hipcie->bus_reset);
return 0;
err_aux_clk:
clk_disable_unprepare(hipcie->aux_clk);
err_pipe_clk:
clk_disable_unprepare(hipcie->pipe_clk);
err_sys_clk:
clk_disable_unprepare(hipcie->sys_clk);
err_bus_clk:
clk_disable_unprepare(hipcie->bus_clk);
return ret;
}
static int st_ehci_platform_power_on(struct platform_device *dev)
{
struct usb_hcd *hcd = platform_get_drvdata(dev);
struct st_ehci_platform_priv *priv = hcd_to_ehci_priv(hcd);
int clk, ret;
ret = reset_control_deassert(priv->pwr);
if (ret)
return ret;
ret = reset_control_deassert(priv->rst);
if (ret)
goto err_assert_power;
/* some SoCs don't have a dedicated 48Mhz clock, but those that do
need the rate to be explicitly set */
if (priv->clk48) {
ret = clk_set_rate(priv->clk48, 48000000);
if (ret)
goto err_assert_reset;
}
for (clk = 0; clk < USB_MAX_CLKS && priv->clks[clk]; clk++) {
ret = clk_prepare_enable(priv->clks[clk]);
if (ret)
goto err_disable_clks;
}
ret = phy_init(priv->phy);
if (ret)
goto err_disable_clks;
ret = phy_power_on(priv->phy);
if (ret)
goto err_exit_phy;
return 0;
err_exit_phy:
phy_exit(priv->phy);
err_disable_clks:
while (--clk >= 0)
clk_disable_unprepare(priv->clks[clk]);
err_assert_reset:
reset_control_assert(priv->rst);
err_assert_power:
reset_control_assert(priv->pwr);
return ret;
}
static int da8xx_rproc_start(struct rproc *rproc)
{
struct device *dev = rproc->dev.parent;
struct da8xx_rproc *drproc = (struct da8xx_rproc *)rproc->priv;
struct clk *dsp_clk = drproc->dsp_clk;
struct reset_control *dsp_reset = drproc->dsp_reset;
int ret;
/* hw requires the start (boot) address be on 1KB boundary */
if (rproc->bootaddr & 0x3ff) {
dev_err(dev, "invalid boot address: must be aligned to 1KB\n");
return -EINVAL;
}
writel(rproc->bootaddr, drproc->bootreg);
ret = clk_prepare_enable(dsp_clk);
if (ret) {
dev_err(dev, "clk_prepare_enable() failed: %d\n", ret);
return ret;
}
ret = reset_control_deassert(dsp_reset);
if (ret) {
dev_err(dev, "reset_control_deassert() failed: %d\n", ret);
clk_disable_unprepare(dsp_clk);
return ret;
}
return 0;
}
static int _alt_hps2fpga_enable_set(struct altera_hps2fpga_data *priv,
bool enable)
{
unsigned long flags;
int ret;
/* bring bridge out of reset */
if (enable)
ret = reset_control_deassert(priv->bridge_reset);
else
ret = reset_control_assert(priv->bridge_reset);
if (ret)
return ret;
/* Allow bridge to be visible to L3 masters or not */
if (priv->remap_mask) {
spin_lock_irqsave(&l3_remap_lock, flags);
l3_remap_shadow |= ALT_L3_REMAP_MPUZERO_MSK;
if (enable)
l3_remap_shadow |= priv->remap_mask;
else
l3_remap_shadow &= ~priv->remap_mask;
ret = regmap_write(priv->l3reg, ALT_L3_REMAP_OFST,
l3_remap_shadow);
spin_unlock_irqrestore(&l3_remap_lock, flags);
}
return ret;
}
static void img_i2s_out_reset(struct img_i2s_out *i2s)
{
int i;
u32 core_ctl, chan_ctl;
core_ctl = img_i2s_out_readl(i2s, IMG_I2S_OUT_CTL) &
~IMG_I2S_OUT_CTL_ME_MASK &
~IMG_I2S_OUT_CTL_DATA_EN_MASK;
if (!i2s->force_clk_active)
core_ctl &= ~IMG_I2S_OUT_CTL_CLK_EN_MASK;
chan_ctl = img_i2s_out_ch_readl(i2s, 0, IMG_I2S_OUT_CH_CTL) &
~IMG_I2S_OUT_CHAN_CTL_ME_MASK;
reset_control_assert(i2s->rst);
reset_control_deassert(i2s->rst);
for (i = 0; i < i2s->max_i2s_chan; i++)
img_i2s_out_ch_writel(i2s, i, chan_ctl, IMG_I2S_OUT_CH_CTL);
for (i = 0; i < i2s->active_channels; i++)
img_i2s_out_ch_enable(i2s, i);
img_i2s_out_writel(i2s, core_ctl, IMG_I2S_OUT_CTL);
img_i2s_out_enable(i2s);
}
static int dwc3_core_init_for_resume(struct dwc3 *dwc)
{
int ret;
ret = reset_control_deassert(dwc->reset);
if (ret)
return ret;
ret = clk_bulk_prepare(dwc->num_clks, dwc->clks);
if (ret)
goto assert_reset;
ret = clk_bulk_enable(dwc->num_clks, dwc->clks);
if (ret)
goto unprepare_clks;
ret = dwc3_core_init(dwc);
if (ret)
goto disable_clks;
return 0;
disable_clks:
clk_bulk_disable(dwc->num_clks, dwc->clks);
unprepare_clks:
clk_bulk_unprepare(dwc->num_clks, dwc->clks);
assert_reset:
reset_control_assert(dwc->reset);
return ret;
}
static void st_rc_hardware_init(struct st_rc_device *dev)
{
int baseclock, freqdiff;
unsigned int rx_max_symbol_per = MAX_SYMB_TIME;
unsigned int rx_sampling_freq_div;
/* Enable the IP */
reset_control_deassert(dev->rstc);
clk_prepare_enable(dev->sys_clock);
baseclock = clk_get_rate(dev->sys_clock);
/* IRB input pins are inverted internally from high to low. */
writel(1, dev->rx_base + IRB_RX_POLARITY_INV);
rx_sampling_freq_div = baseclock / IRB_SAMPLE_FREQ;
writel(rx_sampling_freq_div, dev->base + IRB_SAMPLE_RATE_COMM);
freqdiff = baseclock - (rx_sampling_freq_div * IRB_SAMPLE_FREQ);
if (freqdiff) { /* over clocking, workout the adjustment factors */
dev->overclocking = true;
dev->sample_mult = 1000;
dev->sample_div = baseclock / (10000 * rx_sampling_freq_div);
rx_max_symbol_per = (rx_max_symbol_per * 1000)/dev->sample_div;
}
writel(rx_max_symbol_per, dev->rx_base + IRB_MAX_SYM_PERIOD);
}
static int ade_power_up(struct ade_hw_ctx *ctx)
{
int ret;
ret = clk_prepare_enable(ctx->media_noc_clk);
if (ret) {
DRM_ERROR("failed to enable media_noc_clk (%d)\n", ret);
return ret;
}
ret = reset_control_deassert(ctx->reset);
if (ret) {
DRM_ERROR("failed to deassert reset\n");
return ret;
}
ret = clk_prepare_enable(ctx->ade_core_clk);
if (ret) {
DRM_ERROR("failed to enable ade_core_clk (%d)\n", ret);
return ret;
}
ade_init(ctx);
ctx->power_on = true;
return 0;
}
static int rt288x_wdt_probe(struct platform_device *pdev)
{
struct resource *res;
int ret;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
rt288x_wdt_base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(rt288x_wdt_base))
return PTR_ERR(rt288x_wdt_base);
rt288x_wdt_clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(rt288x_wdt_clk))
return PTR_ERR(rt288x_wdt_clk);
rt288x_wdt_reset = devm_reset_control_get(&pdev->dev, NULL);
if (!IS_ERR(rt288x_wdt_reset))
reset_control_deassert(rt288x_wdt_reset);
rt288x_wdt_freq = clk_get_rate(rt288x_wdt_clk) / RALINK_WDT_PRESCALE;
rt288x_wdt_dev.bootstatus = rt288x_wdt_bootcause();
rt288x_wdt_dev.max_timeout = (0xfffful / rt288x_wdt_freq);
rt288x_wdt_dev.parent = &pdev->dev;
watchdog_init_timeout(&rt288x_wdt_dev, rt288x_wdt_dev.max_timeout,
&pdev->dev);
watchdog_set_nowayout(&rt288x_wdt_dev, nowayout);
ret = watchdog_register_device(&rt288x_wdt_dev);
if (!ret)
dev_info(&pdev->dev, "Initialized\n");
return 0;
}
static void __init sun5i_timer_init(struct device_node *node)
{
struct reset_control *rstc;
void __iomem *timer_base;
struct clk *clk;
int irq;
timer_base = of_io_request_and_map(node, 0, of_node_full_name(node));
if (!timer_base)
panic("Can't map registers");
irq = irq_of_parse_and_map(node, 0);
if (irq <= 0)
panic("Can't parse IRQ");
clk = of_clk_get(node, 0);
if (IS_ERR(clk))
panic("Can't get timer clock");
rstc = of_reset_control_get(node, NULL);
if (!IS_ERR(rstc))
reset_control_deassert(rstc);
sun5i_setup_clocksource(node, timer_base, clk, irq);
sun5i_setup_clockevent(node, timer_base, clk, irq);
}
/* Must be called with clk disabled, and returns with clk enabled */
int tegra_powergate_sequence_power_up(int id, struct clk *clk,
struct reset_control *rst)
{
int ret;
reset_control_assert(rst);
ret = tegra_powergate_power_on(id);
if (ret)
goto err_power;
ret = clk_prepare_enable(clk);
if (ret)
goto err_clk;
udelay(10);
ret = tegra_powergate_remove_clamping(id);
if (ret)
goto err_clamp;
udelay(10);
reset_control_deassert(rst);
return 0;
err_clamp:
clk_disable_unprepare(clk);
err_clk:
tegra_powergate_power_off(id);
err_power:
return ret;
}
static int uniphier_pciephy_init(struct phy *phy)
{
struct uniphier_pciephy_priv *priv = phy_get_drvdata(phy);
int ret;
ret = clk_prepare_enable(priv->clk);
if (ret)
return ret;
ret = reset_control_deassert(priv->rst);
if (ret)
goto out_clk_disable;
uniphier_pciephy_set_param(priv, PCL_PHY_R00,
RX_EQ_ADJ_EN, RX_EQ_ADJ_EN);
uniphier_pciephy_set_param(priv, PCL_PHY_R06, RX_EQ_ADJ,
FIELD_PREP(RX_EQ_ADJ, RX_EQ_ADJ_VAL));
uniphier_pciephy_set_param(priv, PCL_PHY_R26, VCO_CTRL,
FIELD_PREP(VCO_CTRL, VCO_CTRL_INIT_VAL));
usleep_range(1, 10);
uniphier_pciephy_deassert(priv);
usleep_range(1, 10);
return 0;
out_clk_disable:
clk_disable_unprepare(priv->clk);
return ret;
}
static int __init sun5i_timer_init(struct device_node *node)
{
struct reset_control *rstc;
void __iomem *timer_base;
struct clk *clk;
int irq, ret;
timer_base = of_io_request_and_map(node, 0, of_node_full_name(node));
if (IS_ERR(timer_base)) {
pr_err("Can't map registers\n");
return PTR_ERR(timer_base);
}
irq = irq_of_parse_and_map(node, 0);
if (irq <= 0) {
pr_err("Can't parse IRQ\n");
return -EINVAL;
}
clk = of_clk_get(node, 0);
if (IS_ERR(clk)) {
pr_err("Can't get timer clock\n");
return PTR_ERR(clk);
}
rstc = of_reset_control_get(node, NULL);
if (!IS_ERR(rstc))
reset_control_deassert(rstc);
ret = sun5i_setup_clocksource(node, timer_base, clk, irq);
if (ret)
return ret;
return sun5i_setup_clockevent(node, timer_base, clk, irq);
}
static int rockchip_dp_pre_init(struct rockchip_dp_device *dp)
{
reset_control_assert(dp->rst);
usleep_range(10, 20);
reset_control_deassert(dp->rst);
return 0;
}
static int stih407_usb2_pico_ctrl(struct stih407_usb2_picophy *phy_dev)
{
reset_control_deassert(phy_dev->rstc);
return regmap_update_bits(phy_dev->regmap, phy_dev->ctrl,
STIH407_USB_PICOPHY_CTRL_PORT_MASK,
STIH407_USB_PICOPHY_CTRL_PORT_CONF);
}
static void i2c_dw_unprepare_recovery(struct i2c_adapter *adap)
{
struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
i2c_dw_prepare_clk(dev, true);
reset_control_deassert(dev->rst);
i2c_dw_init_master(dev);
}
static int socfpga_dwmac_set_phy_mode(struct socfpga_dwmac *dwmac)
{
struct regmap *sys_mgr_base_addr = dwmac->sys_mgr_base_addr;
int phymode = dwmac->interface;
u32 reg_offset = dwmac->reg_offset;
u32 reg_shift = dwmac->reg_shift;
u32 ctrl, val, module;
switch (phymode) {
case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_ID:
val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
break;
case PHY_INTERFACE_MODE_MII:
case PHY_INTERFACE_MODE_GMII:
val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
break;
default:
dev_err(dwmac->dev, "bad phy mode %d\n", phymode);
return -EINVAL;
}
/* Overwrite val to GMII if splitter core is enabled. The phymode here
* is the actual phy mode on phy hardware, but phy interface from
* EMAC core is GMII.
*/
if (dwmac->splitter_base)
val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
/* Assert reset to the enet controller before changing the phy mode */
if (dwmac->stmmac_rst)
reset_control_assert(dwmac->stmmac_rst);
regmap_read(sys_mgr_base_addr, reg_offset, &ctrl);
ctrl &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << reg_shift);
ctrl |= val << reg_shift;
if (dwmac->f2h_ptp_ref_clk) {
ctrl |= SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2);
regmap_read(sys_mgr_base_addr, SYSMGR_FPGAGRP_MODULE_REG,
&module);
module |= (SYSMGR_FPGAGRP_MODULE_EMAC << (reg_shift / 2));
regmap_write(sys_mgr_base_addr, SYSMGR_FPGAGRP_MODULE_REG,
module);
} else {
ctrl &= ~(SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2));
}
regmap_write(sys_mgr_base_addr, reg_offset, ctrl);
/* Deassert reset for the phy configuration to be sampled by
* the enet controller, and operation to start in requested mode
*/
if (dwmac->stmmac_rst)
reset_control_deassert(dwmac->stmmac_rst);
return 0;
}
static int dwc3_of_simple_resume(struct device *dev)
{
struct dwc3_of_simple *simple = dev_get_drvdata(dev);
if (simple->need_reset)
reset_control_deassert(simple->resets);
return 0;
}
static int st_rproc_start(struct rproc *rproc)
{
struct st_rproc *ddata = rproc->priv;
int err;
regmap_update_bits(ddata->boot_base, ddata->boot_offset,
ddata->config->bootaddr_mask, rproc->bootaddr);
err = clk_enable(ddata->clk);
if (err) {
dev_err(&rproc->dev, "Failed to enable clock\n");
return err;
}
if (ddata->config->sw_reset) {
err = reset_control_deassert(ddata->sw_reset);
if (err) {
dev_err(&rproc->dev, "Failed to deassert S/W Reset\n");
goto sw_reset_fail;
}
}
if (ddata->config->pwr_reset) {
err = reset_control_deassert(ddata->pwr_reset);
if (err) {
dev_err(&rproc->dev, "Failed to deassert Power Reset\n");
goto pwr_reset_fail;
}
}
dev_info(&rproc->dev, "Started from 0x%x\n", rproc->bootaddr);
return 0;
pwr_reset_fail:
if (ddata->config->pwr_reset)
reset_control_assert(ddata->sw_reset);
sw_reset_fail:
clk_disable(ddata->clk);
return err;
}
static int
nvkm_device_tegra_power_up(struct nvkm_device_tegra *tdev)
{
int ret;
if (tdev->vdd) {
ret = regulator_enable(tdev->vdd);
if (ret)
goto err_power;
}
ret = clk_prepare_enable(tdev->clk);
if (ret)
goto err_clk;
if (tdev->clk_ref) {
ret = clk_prepare_enable(tdev->clk_ref);
if (ret)
goto err_clk_ref;
}
ret = clk_prepare_enable(tdev->clk_pwr);
if (ret)
goto err_clk_pwr;
clk_set_rate(tdev->clk_pwr, 204000000);
udelay(10);
reset_control_assert(tdev->rst);
udelay(10);
if (!tdev->pdev->dev.pm_domain) {
ret = tegra_powergate_remove_clamping(TEGRA_POWERGATE_3D);
if (ret)
goto err_clamp;
udelay(10);
}
reset_control_deassert(tdev->rst);
udelay(10);
return 0;
err_clamp:
clk_disable_unprepare(tdev->clk_pwr);
err_clk_pwr:
if (tdev->clk_ref)
clk_disable_unprepare(tdev->clk_ref);
err_clk_ref:
clk_disable_unprepare(tdev->clk);
err_clk:
if (tdev->vdd)
regulator_disable(tdev->vdd);
err_power:
return ret;
}
static int st_dwc3_resume(struct device *dev)
{
struct st_dwc3 *dwc3_data = dev_get_drvdata(dev);
int ret;
pinctrl_pm_select_default_state(dev);
reset_control_deassert(dwc3_data->rstc_pwrdn);
reset_control_deassert(dwc3_data->rstc_rst);
ret = st_dwc3_drd_init(dwc3_data);
if (ret) {
dev_err(dev, "drd initialisation failed\n");
return ret;
}
/* ST glue logic init */
st_dwc3_init(dwc3_data);
return 0;
}
/*
* The 1st USB controller contains some UTMI pad registers that are global for
* all the controllers on the chip. Those registers are also cleared when
* reset is asserted to the 1st controller. This means that the 1st controller
* can only be reset when no other controlled has finished probing. So we'll
* reset the 1st controller before doing any other setup on any of the
* controllers, and then never again.
*
* Since this is a PHY issue, the Tegra PHY driver should probably be doing
* the resetting of the USB controllers. But to keep compatibility with old
* device trees that don't have reset phandles in the PHYs, do it here.
* Those old DTs will be vulnerable to total USB breakage if the 1st EHCI
* device isn't the first one to finish probing, so warn them.
*/
static int tegra_reset_usb_controller(struct platform_device *pdev)
{
struct device_node *phy_np;
struct usb_hcd *hcd = platform_get_drvdata(pdev);
struct tegra_ehci_hcd *tegra =
(struct tegra_ehci_hcd *)hcd_to_ehci(hcd)->priv;
phy_np = of_parse_phandle(pdev->dev.of_node, "nvidia,phy", 0);
if (!phy_np)
return -ENOENT;
if (!usb1_reset_attempted) {
struct reset_control *usb1_reset;
usb1_reset = of_reset_control_get(phy_np, "usb");
if (IS_ERR(usb1_reset)) {
dev_warn(&pdev->dev,
"can't get utmi-pads reset from the PHY\n");
dev_warn(&pdev->dev,
"continuing, but please update your DT\n");
} else {
reset_control_assert(usb1_reset);
udelay(1);
reset_control_deassert(usb1_reset);
}
reset_control_put(usb1_reset);
usb1_reset_attempted = true;
}
if (!of_property_read_bool(phy_np, "nvidia,has-utmi-pad-registers")) {
reset_control_assert(tegra->rst);
udelay(1);
reset_control_deassert(tegra->rst);
}
of_node_put(phy_np);
return 0;
}
static void usb20otg_soft_reset(void *pdata, enum rkusb_rst_flag rst_type)
{
struct dwc_otg_platform_data *usbpdata = pdata;
struct reset_control *rst_otg_h, *rst_otg_p, *rst_otg_c;
rst_otg_h = devm_reset_control_get(usbpdata->dev, "otg_ahb");
rst_otg_p = devm_reset_control_get(usbpdata->dev, "otg_phy");
rst_otg_c = devm_reset_control_get(usbpdata->dev, "otg_controller");
if (IS_ERR(rst_otg_h) || IS_ERR(rst_otg_p) || IS_ERR(rst_otg_c)) {
dev_err(usbpdata->dev, "Fail to get reset control from dts\n");
return;
}
switch(rst_type) {
case RST_POR:
/* PHY reset */
writel(UOC_HIWORD_UPDATE(0x1, 0x3, 0),
RK_GRF_VIRT + RK3036_GRF_UOC0_CON5);
reset_control_assert(rst_otg_p);
udelay(15);
writel(UOC_HIWORD_UPDATE(0x2, 0x3, 0),
RK_GRF_VIRT + RK3036_GRF_UOC0_CON5);
udelay(1500);
reset_control_deassert(rst_otg_p);
udelay(2);
/* Controller reset */
reset_control_assert(rst_otg_c);
reset_control_assert(rst_otg_h);
udelay(2);
reset_control_deassert(rst_otg_c);
reset_control_deassert(rst_otg_h);
break;
default:
break;
}
}
int clk_resume_usb_gxbaby(struct platform_device *pdev,
const char *s_clock_name,
unsigned long usb_peri_reg)
{
struct reset_control *usb_reset;
if (0 == pdev->id) {
usb_reset = p_clk_reset[pdev->id].usb_reset_usb_general;
reset_control_deassert(usb_reset);
usb_reset = p_clk_reset[pdev->id].usb_reset_usb;
reset_control_deassert(usb_reset);
usb_reset = p_clk_reset[pdev->id].usb_reset_usb_to_ddr;
reset_control_deassert(usb_reset);
} else if (1 == pdev->id) {
usb_reset = p_clk_reset[pdev->id].usb_reset_usb_general;
reset_control_deassert(usb_reset);
usb_reset = p_clk_reset[pdev->id].usb_reset_usb;
reset_control_deassert(usb_reset);
usb_reset = p_clk_reset[pdev->id].usb_reset_usb_to_ddr;
reset_control_deassert(usb_reset);
} else {
dev_err(&pdev->dev, "bad usb clk name.\n");
return -1;
}
dmb(4);
return 0;
}
static int sti_tvout_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *node = dev->of_node;
struct sti_tvout *tvout;
struct resource *res;
struct device_node *child_np;
struct component_match *match = NULL;
DRM_INFO("%s\n", __func__);
if (!node)
return -ENODEV;
tvout = devm_kzalloc(dev, sizeof(*tvout), GFP_KERNEL);
if (!tvout)
return -ENOMEM;
tvout->dev = dev;
/* get Memory ressources */
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "tvout-reg");
if (!res) {
DRM_ERROR("Invalid glue resource\n");
return -ENOMEM;
}
tvout->regs = devm_ioremap_nocache(dev, res->start, resource_size(res));
if (!tvout->regs)
return -ENOMEM;
/* get reset resources */
tvout->reset = devm_reset_control_get(dev, "tvout");
/* take tvout out of reset */
if (!IS_ERR(tvout->reset))
reset_control_deassert(tvout->reset);
platform_set_drvdata(pdev, tvout);
of_platform_populate(node, NULL, NULL, dev);
child_np = of_get_next_available_child(node, NULL);
while (child_np) {
component_match_add(dev, &match, compare_of, child_np);
of_node_put(child_np);
child_np = of_get_next_available_child(node, child_np);
}
component_master_add_with_match(dev, &sti_tvout_master_ops, match);
return component_add(dev, &sti_tvout_ops);
}
static int ath10k_ahb_release_reset(struct ath10k *ar)
{
struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
int ret;
if (IS_ERR_OR_NULL(ar_ahb->radio_cold_rst) ||
IS_ERR_OR_NULL(ar_ahb->radio_warm_rst) ||
IS_ERR_OR_NULL(ar_ahb->radio_srif_rst) ||
IS_ERR_OR_NULL(ar_ahb->cpu_init_rst)) {
ath10k_err(ar, "rst ctrl(s) is/are not initialized\n");
return -EINVAL;
}
ret = reset_control_deassert(ar_ahb->radio_cold_rst);
if (ret) {
ath10k_err(ar, "failed to deassert radio cold rst: %d\n", ret);
return ret;
}
ret = reset_control_deassert(ar_ahb->radio_warm_rst);
if (ret) {
ath10k_err(ar, "failed to deassert radio warm rst: %d\n", ret);
return ret;
}
ret = reset_control_deassert(ar_ahb->radio_srif_rst);
if (ret) {
ath10k_err(ar, "failed to deassert radio srif rst: %d\n", ret);
return ret;
}
ret = reset_control_deassert(ar_ahb->cpu_init_rst);
if (ret) {
ath10k_err(ar, "failed to deassert cpu init rst: %d\n", ret);
return ret;
}
return 0;
}
static int sti_hqvdp_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *vtg_np;
struct sti_hqvdp *hqvdp;
struct resource *res;
DRM_DEBUG_DRIVER("\n");
hqvdp = devm_kzalloc(dev, sizeof(*hqvdp), GFP_KERNEL);
if (!hqvdp) {
DRM_ERROR("Failed to allocate HQVDP context\n");
return -ENOMEM;
}
hqvdp->dev = dev;
/* Get Memory resources */
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (res == NULL) {
DRM_ERROR("Get memory resource failed\n");
return -ENXIO;
}
hqvdp->regs = devm_ioremap(dev, res->start, resource_size(res));
if (hqvdp->regs == NULL) {
DRM_ERROR("Register mapping failed\n");
return -ENXIO;
}
/* Get clock resources */
hqvdp->clk = devm_clk_get(dev, "hqvdp");
hqvdp->clk_pix_main = devm_clk_get(dev, "pix_main");
if (IS_ERR(hqvdp->clk) || IS_ERR(hqvdp->clk_pix_main)) {
DRM_ERROR("Cannot get clocks\n");
return -ENXIO;
}
/* Get reset resources */
hqvdp->reset = devm_reset_control_get(dev, "hqvdp");
if (!IS_ERR(hqvdp->reset))
reset_control_deassert(hqvdp->reset);
vtg_np = of_parse_phandle(pdev->dev.of_node, "st,vtg", 0);
if (vtg_np)
hqvdp->vtg = of_vtg_find(vtg_np);
of_node_put(vtg_np);
platform_set_drvdata(pdev, hqvdp);
return component_add(&pdev->dev, &sti_hqvdp_ops);
}
static int tegra_ahci_power_on(struct ahci_host_priv *hpriv)
{
struct tegra_ahci_priv *tegra = hpriv->plat_data;
int ret;
ret = regulator_bulk_enable(ARRAY_SIZE(tegra->supplies),
tegra->supplies);
if (ret)
return ret;
ret = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_SATA,
tegra->sata_clk,
tegra->sata_rst);
if (ret)
goto disable_regulators;
reset_control_assert(tegra->sata_oob_rst);
reset_control_assert(tegra->sata_cold_rst);
ret = ahci_platform_enable_resources(hpriv);
if (ret)
goto disable_power;
reset_control_deassert(tegra->sata_cold_rst);
reset_control_deassert(tegra->sata_oob_rst);
return 0;
disable_power:
clk_disable_unprepare(tegra->sata_clk);
tegra_powergate_power_off(TEGRA_POWERGATE_SATA);
disable_regulators:
regulator_bulk_disable(ARRAY_SIZE(tegra->supplies), tegra->supplies);
return ret;
}
static void usb20ehci_soft_reset(void *pdata, enum rkusb_rst_flag rst_type)
{
struct rkehci_platform_data *usbpdata = pdata;
struct reset_control *rst_host_h, *rst_host_p, *rst_host_c;
rst_host_h = devm_reset_control_get(usbpdata->dev, "host_ahb");
rst_host_p = devm_reset_control_get(usbpdata->dev, "host_phy");
rst_host_c = devm_reset_control_get(usbpdata->dev, "host_controller");
if (IS_ERR(rst_host_h) || IS_ERR(rst_host_p) || IS_ERR(rst_host_c)) {
dev_err(usbpdata->dev, "Fail to get reset control from dts\n");
return;
}
switch (rst_type) {
case RST_POR:
/* PHY reset */
uoc_write(UOC_HIWORD_UPDATE(0x1, 0x3, 0), 0x728);
reset_control_assert(rst_host_p);
udelay(15);
uoc_write(UOC_HIWORD_UPDATE(0x2, 0x3, 0), 0x728);
udelay(1500);
reset_control_deassert(rst_host_p);
/* Controller reset */
reset_control_assert(rst_host_c);
reset_control_assert(rst_host_h);
udelay(5);
reset_control_deassert(rst_host_c);
reset_control_deassert(rst_host_h);
break;
default:
break;
}
}
