static void error_print(CHAR16* msg, EFI_STATUS* status)
{
Print(msg);
if (status){
Print(L"EFI_STATUS = %d, %s\n", *status, print_status_msg(*status));
}
reset_system(EFI_SUCCESS);
}
void vdp1_framebuffer_write_test()
{
volatile u16* framebuffer_ptr = (volatile u16*)0x25C80000;
int i;
vdp_vsync();
VDP1_REG_FBCR = 3;
//we have to wait a little bit so we don't write to both framebuffers
vdp_wait_hblankout();
for (i = 0; i < 128; i += 4)
{
framebuffer_ptr[i + 0] = 0xdead;
framebuffer_ptr[i + 1] = 0xbeef;
framebuffer_ptr[i + 2] = 0xfeed;
framebuffer_ptr[i + 3] = 0xcafe;
}
#ifdef BUILD_AUTOMATED_TESTING
auto_test_get_framebuffer();
#else
for (;;)
{
while (!(VDP2_REG_TVSTAT & 8))
{
ud_check(0);
}
while (VDP2_REG_TVSTAT & 8) {}
if (per[0].but_push_once & PAD_START)
break;
if (per[0].but_push_once & PAD_X)
{
ar_menu();
}
if (per[0].but_push_once & PAD_Y)
{
reset_system();
}
}
#endif
}
EFI_STATUS efi_main(EFI_HANDLE image_handle, EFI_SYSTEM_TABLE* system_table)
{
init(image_handle, system_table);
Print(L"When you press any key, the system will reboot.\n");
Print(L"\n");
EFI_FILE* efi_file = open_print_info(L"\\result.txt");
write_print_info1(efi_file, L"Firmware Vendor: %s", system_table->FirmwareVendor);
write_print_info2(efi_file, L"Firmware Revision: 0x%x", system_table->FirmwareRevision);
UINT32 rev_1 = (system_table->Hdr.Revision & 0xffff0000) >> 16;
UINT32 rev_2 = system_table->Hdr.Revision & 0x0000ffff;
write_print_info3(efi_file, L"UEFI Version: %d.%d", rev_1, rev_2);
// EAX, EBX, ECX and EDX
int cpu_info[4] = { 0 };
__cpuid(cpu_info, 0x07);
write_print_info1(efi_file, L"SGX: %s", GET_CPU_INFO(cpu_info, CPU_INFO_EBX, 2));
write_print_info1(efi_file, L"SMEP: %s", GET_CPU_INFO(cpu_info, CPU_INFO_EBX, 7));
write_print_info1(efi_file, L"INVPCID: %s", GET_CPU_INFO(cpu_info, CPU_INFO_EBX, 10));
write_print_info1(efi_file, L"MPX: %s", GET_CPU_INFO(cpu_info, CPU_INFO_EBX, 14));
write_print_info1(efi_file, L"SMAP: %s", GET_CPU_INFO(cpu_info, CPU_INFO_EBX, 20));
write_print_info1(efi_file, L"CLFLUSHOPT: %s", GET_CPU_INFO(cpu_info, CPU_INFO_EBX, 23));
write_print_info1(efi_file, L"PREFETCHWT1: %s", GET_CPU_INFO(cpu_info, CPU_INFO_ECX, 1));
write_print_info1(efi_file, L"PKU: %s", GET_CPU_INFO(cpu_info, CPU_INFO_ECX, 3));
write_print_info1(efi_file, L"OSPKE: %s", GET_CPU_INFO(cpu_info, CPU_INFO_ECX, 4));
memset(cpu_info, 0, sizeof(cpu_info));
__cpuid(cpu_info, 0x06);
write_print_info1(
efi_file,
L"ARAT. APIC-Timer-always-running feature: %s",
GET_CPU_INFO(cpu_info, CPU_INFO_EAX, 2)
);
memset(cpu_info, 0, sizeof(cpu_info));
__cpuid(cpu_info, 0x80000007);
write_print_info1(efi_file, L"Invariant TSC: %s", GET_CPU_INFO(cpu_info, CPU_INFO_EDX, 8));
memset(cpu_info, 0, sizeof(cpu_info));
__cpuid(cpu_info, 0x01);
write_print_info1(efi_file, L"x2APIC: %s", GET_CPU_INFO(cpu_info, CPU_INFO_ECX, 21));
write_print_info1(efi_file, L"TSC-Deadline: %s", GET_CPU_INFO(cpu_info, CPU_INFO_ECX, 24));
close_print_info(efi_file);
reset_system(EFI_SUCCESS);
return EFI_SUCCESS;
}
void raminit(struct mrc_params *mp, int prev_sleep_state)
{
int ret;
mrc_wrapper_entry_t mrc_entry;
const struct mrc_saved_data *cache;
/* Fill in default entries. */
mp->version = MRC_PARAMS_VER;
mp->console_out = &send_to_console;
mp->prev_sleep_state = prev_sleep_state;
mp->rmt_enabled = IS_ENABLED(CONFIG_MRC_RMT);
/* Default to 2GiB IO hole. */
if (!mp->io_hole_mb)
mp->io_hole_mb = 2048;
if (vboot_recovery_mode_enabled()) {
printk(BIOS_DEBUG, "Recovery mode: not using MRC cache.\n");
} else if (!mrc_cache_get_current(&cache)) {
mp->saved_data_size = cache->size;
mp->saved_data = &cache->data[0];
} else if (prev_sleep_state == ACPI_S3) {
/* If waking from S3 and no cache then. */
printk(BIOS_DEBUG, "No MRC cache found in S3 resume path.\n");
post_code(POST_RESUME_FAILURE);
reset_system();
} else {
printk(BIOS_DEBUG, "No MRC cache found.\n");
#if CONFIG_EC_GOOGLE_CHROMEEC
if (prev_sleep_state == ACPI_S0) {
/* Ensure EC is running RO firmware. */
google_chromeec_check_ec_image(EC_IMAGE_RO);
}
#endif
}
/* Determine if mrc.bin is in the cbfs. */
if (cbfs_boot_map_with_leak("mrc.bin", CBFS_TYPE_MRC, NULL) == NULL) {
printk(BIOS_DEBUG, "Couldn't find mrc.bin\n");
return;
}
/*
* The entry point is currently the first instruction. Handle the
* case of an ELF file being put in the cbfs by setting the entry
* to the CONFIG_MRC_BIN_ADDRESS.
*/
mrc_entry = (void *)(uintptr_t)CONFIG_MRC_BIN_ADDRESS;
if (mp->mainboard.dram_info_location == DRAM_INFO_SPD_SMBUS)
enable_smbus();
ret = mrc_entry(mp);
print_dram_info();
if (prev_sleep_state != ACPI_S3) {
cbmem_initialize_empty();
} else if (cbmem_initialize()) {
#if CONFIG_HAVE_ACPI_RESUME
printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n");
/* Failed S3 resume, reset to come up cleanly */
reset_system();
#endif
}
printk(BIOS_DEBUG, "MRC Wrapper returned %d\n", ret);
printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", mp->data_to_save,
mp->data_to_save_size);
if (mp->data_to_save != NULL && mp->data_to_save_size > 0)
mrc_cache_stash_data(mp->data_to_save, mp->data_to_save_size);
}
void vdp1_clip_test()
{
int gouraud_table_address = 0x40000;
u32 clipping_mode = 3;//outside
u16* p = (u16 *)(0x25C00000 + gouraud_table_address);
auto_test_sub_test_start("Clipping test");
VDP1_REG_FBCR = 0;
vdp_start_draw_list();
sprite_struct quad;
quad.x = 0;
quad.y = 0;
vdp_local_coordinate(&quad);
//system clipping
quad.x = 319 - 8;
quad.y = 223 - 8;
vdp_system_clipping(&quad);
//user clipping
quad.x = 8;
quad.y = 8;
quad.x2 = 319 - 16;
quad.y2 = 223 - 16;
vdp_user_clipping(&quad);
//fullscreen polygon
quad.x = 319;
quad.y = 0;
quad.x2 = 319;
quad.y2 = 223;
quad.x3 = 0;
quad.y3 = 223;
quad.x4 = 0;
quad.y4 = 0;
quad.bank = RGB16(0x10, 0x10, 0x10);//gray
quad.gouraud_addr = gouraud_table_address;
quad.attr = (clipping_mode << 9) | 4;//use gouraud shading
//red, green, blue, and white
p[0] = RGB16(31, 0, 0);
p[1] = RGB16(0, 31, 0);
p[2] = RGB16(0, 0, 31);
p[3] = RGB16(31, 31, 31);
vdp_draw_polygon(&quad);
vdp_end_draw_list();
vdp_vsync();
VDP1_REG_FBCR = 3;
vdp_vsync();
vdp_vsync();
#ifdef BUILD_AUTOMATED_TESTING
auto_test_get_framebuffer();
#else
for (;;)
{
while (!(VDP2_REG_TVSTAT & 8))
{
ud_check(0);
}
while (VDP2_REG_TVSTAT & 8)
{
}
if (per[0].but_push_once & PAD_A)
{
clipping_mode = 0; //clipping disabled
}
if (per[0].but_push_once & PAD_B)
{
clipping_mode = 2; //inside drawing mode
}
if (per[0].but_push_once & PAD_C)
{
clipping_mode = 3; //outside drawing mode
}
if (per[0].but_push_once & PAD_START)
break;
if (per[0].but_push_once & PAD_X)
{
ar_menu();
}
if (per[0].but_push_once & PAD_Y)
{
reset_system();
}
}
#endif
}
void ramstage_cache_invalid(struct ramstage_cache *cache)
{
#if CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE
reset_system();
#endif
}
void romstage_common(const struct romstage_params *params)
{
int boot_mode;
int wake_from_s3;
struct romstage_handoff *handoff;
#if CONFIG_COLLECT_TIMESTAMPS
uint64_t start_romstage_time;
uint64_t before_dram_time;
uint64_t after_dram_time;
uint64_t base_time =
(uint64_t)pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) << 32 ||
pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc);
#endif
#if CONFIG_COLLECT_TIMESTAMPS
start_romstage_time = timestamp_get();
#endif
if (params->bist == 0)
enable_lapic();
wake_from_s3 = early_pch_init(params->gpio_map, params->rcba_config);
#if CONFIG_EC_GOOGLE_CHROMEEC
/* Ensure the EC is in the right mode for recovery */
google_chromeec_early_init();
#endif
/* Halt if there was a built in self test failure */
report_bist_failure(params->bist);
/* Perform some early chipset initialization required
* before RAM initialization can work
*/
haswell_early_initialization(HASWELL_MOBILE);
printk(BIOS_DEBUG, "Back from haswell_early_initialization()\n");
if (wake_from_s3) {
#if CONFIG_HAVE_ACPI_RESUME
printk(BIOS_DEBUG, "Resume from S3 detected.\n");
#else
printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
wake_from_s3 = 0;
#endif
}
/* There are hard coded assumptions of 2 meaning s3 wake. Normalize
* the users of the 2 literal here based off wake_from_s3. */
boot_mode = wake_from_s3 ? 2 : 0;
/* Prepare USB controller early in S3 resume */
if (wake_from_s3)
enable_usb_bar();
post_code(0x3a);
params->pei_data->boot_mode = boot_mode;
#if CONFIG_COLLECT_TIMESTAMPS
before_dram_time = timestamp_get();
#endif
report_platform_info();
if (params->copy_spd != NULL)
params->copy_spd(params->pei_data);
sdram_initialize(params->pei_data);
#if CONFIG_COLLECT_TIMESTAMPS
after_dram_time = timestamp_get();
#endif
post_code(0x3b);
intel_early_me_status();
quick_ram_check();
post_code(0x3e);
if (!wake_from_s3) {
cbmem_initialize_empty();
/* Save data returned from MRC on non-S3 resumes. */
save_mrc_data(params->pei_data);
} else if (cbmem_initialize()) {
#if CONFIG_HAVE_ACPI_RESUME
/* Failed S3 resume, reset to come up cleanly */
reset_system();
#endif
}
handoff = romstage_handoff_find_or_add();
if (handoff != NULL)
handoff->s3_resume = wake_from_s3;
else
printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
post_code(0x3f);
#if CONFIG_CHROMEOS
init_chromeos(boot_mode);
#endif
#if CONFIG_COLLECT_TIMESTAMPS
timestamp_init(base_time);
timestamp_add(TS_START_ROMSTAGE, start_romstage_time );
timestamp_add(TS_BEFORE_INITRAM, before_dram_time );
timestamp_add(TS_AFTER_INITRAM, after_dram_time );
timestamp_add_now(TS_END_ROMSTAGE);
#endif
}
void romstage_common(const struct romstage_params *params)
{
int boot_mode;
int wake_from_s3;
timestamp_init(get_initial_timestamp());
timestamp_add_now(TS_START_ROMSTAGE);
if (params->bist == 0)
enable_lapic();
wake_from_s3 = early_pch_init(params->gpio_map, params->rcba_config);
#if CONFIG_EC_GOOGLE_CHROMEEC
/* Ensure the EC is in the right mode for recovery */
google_chromeec_early_init();
#endif
/* Halt if there was a built in self test failure */
report_bist_failure(params->bist);
/* Perform some early chipset initialization required
* before RAM initialization can work
*/
haswell_early_initialization(HASWELL_MOBILE);
printk(BIOS_DEBUG, "Back from haswell_early_initialization()\n");
if (wake_from_s3) {
#if CONFIG_HAVE_ACPI_RESUME
printk(BIOS_DEBUG, "Resume from S3 detected.\n");
#else
printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
wake_from_s3 = 0;
#endif
}
/* There are hard coded assumptions of 2 meaning s3 wake. Normalize
* the users of the 2 literal here based off wake_from_s3. */
boot_mode = wake_from_s3 ? 2 : 0;
/* Prepare USB controller early in S3 resume */
if (wake_from_s3)
enable_usb_bar();
post_code(0x3a);
params->pei_data->boot_mode = boot_mode;
timestamp_add_now(TS_BEFORE_INITRAM);
report_platform_info();
if (params->copy_spd != NULL)
params->copy_spd(params->pei_data);
sdram_initialize(params->pei_data);
timestamp_add_now(TS_AFTER_INITRAM);
post_code(0x3b);
intel_early_me_status();
quick_ram_check();
post_code(0x3e);
if (!wake_from_s3) {
cbmem_initialize_empty();
/* Save data returned from MRC on non-S3 resumes. */
save_mrc_data(params->pei_data);
} else if (cbmem_initialize()) {
#if CONFIG_HAVE_ACPI_RESUME
/* Failed S3 resume, reset to come up cleanly */
reset_system();
#endif
}
romstage_handoff_init(wake_from_s3);
post_code(0x3f);
if (IS_ENABLED(CONFIG_LPC_TPM))
init_tpm(wake_from_s3);
}
/**
* reset cpu by dog's time-out
*
*/
void machine_reset()
{
reset_system();
}
