static int rk3288_sys_set_power_domain(enum pmu_power_domain pd, bool on) { u32 clks_ungating[RK3288_CRU_CLKGATES_CON_CNT]; u32 clks_save[RK3288_CRU_CLKGATES_CON_CNT]; u32 i, ret; for (i = 0; i < RK3288_CRU_CLKGATES_CON_CNT; i++) { clks_save[i] = cru_readl(RK3288_CRU_CLKGATES_CON(i)); clks_ungating[i] = 0; } switch (pd) { case PD_GPU: /* gpu */ clks_ungating[5] = 1 << 7; /* aclk_gpu */ clks_ungating[18] = 1 << 0; break; case PD_VIDEO: /* aclk_vdpu_src hclk_vpu aclk_vepu_src */ clks_ungating[3] = 1 << 11 | 1 << 10 | 1 << 9; /* hclk_video aclk_video */ clks_ungating[9] = 1 << 1 | 1 << 0; break; case PD_VIO: /* aclk_lcdc0/1_src dclk_lcdc0/1_src rga_core aclk_rga_src */ /* edp_24m edp isp isp_jpeg */ clks_ungating[3] = 1 << 0 | 1 << 1 | 1 << 2 | 1 << 3 | 1 << 4 | 1 << 5 | 1 << 12 | 1 << 13 | 1 << 14 | 1 << 15; clks_ungating[15] = 0xffff; clks_ungating[16] = 0x0fff; break; case PD_HEVC: /* hevc_core hevc_cabac aclk_hevc */ clks_ungating[13] = 1 << 15 | 1 << 14 | 1 << 13; break; #if 0 case PD_CS: clks_ungating[12] = 1 << 11 | 1 < 10 | 1 << 9 | 1 << 8; break; #endif default: break; } for (i = 0; i < RK3288_CRU_CLKGATES_CON_CNT; i++) { if (clks_ungating[i]) cru_writel(clks_ungating[i] << 16, RK3288_CRU_CLKGATES_CON(i)); } ret = rk3288_pmu_set_power_domain(pd, on); for (i = 0; i < RK3288_CRU_CLKGATES_CON_CNT; i++) { if (clks_ungating[i]) cru_writel(clks_save[i] | 0xffff0000, RK3288_CRU_CLKGATES_CON(i)); } return ret; }
int rk3288_sys_set_power_domain(enum pmu_power_domain pd, bool on) { u32 clks_ungating[RK3288_CRU_CLKGATES_CON_CNT]; u32 clks_save[RK3288_CRU_CLKGATES_CON_CNT]; u32 i,ret; for(i=0;i<RK3288_CRU_CLKGATES_CON_CNT;i++) { clks_save[i]=cru_readl(RK3288_CRU_CLKGATES_CON(i)); clks_ungating[i]=0; } switch(pd) { case PD_GPU: clks_ungating[5]=0x1<<7; break; case PD_VIDEO: clks_ungating[3]=0x1<<11|0x1<<10|0x1<<9; break; case PD_VIO: clks_ungating[3]=0x1<<0|0x1<<2|0x1<<5|0x1<<4|0x1<<1|0x1<<3|0x1<<12|0x1<<13 |0x1<<14|0x1<<15|0x1<<12|0x1<<11; break; case PD_HEVC: clks_ungating[13]=0x1<<15|0x1<<14|0x1<<13; break; #if 0 case PD_CS: clks_ungating[12]=0x1<<11|0x1<10|0x1<<9|0x1<<8; break; #endif default: break; } for(i=0;i<RK3288_CRU_CLKGATES_CON_CNT;i++) { if(clks_ungating[i]) cru_writel(clks_ungating[i]<<16,RK3288_CRU_CLKGATES_CON(i)); } ret=rk3288_pmu_set_power_domain(pd,on); for(i=0;i<RK3288_CRU_CLKGATES_CON_CNT;i++) { if(clks_ungating[i]) cru_writel(clks_save[i]|0xffff0000,RK3288_CRU_CLKGATES_CON(i)); } return ret; }