static void __init rk3288_clk_init(struct device_node *np) { void __iomem *reg_base; struct clk *clk; reg_base = of_iomap(np, 0); if (!reg_base) { pr_err("%s: could not map cru region\n", __func__); return; } rockchip_clk_init(np, reg_base, CLK_NR_CLKS); /* xin12m is created by an cru-internal divider */ clk = clk_register_fixed_factor(NULL, "xin12m", "xin24m", 0, 1, 2); if (IS_ERR(clk)) pr_warn("%s: could not register clock xin12m: %ld\n", __func__, PTR_ERR(clk)); clk = clk_register_fixed_factor(NULL, "usb480m", "xin24m", 0, 20, 1); if (IS_ERR(clk)) pr_warn("%s: could not register clock usb480m: %ld\n", __func__, PTR_ERR(clk)); clk = clk_register_fixed_factor(NULL, "hclk_vcodec_pre", "hclk_vcodec_pre_v", 0, 1, 4); if (IS_ERR(clk)) pr_warn("%s: could not register clock hclk_vcodec_pre: %ld\n", __func__, PTR_ERR(clk)); /* Watchdog pclk is controlled by RK3288_SGRF_SOC_CON0[1]. */ clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_pd_alive", 0, 1, 1); if (IS_ERR(clk)) pr_warn("%s: could not register clock pclk_wdt: %ld\n", __func__, PTR_ERR(clk)); else rockchip_clk_add_lookup(clk, PCLK_WDT); rockchip_clk_register_plls(rk3288_pll_clks, ARRAY_SIZE(rk3288_pll_clks), RK3288_GRF_SOC_STATUS1); rockchip_clk_register_branches(rk3288_clk_branches, ARRAY_SIZE(rk3288_clk_branches)); rockchip_clk_protect_critical(rk3288_critical_clocks, ARRAY_SIZE(rk3288_critical_clocks)); rockchip_clk_register_armclk(ARMCLK, "armclk", mux_armclk_p, ARRAY_SIZE(mux_armclk_p), &rk3288_cpuclk_data, rk3288_cpuclk_rates, ARRAY_SIZE(rk3288_cpuclk_rates)); rockchip_register_softrst(np, 12, reg_base + RK3288_SOFTRST_CON(0), ROCKCHIP_SOFTRST_HIWORD_MASK); rockchip_register_restart_notifier(RK3288_GLB_SRST_FST); rk3288_clk_sleep_init(reg_base); }
static void __init rk3368_clk_init(struct device_node *np) { struct rockchip_clk_provider *ctx; void __iomem *reg_base; struct clk *clk; reg_base = of_iomap(np, 0); if (!reg_base) { pr_err("%s: could not map cru region\n", __func__); return; } ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); if (IS_ERR(ctx)) { pr_err("%s: rockchip clk init failed\n", __func__); iounmap(reg_base); return; } /* Watchdog pclk is controlled by sgrf_soc_con3[7]. */ clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_pd_alive", 0, 1, 1); if (IS_ERR(clk)) pr_warn("%s: could not register clock pclk_wdt: %ld\n", __func__, PTR_ERR(clk)); else rockchip_clk_add_lookup(ctx, clk, PCLK_WDT); rockchip_clk_register_plls(ctx, rk3368_pll_clks, ARRAY_SIZE(rk3368_pll_clks), RK3368_GRF_SOC_STATUS0); rockchip_clk_register_branches(ctx, rk3368_clk_branches, ARRAY_SIZE(rk3368_clk_branches)); rockchip_clk_protect_critical(rk3368_critical_clocks, ARRAY_SIZE(rk3368_critical_clocks)); rockchip_clk_register_armclk(ctx, ARMCLKB, "armclkb", mux_armclkb_p, ARRAY_SIZE(mux_armclkb_p), &rk3368_cpuclkb_data, rk3368_cpuclkb_rates, ARRAY_SIZE(rk3368_cpuclkb_rates)); rockchip_clk_register_armclk(ctx, ARMCLKL, "armclkl", mux_armclkl_p, ARRAY_SIZE(mux_armclkl_p), &rk3368_cpuclkl_data, rk3368_cpuclkl_rates, ARRAY_SIZE(rk3368_cpuclkl_rates)); rockchip_register_softrst(np, 15, reg_base + RK3368_SOFTRST_CON(0), ROCKCHIP_SOFTRST_HIWORD_MASK); rockchip_register_restart_notifier(ctx, RK3368_GLB_SRST_FST, NULL); rockchip_clk_of_add_provider(np, ctx); }
void __init rockchip_clk_register_armclk(unsigned int lookup_id, const char *name, const char *const *parent_names, u8 num_parents, const struct rockchip_cpuclk_reg_data *reg_data, const struct rockchip_cpuclk_rate_table *rates, int nrates) { struct clk *clk; clk = rockchip_clk_register_cpuclk(name, parent_names, num_parents, reg_data, rates, nrates, reg_base, &clk_lock); if (IS_ERR(clk)) { pr_err("%s: failed to register clock %s: %ld\n", __func__, name, PTR_ERR(clk)); return; } rockchip_clk_add_lookup(clk, lookup_id); }
void __init rockchip_clk_register_plls(struct rockchip_pll_clock *list, unsigned int nr_pll, int grf_lock_offset) { struct clk *clk; int idx; for (idx = 0; idx < nr_pll; idx++, list++) { clk = rockchip_clk_register_pll(list->type, list->name, list->parent_names, list->num_parents, reg_base, list->con_offset, grf_lock_offset, list->lock_shift, list->mode_offset, list->mode_shift, list->rate_table, list->pll_flags, &clk_lock); if (IS_ERR(clk)) { pr_err("%s: failed to register clock %s\n", __func__, list->name); continue; } rockchip_clk_add_lookup(clk, list->id); } }
void __init rockchip_clk_register_branches( struct rockchip_clk_branch *list, unsigned int nr_clk) { struct clk *clk = NULL; unsigned int idx; unsigned long flags; for (idx = 0; idx < nr_clk; idx++, list++) { flags = list->flags; /* catch simple muxes */ switch (list->branch_type) { case branch_mux: clk = clk_register_mux(NULL, list->name, list->parent_names, list->num_parents, flags, reg_base + list->muxdiv_offset, list->mux_shift, list->mux_width, list->mux_flags, &clk_lock); break; case branch_divider: if (list->div_table) clk = clk_register_divider_table(NULL, list->name, list->parent_names[0], flags, reg_base + list->muxdiv_offset, list->div_shift, list->div_width, list->div_flags, list->div_table, &clk_lock); else clk = clk_register_divider(NULL, list->name, list->parent_names[0], flags, reg_base + list->muxdiv_offset, list->div_shift, list->div_width, list->div_flags, &clk_lock); break; case branch_fraction_divider: clk = rockchip_clk_register_frac_branch(list->name, list->parent_names, list->num_parents, reg_base, list->muxdiv_offset, list->div_flags, list->gate_offset, list->gate_shift, list->gate_flags, flags, list->child, &clk_lock); break; case branch_gate: flags |= CLK_SET_RATE_PARENT; clk = clk_register_gate(NULL, list->name, list->parent_names[0], flags, reg_base + list->gate_offset, list->gate_shift, list->gate_flags, &clk_lock); break; case branch_composite: clk = rockchip_clk_register_branch(list->name, list->parent_names, list->num_parents, reg_base, list->muxdiv_offset, list->mux_shift, list->mux_width, list->mux_flags, list->div_shift, list->div_width, list->div_flags, list->div_table, list->gate_offset, list->gate_shift, list->gate_flags, flags, &clk_lock); break; case branch_mmc: clk = rockchip_clk_register_mmc( list->name, list->parent_names, list->num_parents, reg_base + list->muxdiv_offset, list->div_shift ); break; case branch_inverter: clk = rockchip_clk_register_inverter( list->name, list->parent_names, list->num_parents, reg_base + list->muxdiv_offset, list->div_shift, list->div_flags, &clk_lock); break; case branch_factor: clk = rockchip_clk_register_factor_branch( list->name, list->parent_names, list->num_parents, reg_base, list->div_shift, list->div_width, list->gate_offset, list->gate_shift, list->gate_flags, flags, &clk_lock); break; } /* none of the cases above matched */ if (!clk) { pr_err("%s: unknown clock type %d\n", __func__, list->branch_type); continue; } if (IS_ERR(clk)) { pr_err("%s: failed to register clock %s: %ld\n", __func__, list->name, PTR_ERR(clk)); continue; } rockchip_clk_add_lookup(clk, list->id); } }
static struct clk *rockchip_clk_register_frac_branch(const char *name, const char *const *parent_names, u8 num_parents, void __iomem *base, int muxdiv_offset, u8 div_flags, int gate_offset, u8 gate_shift, u8 gate_flags, unsigned long flags, struct rockchip_clk_branch *child, spinlock_t *lock) { struct rockchip_clk_frac *frac; struct clk *clk; struct clk_gate *gate = NULL; struct clk_fractional_divider *div = NULL; const struct clk_ops *div_ops = NULL, *gate_ops = NULL; if (muxdiv_offset < 0) return ERR_PTR(-EINVAL); if (child && child->branch_type != branch_mux) { pr_err("%s: fractional child clock for %s can only be a mux\n", __func__, name); return ERR_PTR(-EINVAL); } frac = kzalloc(sizeof(*frac), GFP_KERNEL); if (!frac) return ERR_PTR(-ENOMEM); if (gate_offset >= 0) { gate = &frac->gate; gate->flags = gate_flags; gate->reg = base + gate_offset; gate->bit_idx = gate_shift; gate->lock = lock; gate_ops = &clk_gate_ops; } div = &frac->div; div->flags = div_flags; div->reg = base + muxdiv_offset; div->mshift = 16; div->mwidth = 16; div->mmask = GENMASK(div->mwidth - 1, 0) << div->mshift; div->nshift = 0; div->nwidth = 16; div->nmask = GENMASK(div->nwidth - 1, 0) << div->nshift; div->lock = lock; div_ops = &clk_fractional_divider_ops; clk = clk_register_composite(NULL, name, parent_names, num_parents, NULL, NULL, &div->hw, div_ops, gate ? &gate->hw : NULL, gate_ops, flags | CLK_SET_RATE_UNGATE); if (IS_ERR(clk)) { kfree(frac); return clk; } if (child) { struct clk_mux *frac_mux = &frac->mux; struct clk_init_data init; struct clk *mux_clk; int i, ret; frac->mux_frac_idx = -1; for (i = 0; i < child->num_parents; i++) { if (!strcmp(name, child->parent_names[i])) { pr_debug("%s: found fractional parent in mux at pos %d\n", __func__, i); frac->mux_frac_idx = i; break; } } frac->mux_ops = &clk_mux_ops; frac->clk_nb.notifier_call = rockchip_clk_frac_notifier_cb; frac_mux->reg = base + child->muxdiv_offset; frac_mux->shift = child->mux_shift; frac_mux->mask = BIT(child->mux_width) - 1; frac_mux->flags = child->mux_flags; frac_mux->lock = lock; frac_mux->hw.init = &init; init.name = child->name; init.flags = child->flags | CLK_SET_RATE_PARENT; init.ops = frac->mux_ops; init.parent_names = child->parent_names; init.num_parents = child->num_parents; mux_clk = clk_register(NULL, &frac_mux->hw); if (IS_ERR(mux_clk)) return clk; rockchip_clk_add_lookup(mux_clk, child->id); /* notifier on the fraction divider to catch rate changes */ if (frac->mux_frac_idx >= 0) { ret = clk_notifier_register(clk, &frac->clk_nb); if (ret) pr_err("%s: failed to register clock notifier for %s\n", __func__, name); } else { pr_warn("%s: could not find %s as parent of %s, rate changes may not work\n", __func__, name, child->name); } } return clk; }