C++ (Cpp) rsb_reg_writel Examples

Example #1

File: rsb_spl.c Project: carpecarp/CC-A80-u-boot

static void rsb_set_clk(u32 sck)
{
	u32 src_clk = 0;
	u32 div = 0;
	u32 cd_odly = 0;
	u32 rval = 0;

	src_clk = 24000000;

	div = src_clk/sck/2;
	if(0==div){
		div = 1;
		rsb_printk("Source clock is too low\n");
	}else if(div>256){
		div = 256;
		rsb_printk("Source clock is too high\n");
	}
	div--;
	cd_odly = div >> 1;
	//cd_odly = 1;
	if(!cd_odly)
		cd_odly = 1;
	rval = div | (cd_odly << 8);
	rsb_reg_writel(rval, RSB_REG_CCR);
}

Example #2

File: rsb_spl.c Project: carpecarp/CC-A80-u-boot

static void rsb_clock_enable(void)
{
//	r_prcm_clock_enable(R_RSB_CKID);
	rsb_reg_writel(rsb_reg_readl(SUNXI_RPRCM_BASE + 0x28)|(0x1U << 3),SUNXI_RPRCM_BASE + 0x28);
}

Example #3

File: rsb_spl.c Project: carpecarp/CC-A80-u-boot

static void rsb_cfg_io(void)
{
    unsigned int reg_val;
    //note:
    //make sure cpus pio is opened.
    //sram_area_init has opened cpus pio, so There is no need to open it again.
    *(volatile unsigned int *)(0x01f01400 + 0x28) = 0x9;// apb0_clk_gating: r_rsb && r_pio gating open

#if (defined(CONFIG_A73_FPGA))
	//PH14,PH15 cfg 3
	rsb_reg_writel(rsb_reg_readl(SUNXI_PIO_BASE+0x100) & (~(0xff<<24)),SUNXI_PIO_BASE+0x100);
	rsb_reg_writel(rsb_reg_readl(SUNXI_PIO_BASE+0x100)|(unsigned int)(0x33<<24),SUNXI_PIO_BASE+0x100);
	//PH14,PH15 pull up 1
	rsb_reg_writel(rsb_reg_readl(SUNXI_PIO_BASE+0x118)& (unsigned int)(~(0xf<<28)),SUNXI_PIO_BASE+0x118);
	rsb_reg_writel(rsb_reg_readl(SUNXI_PIO_BASE+0x118)| (unsigned int)(0x5<<28),SUNXI_PIO_BASE+0x118);
	//PH14,PH15 drv 2
	rsb_reg_writel(rsb_reg_readl(SUNXI_PIO_BASE+0x110)& (unsigned int)(~(0xf<<28)),SUNXI_PIO_BASE+0x110);
	rsb_reg_writel(rsb_reg_readl(SUNXI_PIO_BASE+0x110)|(unsigned int)(0xa<<28),SUNXI_PIO_BASE+0x110);
#else
		//PL0,PL1 cfg 2
	rsb_reg_writel(rsb_reg_readl(0x01f02c00)& ~0xff,0x01f02c00);
	rsb_reg_writel(rsb_reg_readl(0x01f02c00)|0x22,0x01f02c00);
	//PL0,PL1 pull up 1
	rsb_reg_writel(rsb_reg_readl(0x01f02c00+0x1c)& ~0xf,0x01f02c00+0x1c);
	rsb_reg_writel(rsb_reg_readl(0x01f02c00+0x1c)|0x5,0x01f02c00+0x1c);
	//PL0,PL1 drv 2
	rsb_reg_writel(rsb_reg_readl(0x01f02c00+0x14)& ~0xf,0x01f02c00+0x14);
	rsb_reg_writel(rsb_reg_readl(0x01f02c00+0x14)|0xa,0x01f02c00+0x14);
#endif

}

Example #4

File: rsb_spl.c Project: carpecarp/CC-A80-u-boot

static void rsb_module_reset(void)
{
//	r_prcm_module_reset(R_RSB_CKID);
	rsb_reg_writel(rsb_reg_readl(SUNXI_RPRCM_BASE + 0xb0)& ~(0x1U << 3),SUNXI_RPRCM_BASE + 0xb0);
	rsb_reg_writel(rsb_reg_readl(SUNXI_RPRCM_BASE + 0xb0)|(0x1U << 3),SUNXI_RPRCM_BASE + 0xb0);
}

Example #5

File: rsb.c Project: mfkiwl/a33_bootloader

static void rsb_cfg_io(void)
{
#if (defined(CONFIG_A73_FPGA) || defined(CONFIG_A67_FPGA) || defined(CONFIG_A50_FPGA) || (defined(CONFIG_A39_FPGA)))
//	gpio_set_cfg(GPIO_H(14), 2, 3);
//	gpio_set_pull(GPIO_H(14), 2, 1);
//	gpio_set_drv(GPIO_H(14), 2, 2);
	//PH14,PH15 cfg 3
	rsb_reg_writel(rsb_reg_readl(SUNXI_PIO_BASE+0x100)& ~(0xff<<24),SUNXI_PIO_BASE+0x100);
	rsb_reg_writel(rsb_reg_readl(SUNXI_PIO_BASE+0x100)|(0x33<<24),SUNXI_PIO_BASE+0x100);
	//PH14,PH15 pull up 1
	rsb_reg_writel(rsb_reg_readl(SUNXI_PIO_BASE+0x118)& ~(0xf<<28),SUNXI_PIO_BASE+0x118);
	rsb_reg_writel(rsb_reg_readl(SUNXI_PIO_BASE+0x118)|(0x5<<28),SUNXI_PIO_BASE+0x118);
	//PH14,PH15 drv 2
	rsb_reg_writel(rsb_reg_readl(SUNXI_PIO_BASE+0x110)& ~(0xf<<28),SUNXI_PIO_BASE+0x110);
	rsb_reg_writel(rsb_reg_readl(SUNXI_PIO_BASE+0x110)|(0xa<<28),SUNXI_PIO_BASE+0x110);
#elif (defined(CONFIG_ARCH_SUN8IW3P1) || defined(CONFIG_ARCH_SUN8IW5P1) || defined(CONFIG_ARCH_SUN8IW6P1) )
//	r_gpio_set_cfg(R_GPIO_L(0), 2, 2);
//	r_gpio_set_pull(R_GPIO_L(0), 2, 1);
//	r_gpio_set_drv(R_GPIO_L(0), 2, 2);
	//PL0,PL1 cfg 2
	rsb_reg_writel(rsb_reg_readl(0x01f02c00)& ~0xff,0x01f02c00);
	rsb_reg_writel(rsb_reg_readl(0x01f02c00)|0x22,0x01f02c00);
	//PL0,PL1 pull up 1
	rsb_reg_writel(rsb_reg_readl(0x01f02c00+0x1c)& ~0xf,0x01f02c00+0x1c);
	rsb_reg_writel(rsb_reg_readl(0x01f02c00+0x1c)|0x5,0x01f02c00+0x1c);
	//PL0,PL1 drv 2
	rsb_reg_writel(rsb_reg_readl(0x01f02c00+0x14)& ~0xf,0x01f02c00+0x14);
	rsb_reg_writel(rsb_reg_readl(0x01f02c00+0x14)|0xa,0x01f02c00+0x14);
#elif defined(CONFIG_ARCH_SUN9IW1P1)
	//PN0,PN1 cfg 3
	rsb_reg_writel(rsb_reg_readl(0x08002c00+0x48)& ~0xff,0x08002c00+0x48);
	rsb_reg_writel(rsb_reg_readl(0x08002c00+0x48)|0x33,0x08002c00+0x48);
	//PN0,PN1 pull up 1
	rsb_reg_writel(rsb_reg_readl(0x08002c00+0x64)& ~0xf,0x08002c00+0x64);
	rsb_reg_writel(rsb_reg_readl(0x08002c00+0x64)|0x5,0x08002c00+0x64);
	//PN0,PN1 drv 2
	rsb_reg_writel(rsb_reg_readl(0x08002c00+0x5c)& ~0xf,0x08002c00+0x5c);
	rsb_reg_writel(rsb_reg_readl(0x08002c00+0x5c)|0xa,0x08002c00+0x5c);

#else

#endif
}