static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
{
struct rt2x00_dev *rt2x00dev = hw->priv;
u32 reg;
rt2x00pci_register_read(rt2x00dev, CSR15, ®);
return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
}
static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
{
struct queue_entry_priv_pci *entry_priv;
u32 reg;
/*
* Initialize registers.
*/
entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT0,
rt2x00dev->tx[0].limit);
rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX0, 0);
rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX0, 0);
entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT1,
rt2x00dev->tx[1].limit);
rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX1, 0);
rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX1, 0);
entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT2,
rt2x00dev->tx[2].limit);
rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX2, 0);
rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX2, 0);
entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT3,
rt2x00dev->tx[3].limit);
rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX3, 0);
rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX3, 0);
entry_priv = rt2x00dev->rx->entries[0].priv_data;
rt2x00pci_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
rt2x00pci_register_write(rt2x00dev, RX_MAX_CNT,
rt2x00dev->rx[0].limit);
rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX,
rt2x00dev->rx[0].limit - 1);
rt2x00pci_register_write(rt2x00dev, RX_DRX_IDX, 0);
/*
* Enable global DMA configuration
*/
rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, ®);
rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
rt2x00pci_register_write(rt2x00dev, DELAY_INT_CFG, 0);
return 0;
}
static void rt2400pci_disable_led(struct rt2x00_dev *rt2x00dev)
{
u32 reg;
rt2x00pci_register_read(rt2x00dev, LEDCSR, ®);
rt2x00_set_field32(®, LEDCSR_LINK, 0);
rt2x00_set_field32(®, LEDCSR_ACTIVITY, 0);
rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
}
static int rt2400pci_init_rings(struct rt2x00_dev *rt2x00dev)
{
u32 reg;
/*
* Initialize rings.
*/
rt2400pci_init_rxring(rt2x00dev);
rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
/*
* Initialize registers.
*/
rt2x00pci_register_read(rt2x00dev, TXCSR2, ®);
rt2x00_set_field32(®, TXCSR2_TXD_SIZE,
rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].desc_size);
rt2x00_set_field32(®, TXCSR2_NUM_TXD,
rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].stats.limit);
rt2x00_set_field32(®, TXCSR2_NUM_ATIM,
rt2x00dev->bcn[1].stats.limit);
rt2x00_set_field32(®, TXCSR2_NUM_PRIO,
rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].stats.limit);
rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
rt2x00pci_register_read(rt2x00dev, TXCSR3, ®);
rt2x00_set_field32(®, TXCSR3_TX_RING_REGISTER,
rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].data_dma);
rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
rt2x00pci_register_read(rt2x00dev, TXCSR5, ®);
rt2x00_set_field32(®, TXCSR5_PRIO_RING_REGISTER,
rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].data_dma);
rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
rt2x00pci_register_read(rt2x00dev, TXCSR4, ®);
rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER,
rt2x00dev->bcn[1].data_dma);
rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
rt2x00pci_register_read(rt2x00dev, TXCSR6, ®);
rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER,
rt2x00dev->bcn[0].data_dma);
rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
rt2x00pci_register_read(rt2x00dev, RXCSR1, ®);
rt2x00_set_field32(®, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
rt2x00_set_field32(®, RXCSR1_NUM_RXD, rt2x00dev->rx->stats.limit);
rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
rt2x00pci_register_read(rt2x00dev, RXCSR2, ®);
rt2x00_set_field32(®, RXCSR2_RX_RING_REGISTER,
rt2x00dev->rx->data_dma);
rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
return 0;
}
static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
{
struct rt2x00_dev *rt2x00dev = dev_instance;
u32 reg;
/*
* Get the interrupt sources & saved to local variable.
* Write register value back to clear pending interrupts.
*/
rt2x00pci_register_read(rt2x00dev, CSR7, ®);
rt2x00pci_register_write(rt2x00dev, CSR7, reg);
if (!reg)
return IRQ_NONE;
if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
return IRQ_HANDLED;
/*
* Handle interrupts, walk through all bits
* and run the tasks, the bits are checked in order of
* priority.
*/
/*
* 1 - Beacon timer expired interrupt.
*/
if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
rt2x00lib_beacondone(rt2x00dev);
/*
* 2 - Rx ring done interrupt.
*/
if (rt2x00_get_field32(reg, CSR7_RXDONE))
rt2x00pci_rxdone(rt2x00dev);
/*
* 3 - Atim ring transmit done interrupt.
*/
if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
rt2400pci_txdone(rt2x00dev, QID_ATIM);
/*
* 4 - Priority ring transmit done interrupt.
*/
if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
rt2400pci_txdone(rt2x00dev, QID_AC_BE);
/*
* 5 - Tx ring transmit done interrupt.
*/
if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
rt2400pci_txdone(rt2x00dev, QID_AC_BK);
return IRQ_HANDLED;
}
static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
{
struct rt2x00_dev *rt2x00dev = dev_instance;
u32 reg, mask;
rt2x00pci_register_read(rt2x00dev, CSR7, ®);
rt2x00pci_register_write(rt2x00dev, CSR7, reg);
if (!reg)
return IRQ_NONE;
if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
return IRQ_HANDLED;
mask = reg;
if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
if (rt2x00_get_field32(reg, CSR7_RXDONE))
tasklet_schedule(&rt2x00dev->rxdone_tasklet);
if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING) ||
rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING) ||
rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) {
tasklet_schedule(&rt2x00dev->txstatus_tasklet);
rt2x00_set_field32(&mask, CSR8_TXDONE_TXRING, 1);
rt2x00_set_field32(&mask, CSR8_TXDONE_ATIMRING, 1);
rt2x00_set_field32(&mask, CSR8_TXDONE_PRIORING, 1);
}
spin_lock(&rt2x00dev->irqmask_lock);
rt2x00pci_register_read(rt2x00dev, CSR8, ®);
reg |= mask;
rt2x00pci_register_write(rt2x00dev, CSR8, reg);
spin_unlock(&rt2x00dev->irqmask_lock);
return IRQ_HANDLED;
}
static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
struct ieee80211_tx_queue_params *params)
{
u32 reg;
rt2x00pci_register_read(rt2x00dev, CSR11, ®);
rt2x00_set_field32(®, CSR11_CWMIN, params->cw_min);
rt2x00_set_field32(®, CSR11_CWMAX, params->cw_max);
rt2x00pci_register_write(rt2x00dev, CSR11, reg);
}
static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
const int cw_min, const int cw_max)
{
u32 reg;
rt2x00pci_register_read(rt2x00dev, CSR11, ®);
rt2x00_set_field32(®, CSR11_CWMIN, cw_min);
rt2x00_set_field32(®, CSR11_CWMAX, cw_max);
rt2x00pci_register_write(rt2x00dev, CSR11, reg);
}
/*
* Device state switch handlers.
*/
static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
enum dev_state state)
{
u32 reg;
rt2x00pci_register_read(rt2x00dev, RXCSR0, ®);
rt2x00_set_field32(®, RXCSR0_DISABLE_RX,
state == STATE_RADIO_RX_OFF);
rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
}
static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
struct rt2x00lib_erp *erp)
{
int preamble_mask;
u32 reg;
/*
* When short preamble is enabled, we should set bit 0x08
*/
preamble_mask = erp->short_preamble << 3;
rt2x00pci_register_read(rt2x00dev, TXCSR1, ®);
rt2x00_set_field32(®, TXCSR1_ACK_TIMEOUT,
erp->ack_timeout);
rt2x00_set_field32(®, TXCSR1_ACK_CONSUME_TIME,
erp->ack_consume_time);
rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
rt2x00pci_register_read(rt2x00dev, ARCSR2, ®);
rt2x00_set_field32(®, ARCSR2_SIGNAL, 0x00);
rt2x00_set_field32(®, ARCSR2_SERVICE, 0x04);
rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
rt2x00pci_register_read(rt2x00dev, ARCSR3, ®);
rt2x00_set_field32(®, ARCSR3_SIGNAL, 0x01 | preamble_mask);
rt2x00_set_field32(®, ARCSR3_SERVICE, 0x04);
rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
rt2x00pci_register_read(rt2x00dev, ARCSR4, ®);
rt2x00_set_field32(®, ARCSR4_SIGNAL, 0x02 | preamble_mask);
rt2x00_set_field32(®, ARCSR4_SERVICE, 0x04);
rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
rt2x00pci_register_read(rt2x00dev, ARCSR5, ®);
rt2x00_set_field32(®, ARCSR5_SIGNAL, 0x03 | preamble_mask);
rt2x00_set_field32(®, ARCSR5_SERVICE, 0x84);
rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
}
static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
{
u32 reg;
u16 value;
u16 eeprom;
/*
* Read EEPROM word for configuration.
*/
rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
/*
* Identify RF chipset.
*/
value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
rt2x00pci_register_read(rt2x00dev, CSR0, ®);
rt2x00_set_chip(rt2x00dev, RT2460, value, reg);
if (!rt2x00_rf(&rt2x00dev->chip, RF2420) &&
!rt2x00_rf(&rt2x00dev->chip, RF2421)) {
ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
return -ENODEV;
}
/*
* Identify default antenna configuration.
*/
rt2x00dev->hw->conf.antenna_sel_tx =
rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
rt2x00dev->hw->conf.antenna_sel_rx =
rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
/*
* Store led mode, for correct led behaviour.
*/
rt2x00dev->led_mode =
rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
/*
* Detect if this device has an hardware controlled radio.
*/
#ifdef CONFIG_RT2400PCI_RFKILL
if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
__set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
#endif /* CONFIG_RT2400PCI_RFKILL */
/*
* Check if the BBP tuning should be enabled.
*/
if (!rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
__set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
return 0;
}
static void rt2400pci_kick_tx_queue(struct data_queue *queue)
{
struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
u32 reg;
rt2x00pci_register_read(rt2x00dev, TXCSR0, ®);
rt2x00_set_field32(®, TXCSR0_KICK_PRIO, (queue->qid == QID_AC_BE));
rt2x00_set_field32(®, TXCSR0_KICK_TX, (queue->qid == QID_AC_BK));
rt2x00_set_field32(®, TXCSR0_KICK_ATIM, (queue->qid == QID_ATIM));
rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
}
static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
{
u32 reg;
/*
* Reset DMA indexes
*/
rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, ®);
rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX0, 1);
rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX1, 1);
rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX2, 1);
rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX3, 1);
rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX4, 1);
rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX5, 1);
rt2x00_set_field32(®, WPDMA_RST_IDX_DRX_IDX0, 1);
rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
if (rt2x00_is_pcie(rt2x00dev) &&
(rt2x00_rt(rt2x00dev, RT3572) ||
rt2x00_rt(rt2x00dev, RT5390) ||
rt2x00_rt(rt2x00dev, RT5392))) {
rt2x00pci_register_read(rt2x00dev, AUX_CTRL, ®);
rt2x00_set_field32(®, AUX_CTRL_FORCE_PCIE_CLK, 1);
rt2x00_set_field32(®, AUX_CTRL_WAKE_PCIE_EN, 1);
rt2x00pci_register_write(rt2x00dev, AUX_CTRL, reg);
}
rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
reg = 0;
rt2x00_set_field32(®, MAC_SYS_CTRL_RESET_CSR, 1);
rt2x00_set_field32(®, MAC_SYS_CTRL_RESET_BBP, 1);
rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
return 0;
}
static void rt2400pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
struct rt2x00lib_conf *libconf)
{
u32 reg;
rt2x00pci_register_read(rt2x00dev, CSR11, ®);
rt2x00_set_field32(®, CSR11_LONG_RETRY,
libconf->conf->long_frame_max_tx_count);
rt2x00_set_field32(®, CSR11_SHORT_RETRY,
libconf->conf->short_frame_max_tx_count);
rt2x00pci_register_write(rt2x00dev, CSR11, reg);
}
static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
struct link_qual *qual)
{
u32 reg;
u8 bbp;
rt2x00pci_register_read(rt2x00dev, CNT0, ®);
qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
qual->false_cca = bbp;
}
static int rt2400pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
struct ieee80211_tx_control *control)
{
struct rt2x00_dev *rt2x00dev = hw->priv;
struct rt2x00_intf *intf = vif_to_intf(control->vif);
struct queue_entry_priv_pci_tx *priv_tx;
struct skb_frame_desc *skbdesc;
u32 reg;
if (unlikely(!intf->beacon))
return -ENOBUFS;
priv_tx = intf->beacon->priv_data;
/*
* Fill in skb descriptor
*/
skbdesc = get_skb_frame_desc(skb);
memset(skbdesc, 0, sizeof(*skbdesc));
skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED;
skbdesc->data = skb->data;
skbdesc->data_len = skb->len;
skbdesc->desc = priv_tx->desc;
skbdesc->desc_len = intf->beacon->queue->desc_size;
skbdesc->entry = intf->beacon;
/*
* Disable beaconing while we are reloading the beacon data,
* otherwise we might be sending out invalid data.
*/
rt2x00pci_register_read(rt2x00dev, CSR14, ®);
rt2x00_set_field32(®, CSR14_TSF_COUNT, 0);
rt2x00_set_field32(®, CSR14_TBCN, 0);
rt2x00_set_field32(®, CSR14_BEACON_GEN, 0);
rt2x00pci_register_write(rt2x00dev, CSR14, reg);
/*
* mac80211 doesn't provide the control->queue variable
* for beacons. Set our own queue identification so
* it can be used during descriptor initialization.
*/
control->queue = RT2X00_BCN_QUEUE_BEACON;
rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
/*
* Enable beacon generation.
* Write entire beacon with descriptor to register,
* and kick the beacon generator.
*/
memcpy(priv_tx->data, skb->data, skb->len);
rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, control->queue);
return 0;
}
static void rt2400pci_kill_tx_queue(struct data_queue *queue)
{
struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
u32 reg;
if (queue->qid == QID_BEACON) {
rt2x00pci_register_write(rt2x00dev, CSR14, 0);
} else {
rt2x00pci_register_read(rt2x00dev, TXCSR0, ®);
rt2x00_set_field32(®, TXCSR0_ABORT, 1);
rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
}
}
static inline void rt2400pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
struct rt2x00_field32 irq_field)
{
u32 reg;
spin_lock_irq(&rt2x00dev->irqmask_lock);
rt2x00pci_register_read(rt2x00dev, CSR8, ®);
rt2x00_set_field32(®, irq_field, 0);
rt2x00pci_register_write(rt2x00dev, CSR8, reg);
spin_unlock_irq(&rt2x00dev->irqmask_lock);
}
static void rt2400pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
const enum data_queue_qid qid)
{
u32 reg;
if (qid == QID_BEACON) {
rt2x00pci_register_write(rt2x00dev, CSR14, 0);
} else {
rt2x00pci_register_read(rt2x00dev, TXCSR0, ®);
rt2x00_set_field32(®, TXCSR0_ABORT, 1);
rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
}
}
static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
const enum data_queue_qid queue)
{
u32 reg;
if (queue == QID_BEACON) {
rt2x00pci_register_read(rt2x00dev, CSR14, ®);
if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
rt2x00_set_field32(®, CSR14_TSF_COUNT, 1);
rt2x00_set_field32(®, CSR14_TBCN, 1);
rt2x00_set_field32(®, CSR14_BEACON_GEN, 1);
rt2x00pci_register_write(rt2x00dev, CSR14, reg);
}
return;
}
rt2x00pci_register_read(rt2x00dev, TXCSR0, ®);
rt2x00_set_field32(®, TXCSR0_KICK_PRIO, (queue == QID_AC_BE));
rt2x00_set_field32(®, TXCSR0_KICK_TX, (queue == QID_AC_BK));
rt2x00_set_field32(®, TXCSR0_KICK_ATIM, (queue == QID_ATIM));
rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
}
/*
* IEEE80211 stack callback functions.
*/
static int rt2400pci_set_retry_limit(struct ieee80211_hw *hw,
u32 short_retry, u32 long_retry)
{
struct rt2x00_dev *rt2x00dev = hw->priv;
u32 reg;
rt2x00pci_register_read(rt2x00dev, CSR11, ®);
rt2x00_set_field32(®, CSR11_LONG_RETRY, long_retry);
rt2x00_set_field32(®, CSR11_SHORT_RETRY, short_retry);
rt2x00pci_register_write(rt2x00dev, CSR11, reg);
return 0;
}
static void rt2400pci_start_queue(struct data_queue *queue)
{
struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
u32 reg;
switch (queue->qid) {
case QID_RX:
rt2x00pci_register_read(rt2x00dev, RXCSR0, ®);
rt2x00_set_field32(®, RXCSR0_DISABLE_RX, 0);
rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
break;
case QID_BEACON:
rt2x00pci_register_read(rt2x00dev, CSR14, ®);
rt2x00_set_field32(®, CSR14_TSF_COUNT, 1);
rt2x00_set_field32(®, CSR14_TBCN, 1);
rt2x00_set_field32(®, CSR14_BEACON_GEN, 1);
rt2x00pci_register_write(rt2x00dev, CSR14, reg);
break;
default:
break;
}
}
static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
enum dev_state state)
{
u32 reg;
unsigned int i;
char put_to_sleep;
char bbp_state;
char rf_state;
put_to_sleep = (state != STATE_AWAKE);
rt2x00pci_register_read(rt2x00dev, PWRCSR1, ®);
rt2x00_set_field32(®, PWRCSR1_SET_STATE, 1);
rt2x00_set_field32(®, PWRCSR1_BBP_DESIRE_STATE, state);
rt2x00_set_field32(®, PWRCSR1_RF_DESIRE_STATE, state);
rt2x00_set_field32(®, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
/*
* Device is not guaranteed to be in the requested state yet.
* We must wait until the register indicates that the
* device has entered the correct state.
*/
for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
rt2x00pci_register_read(rt2x00dev, PWRCSR1, ®);
bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
if (bbp_state == state && rf_state == state)
return 0;
msleep(10);
}
NOTICE(rt2x00dev, "Device failed to enter state %d, "
"current device state: bbp %d and rf %d.\n",
state, bbp_state, rf_state);
return -EBUSY;
}
static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
{
struct rt2x00_dev *rt2x00dev = eeprom->data;
u32 reg;
rt2x00pci_register_read(rt2x00dev, CSR21, ®);
eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
eeprom->reg_data_clock =
!!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
eeprom->reg_chip_select =
!!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
}
/*
* Register access.
* All access to the CSR registers will go through the methods
* rt2x00pci_register_read and rt2x00pci_register_write.
* BBP and RF register require indirect register access,
* and use the CSR registers BBPCSR and RFCSR to achieve this.
* These indirect registers work with busy bits,
* and we will try maximal REGISTER_BUSY_COUNT times to access
* the register while taking a REGISTER_BUSY_DELAY us delay
* between each attampt. When the busy bit is still set at that time,
* the access attempt is considered to have failed,
* and we will print an error.
*/
static u32 rt2400pci_bbp_check(struct rt2x00_dev *rt2x00dev)
{
u32 reg;
unsigned int i;
for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
rt2x00pci_register_read(rt2x00dev, BBPCSR, ®);
if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
break;
udelay(REGISTER_BUSY_DELAY);
}
return reg;
}
static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
struct rf_channel *rf)
{
/*
* Switch on tuning bits.
*/
rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
/*
* RF2420 chipset don't need any additional actions.
*/
if (rt2x00_rf(rt2x00dev, RF2420))
return;
/*
* For the RT2421 chipsets we need to write an invalid
* reference clock rate to activate auto_tune.
* After that we set the value back to the correct channel.
*/
rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
msleep(1);
rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
msleep(1);
/*
* Switch off tuning bits.
*/
rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
/*
* Clear false CRC during channel switch.
*/
rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
}
/*
* TX data initialization
*/
static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
unsigned int queue)
{
u32 reg;
if (queue == IEEE80211_TX_QUEUE_BEACON) {
rt2x00pci_register_read(rt2x00dev, CSR14, ®);
if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
rt2x00_set_field32(®, CSR14_BEACON_GEN, 1);
rt2x00pci_register_write(rt2x00dev, CSR14, reg);
}
return;
}
rt2x00pci_register_read(rt2x00dev, TXCSR0, ®);
if (queue == IEEE80211_TX_QUEUE_DATA0)
rt2x00_set_field32(®, TXCSR0_KICK_PRIO, 1);
else if (queue == IEEE80211_TX_QUEUE_DATA1)
rt2x00_set_field32(®, TXCSR0_KICK_TX, 1);
else if (queue == IEEE80211_TX_QUEUE_AFTER_BEACON)
rt2x00_set_field32(®, TXCSR0_KICK_ATIM, 1);
rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
}
static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
{
struct queue_entry_priv_pci *entry_priv;
u32 reg;
/*
* Initialize registers.
*/
rt2x00pci_register_read(rt2x00dev, TXCSR2, ®);
rt2x00_set_field32(®, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
rt2x00_set_field32(®, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
rt2x00_set_field32(®, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
rt2x00_set_field32(®, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
rt2x00pci_register_read(rt2x00dev, TXCSR3, ®);
rt2x00_set_field32(®, TXCSR3_TX_RING_REGISTER,
entry_priv->desc_dma);
rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
rt2x00pci_register_read(rt2x00dev, TXCSR5, ®);
rt2x00_set_field32(®, TXCSR5_PRIO_RING_REGISTER,
entry_priv->desc_dma);
rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
rt2x00pci_register_read(rt2x00dev, TXCSR4, ®);
rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER,
entry_priv->desc_dma);
rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
rt2x00pci_register_read(rt2x00dev, TXCSR6, ®);
rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER,
entry_priv->desc_dma);
rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
rt2x00pci_register_read(rt2x00dev, RXCSR1, ®);
rt2x00_set_field32(®, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
rt2x00_set_field32(®, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
entry_priv = rt2x00dev->rx->entries[0].priv_data;
rt2x00pci_register_read(rt2x00dev, RXCSR2, ®);
rt2x00_set_field32(®, RXCSR2_RX_RING_REGISTER,
entry_priv->desc_dma);
rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
return 0;
}
static inline void rt2800pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
struct rt2x00_field32 irq_field)
{
u32 reg;
/*
* Enable a single interrupt. The interrupt mask register
* access needs locking.
*/
spin_lock_irq(&rt2x00dev->irqmask_lock);
rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, ®);
rt2x00_set_field32(®, irq_field, 1);
rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
spin_unlock_irq(&rt2x00dev->irqmask_lock);
}
static int rt2400pci_blink_set(struct led_classdev *led_cdev,
unsigned long *delay_on,
unsigned long *delay_off)
{
struct rt2x00_led *led =
container_of(led_cdev, struct rt2x00_led, led_dev);
u32 reg;
rt2x00pci_register_read(led->rt2x00dev, LEDCSR, ®);
rt2x00_set_field32(®, LEDCSR_ON_PERIOD, *delay_on);
rt2x00_set_field32(®, LEDCSR_OFF_PERIOD, *delay_off);
rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
return 0;
}
