/** * This function will initialize hardware interrupt */ void rt_hw_interrupt_init(void) { rt_hw_vector_init(); gic_init(); /* init interrupt nest, and context in thread sp */ rt_interrupt_nest = 0; rt_interrupt_from_thread = 0; rt_interrupt_to_thread = 0; rt_thread_switch_interrupt_flag = 0; }
/** * This function will initialize hardware interrupt */ void rt_hw_interrupt_init(void) { rt_uint32_t gic_cpu_base; rt_uint32_t gic_dist_base; /* initialize vector table */ rt_hw_vector_init(); /* initialize exceptions table */ rt_memset(isr_table, 0x00, sizeof(isr_table)); /* initialize ARM GIC */ gic_dist_base = REALVIEW_GIC_DIST_BASE; gic_cpu_base = REALVIEW_GIC_CPU_BASE; arm_gic_dist_init(0, gic_dist_base, 0); arm_gic_cpu_init(0, gic_cpu_base); }
/** * This function will initialize hardware interrupt */ void rt_hw_interrupt_init(void) { rt_uint32_t gic_cpu_base; rt_uint32_t gic_dist_base; /* initialize vector table */ rt_hw_vector_init(); /* initialize exceptions table */ rt_memset(isr_table, 0x00, sizeof(isr_table)); /* initialize ARM GIC */ gic_dist_base = REALVIEW_GIC_DIST_BASE; gic_cpu_base = REALVIEW_GIC_CPU_BASE; arm_gic_dist_init(0, gic_dist_base, 0); arm_gic_cpu_init(0, gic_cpu_base); /*arm_gic_dump_type(0);*/ /* init interrupt nest, and context in thread sp */ rt_interrupt_nest = 0; rt_interrupt_from_thread = 0; rt_interrupt_to_thread = 0; rt_thread_switch_interrupt_flag = 0; }