void bsp_start( void )
{
rtems_status_code sc = RTEMS_SUCCESSFUL;
uintptr_t intrStackStart;
uintptr_t intrStackSize;
/*
* Note we can not get CPU identification dynamically, so
* force current_ppc_cpu.
*/
current_ppc_cpu = PPC_PSIM;
/*
* initialize the device driver parameters
* assume we are running with 20MHz bus
* this should speed up some tests :-)
*/
BSP_bus_frequency = 20;
bsp_time_base_frequency = 20000000;
bsp_clicks_per_usec = BSP_bus_frequency;
rtems_counter_initialize_converter(bsp_time_base_frequency);
/*
* Initialize the interrupt related settings.
*/
intrStackStart = (uintptr_t) bsp_interrupt_stack_start;
intrStackSize = (uintptr_t) bsp_interrupt_stack_size;
BSP_mem_size = (uint32_t )RamSize;
/*
* Initialize default raw exception handlers.
*/
ppc_exc_initialize(intrStackStart, intrStackSize);
/* Install default handler for the decrementer exception */
sc = ppc_exc_set_handler( ASM_DEC_VECTOR, default_decrementer_exception_handler);
if (sc != RTEMS_SUCCESSFUL) {
BSP_panic("cannot install decrementer exception handler");
}
/* Initalize interrupt support */
bsp_interrupt_initialize();
#if 0
/*
* Setup BATs and enable MMU
*/
/* Memory */
setdbat(0, 0x0<<24, 0x0<<24, 2<<24, _PAGE_RW);
setibat(0, 0x0<<24, 0x0<<24, 2<<24, 0);
/* PCI */
setdbat(1, 0x8<<24, 0x8<<24, 1<<24, IO_PAGE);
setdbat(2, 0xc<<24, 0xc<<24, 1<<24, IO_PAGE);
_write_MSR(_read_MSR() | MSR_DR | MSR_IR);
__asm__ volatile("sync; isync");
#endif
}
void bsp_start(void)
{
unsigned long i = 0;
ppc_cpu_id_t myCpu;
ppc_cpu_revision_t myCpuRevision;
/*
* Get CPU identification dynamically. Note that the get_ppc_cpu_type() function
* store the result in global variables so that it can be used latter...
*/
myCpu = get_ppc_cpu_type();
myCpuRevision = get_ppc_cpu_revision();
/* Initialize some device driver parameters */
#ifdef HAS_UBOOT
BSP_bus_frequency = bsp_uboot_board_info.bi_busfreq;
bsp_clicks_per_usec = bsp_uboot_board_info.bi_busfreq / 8000000;
#endif /* HAS_UBOOT */
rtems_counter_initialize_converter(BSP_bus_frequency / 8);
/* Initialize some console parameters */
for (i = 0; i < Console_Configuration_Count; ++i) {
console_tbl *ct = &Console_Configuration_Ports[i];
ct->ulClock = BSP_bus_frequency;
#ifdef HAS_UBOOT
if (ct->deviceType == SERIAL_NS16550) {
ct->pDeviceParams = (void *) bsp_uboot_board_info.bi_baudrate;
}
#endif
}
/* Disable decrementer */
PPC_CLEAR_SPECIAL_PURPOSE_REGISTER_BITS(BOOKE_TCR, BOOKE_TCR_DIE);
/* Initialize exception handler */
ppc_exc_initialize_with_vector_base(
(uintptr_t) bsp_section_work_begin,
rtems_configuration_get_interrupt_stack_size(),
bsp_exc_vector_base
);
/* Now it is possible to make the code execute only */
qoriq_mmu_change_perm(
FSL_EIS_MAS3_SR | FSL_EIS_MAS3_SX,
FSL_EIS_MAS3_SX,
FSL_EIS_MAS3_SR
);
/* Initalize interrupt support */
bsp_interrupt_initialize();
/* Disable boot page translation */
qoriq.lcc.bptr &= ~BPTR_EN;
}
static void erc32_counter_initialize( uint32_t frequency )
{
_SPARC_Counter_initialize(
_SPARC_Counter_read_address,
_SPARC_Counter_difference_clock_period,
&ERC32_MEC.Real_Time_Clock_Counter
);
rtems_counter_initialize_converter( frequency );
}
static void armv7m_cpu_counter_initialize(void)
{
bool cyccnt_enabled;
cyccnt_enabled = _ARMV7M_DWT_Enable_CYCCNT();
if (cyccnt_enabled) {
#ifdef BSP_ARMV7M_SYSTICK_FREQUENCY
uint64_t freq = BSP_ARMV7M_SYSTICK_FREQUENCY;
#else
volatile ARMV7M_Systick *systick = _ARMV7M_Systick;
uint64_t freq = ARMV7M_SYSTICK_CALIB_TENMS_GET(systick->calib) * 100ULL;
#endif
rtems_counter_initialize_converter(freq);
} else {
bsp_fatal(BSP_ARM_ARMV7M_CPU_COUNTER_INIT);
}
}
void bsp_start(void)
{
null_pointer_protection();
/*
* Get CPU identification dynamically. Note that the get_ppc_cpu_type()
* function store the result in global variables so that it can be used
* latter...
*/
get_ppc_cpu_type();
get_ppc_cpu_revision();
/*
* determine clock speed
*/
bsp_clock_speed = mpc55xx_get_system_clock() / MPC55XX_SYSTEM_CLOCK_DIVIDER;
/* Time reference value */
bsp_clicks_per_usec = bsp_clock_speed / 1000000;
rtems_counter_initialize_converter(bsp_clock_speed);
/* Initialize exceptions */
ppc_exc_initialize_with_vector_base(
(uintptr_t) bsp_section_work_begin,
rtems_configuration_get_interrupt_stack_size(),
mpc55xx_exc_vector_base
);
#ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER
ppc_exc_set_handler(ASM_ALIGN_VECTOR, ppc_exc_alignment_handler);
#endif
/* Initialize interrupts */
bsp_interrupt_initialize();
#if MPC55XX_CHIP_FAMILY != 566
mpc55xx_edma_init();
#endif
#ifdef MPC55XX_EMIOS_PRESCALER
mpc55xx_emios_initialize(MPC55XX_EMIOS_PRESCALER);
#endif
}
/*
* bsp_start()
*
* Board-specific initialization code. Called from the generic boot_card()
* function defined in rtems/c/src/lib/libbsp/shared/main.c. That function
* does some of the board independent initialization. It is called from the
* SS555 entry point _start() defined in
* rtems/c/src/lib/libbsp/powerpc/ss555/start/start.S
*
* _start() has set up a stack, has zeroed the .bss section, has set up the
* .data section from contents stored in ROM, has turned off interrupts,
* and placed the processor in the supervisor mode. boot_card() has left
* the processor in that state when bsp_start() was called.
*
* Input parameters: NONE
*
* Output parameters: NONE
*
* Return values: NONE
*/
void bsp_start(void)
{
ppc_cpu_id_t myCpu;
ppc_cpu_revision_t myCpuRevision;
register unsigned char* intrStack;
/*
* Get CPU identification dynamically. Note that the get_ppc_cpu_type()
* function stores the result in global variables so that it can be used
* later.
*/
myCpu = get_ppc_cpu_type();
myCpuRevision = get_ppc_cpu_revision();
/*
* Initialize some SPRG registers related to irq handling
*/
intrStack = (((unsigned char*)&intrStackPtr) - PPC_MINIMUM_STACK_FRAME_SIZE);
_write_SPRG1((unsigned int)intrStack);
/*
* Install our own set of exception vectors
*/
initialize_exceptions();
/*
* initialize the device driver parameters
*/
bsp_clicks_per_usec = BSP_CRYSTAL_HZ / 4 / 1000000;
bsp_clock_speed = BSP_CLOCK_HZ; /* for SCI baud rate generator */
bsp_timer_least_valid = 0;
bsp_timer_average_overhead = 0;
rtems_counter_initialize_converter(BSP_CRYSTAL_HZ / 4);
/*
* Initalize RTEMS IRQ system
*/
BSP_rtems_irq_mng_init(0);
}
void bsp_start( void )
{
#ifdef CONF_VPD
int i;
#endif
#ifdef SHOW_LCR1_REGISTER
unsigned l1cr;
#endif
#ifdef SHOW_LCR2_REGISTER
unsigned l2cr;
#endif
#ifdef SHOW_LCR3_REGISTER
unsigned l3cr;
#endif
uintptr_t intrStackStart;
uintptr_t intrStackSize;
Triv121PgTbl pt=0;
/* Till Straumann: 4/2005
* Need to map the system registers early, so we can printk...
* (otherwise we silently die)
*/
/*
* Kate Feng : PCI 0 domain memory space, want to leave room for the VME window
*/
setdbat(2, PCI0_MEM_BASE, PCI0_MEM_BASE, 0x10000000, IO_PAGE);
/* Till Straumann: 2004
* map the PCI 0, 1 Domain I/O space, GT64260B registers
* and the reserved area so that the size is the power of 2.
* 2009 : map the entire 256 M space
*
*/
setdbat(3,PCI0_IO_BASE, PCI0_IO_BASE, 0x10000000, IO_PAGE);
/*
* Get CPU identification dynamically. Note that the get_ppc_cpu_type()
* function store the result in global variables so that it can be used later.
*/
get_ppc_cpu_type();
get_ppc_cpu_revision();
#ifdef SHOW_LCR1_REGISTER
l1cr = get_L1CR();
printk("Initial L1CR value = %x\n", l1cr);
#endif
/*
* Initialize the interrupt related settings.
*/
intrStackStart = (uintptr_t) __rtems_end;
intrStackSize = rtems_configuration_get_interrupt_stack_size();
/*
* Initialize default raw exception handlers.
*/
ppc_exc_initialize(intrStackStart, intrStackSize);
/*
* Init MMU block address translation to enable hardware
* access
* More PCI1 memory mapping to be done after BSP_pgtbl_activate.
*/
printk("-----------------------------------------\n");
printk("Welcome to %s on MVME5500-0163\n", _RTEMS_version );
printk("-----------------------------------------\n");
BSP_mem_size = probeMemoryEnd();
/* TODO: calculate the BSP_bus_frequency using the REF_CLK bit
* of System Status register
*/
/* rtems_bsp_delay_in_bus_cycles are defined in registers.h */
BSP_bus_frequency = 133333333;
BSP_processor_frequency = 1000000000;
/* P94 : 7455 clocks the TB/DECR at 1/4 of the system bus clock frequency */
BSP_time_base_divisor = 4000;
/* Maybe not setup yet becuase of the warning message */
/* Allocate and set up the page table mappings
* This is only available on >604 CPUs.
*
* NOTE: This setup routine may modify the available memory
* size. It is essential to call it before
* calculating the workspace etc.
*/
pt = BSP_pgtbl_setup(&BSP_mem_size);
if (!pt)
printk("WARNING: unable to setup page tables.\n");
printk("Now BSP_mem_size = 0x%x\n",BSP_mem_size);
/* P94 : 7455 TB/DECR is clocked by the system bus clock frequency */
bsp_clicks_per_usec = BSP_bus_frequency/(BSP_time_base_divisor * 1000);
rtems_counter_initialize_converter(
BSP_bus_frequency / (BSP_time_base_divisor / 1000)
);
/*
* Initalize RTEMS IRQ system
*/
BSP_rtems_irq_mng_init(0);
#ifdef SHOW_LCR2_REGISTER
l2cr = get_L2CR();
printk("Initial L2CR value = %x\n", l2cr);
#endif
#ifdef SHOW_LCR3_REGISTER
/* L3CR needs DEC int. handler installed for bsp_delay()*/
l3cr = get_L3CR();
printk("Initial L3CR value = %x\n", l3cr);
#endif
/* Activate the page table mappings only after
* initializing interrupts because the irq_mng_init()
* routine needs to modify the text
*/
if (pt) {
#ifdef SHOW_MORE_INIT_SETTINGS
printk("Page table setup finished; will activate it NOW...\n");
#endif
BSP_pgtbl_activate(pt);
}
/* Read Configuration Vital Product Data (VPD) */
if ( I2Cread_eeprom(0xa8, 4,2, &ConfVPD_buff[0], 150))
printk("I2Cread_eeprom() error \n");
else {
#ifdef CONF_VPD
printk("\n");
for (i=0; i<150; i++) {
printk("%2x ", ConfVPD_buff[i]);
if ((i % 20)==0 ) printk("\n");
}
printk("\n");
#endif
}
/*
* PCI 1 domain memory space
*/
setdbat(1, PCI1_MEM_BASE, PCI1_MEM_BASE, 0x10000000, IO_PAGE);
#ifdef SHOW_MORE_INIT_SETTINGS
printk("Going to start PCI buses scanning and initialization\n");
#endif
pci_initialize();
#ifdef SHOW_MORE_INIT_SETTINGS
printk("Number of PCI buses found is : %d\n", pci_bus_count());
#endif
/* Install our own exception handler (needs PCI) */
globalExceptHdl = BSP_exceptionHandler;
/* clear hostbridge errors. MCP signal is not used on the MVME5500
* PCI config space scanning code will trip otherwise :-(
*/
_BSP_clear_hostbridge_errors(0, 1 /*quiet*/);
#ifdef SHOW_MORE_INIT_SETTINGS
printk("MSR %x \n", _read_MSR());
printk("Exit from bspstart\n");
#endif
}
void bsp_start( void)
{
rtems_status_code sc = RTEMS_SUCCESSFUL;
unsigned long i = 0;
/*
* Get CPU identification dynamically. Note that the get_ppc_cpu_type() function
* store the result in global variables so that it can be used latter...
*/
get_ppc_cpu_type();
get_ppc_cpu_revision();
/* Basic CPU initialization */
cpu_init();
/*
* Enable instruction and data caches. Do not force writethrough mode.
*/
#ifdef BSP_INSTRUCTION_CACHE_ENABLED
rtems_cache_enable_instruction();
#endif
#ifdef BSP_DATA_CACHE_ENABLED
rtems_cache_enable_data();
#endif
/*
* This is evaluated during runtime, so it should be ok to set it
* before we initialize the drivers.
*/
/* Initialize some device driver parameters */
#ifdef HAS_UBOOT
BSP_bus_frequency = bsp_uboot_board_info.bi_busfreq;
#else /* HAS_UBOOT */
BSP_bus_frequency = BSP_CLKIN_FRQ * BSP_SYSPLL_MF / BSP_SYSPLL_CKID;
#endif /* HAS_UBOOT */
bsp_time_base_frequency = BSP_bus_frequency / 4;
bsp_clicks_per_usec = bsp_time_base_frequency / 1000000;
rtems_counter_initialize_converter(bsp_time_base_frequency);
/* Initialize some console parameters */
for (i = 0; i < console_device_count; ++i) {
ns16550_context *ctx = (ns16550_context *) console_device_table[i].context;
ctx->clock = BSP_bus_frequency;
#ifdef HAS_UBOOT
ctx->initial_baud = bsp_uboot_board_info.bi_baudrate;
#endif
}
/* Initialize exception handler */
#ifndef BSP_DATA_CACHE_ENABLED
ppc_exc_cache_wb_check = 0;
#endif
ppc_exc_initialize(
(uintptr_t) bsp_section_work_begin,
rtems_configuration_get_interrupt_stack_size()
);
/* Install default handler for the decrementer exception */
sc = ppc_exc_set_handler( ASM_DEC_VECTOR, mpc83xx_decrementer_exception_handler);
if (sc != RTEMS_SUCCESSFUL) {
rtems_panic("cannot install decrementer exception handler");
}
/* Initalize interrupt support */
bsp_interrupt_initialize();
#ifdef SHOW_MORE_INIT_SETTINGS
printk("Exit from bspstart\n");
#endif
}
void bsp_start( void)
{
uintptr_t interrupt_stack_start = (uintptr_t) bsp_interrupt_stack_start;
uintptr_t interrupt_stack_size = (uintptr_t) bsp_interrupt_stack_size;
/*
* Get CPU identification dynamically. Note that the get_ppc_cpu_type()
* function stores the result in global variables so that it can be used
* later...
*/
get_ppc_cpu_type();
get_ppc_cpu_revision();
/* Basic CPU initialization */
cpu_init();
/*
* Enable instruction and data caches. Do not force writethrough mode.
*/
#if BSP_INSTRUCTION_CACHE_ENABLED
rtems_cache_enable_instruction();
#endif
#if BSP_DATA_CACHE_ENABLED
rtems_cache_enable_data();
#endif
/*
* This is evaluated during runtime, so it should be ok to set it
* before we initialize the drivers.
*/
/* Initialize some device driver parameters */
/*
* get the (internal) bus frequency
* NOTE: the external bus may be clocked at a lower speed
* but this does not concern the internal units like PIT,
* DEC, baudrate generator etc)
*/
if (RTEMS_SUCCESSFUL !=
bsp_tqm_get_cib_uint32("cu",
&BSP_bus_frequency)) {
rtems_panic("Cannot determine BUS frequency\n");
}
bsp_time_base_frequency = BSP_bus_frequency / 16;
bsp_clicks_per_usec = bsp_time_base_frequency / 1000000;
bsp_timer_least_valid = 3;
bsp_timer_average_overhead = 3;
rtems_counter_initialize_converter(bsp_time_base_frequency);
/* Initialize exception handler */
ppc_exc_initialize(interrupt_stack_start, interrupt_stack_size);
/* Initalize interrupt support */
bsp_interrupt_initialize();
#ifdef SHOW_MORE_INIT_SETTINGS
printk("Exit from bspstart\n");
#endif
}
void bsp_start(void)
{
ppc_cpu_id_t myCpu;
ppc_cpu_revision_t myCpuRevision;
/* Set MPC8260ADS board LEDS and Uart enable lines */
_BSP_GPLED0_off();
_BSP_GPLED1_off();
_BSP_Uart1_enable();
_BSP_Uart2_enable();
/*
* Get CPU identification dynamically. Note that the get_ppc_cpu_type() function
* store the result in global variables so that it can be used latter...
*/
myCpu = get_ppc_cpu_type();
myCpuRevision = get_ppc_cpu_revision();
cpu_init();
/*
mmu_init();
*/
/* Initialize exception handler */
/* FIXME: Interrupt stack begin and size */
ppc_exc_initialize(
(uintptr_t) IntrStack_start,
(uintptr_t) intrStack - (uintptr_t) IntrStack_start
);
/* Initalize interrupt support */
bsp_interrupt_initialize();
/*
mmu_init();
*/
/*
* Enable instruction and data caches. Do not force writethrough mode.
*/
#if BSP_INSTRUCTION_CACHE_ENABLED
rtems_cache_enable_instruction();
#endif
#if BSP_DATA_CACHE_ENABLED
rtems_cache_enable_data();
#endif
/*
* initialize the device driver parameters
*/
bsp_time_base_frequency = 10000000;
bsp_clicks_per_usec = 10; /* for 40MHz extclk */
bsp_serial_per_sec = 40000000;
bsp_serial_external_clock = 0;
bsp_serial_xon_xoff = 0;
bsp_serial_cts_rts = 0;
bsp_serial_rate = 9600;
bsp_timer_average_overhead = 3;
bsp_timer_least_valid = 3;
bsp_clock_speed = 40000000;
rtems_counter_initialize_converter(bsp_clock_speed);
#ifdef REV_0_2
/* set up some board specific registers */
m8260.siumcr &= 0xF3FFFFFF; /* set TBEN ** BUG FIX ** */
m8260.siumcr |= 0x08000000;
#endif
/* use BRG1 to generate 32kHz timebase */
/*
m8260.brgc1 = M8260_BRG_EN + (uint32_t)(((uint16_t)((40016384)/(32768)) - 1) << 1) + 0;
*/
#ifdef SHOW_MORE_INIT_SETTINGS
printk("Exit from bspstart\n");
#endif
}
/*
* bsp_start()
*
* Board-specific initialization code. Called from the generic boot_card()
* function defined in rtems/c/src/lib/libbsp/shared/main.c. That function
* does some of the board independent initialization. It is called from the
* MBX8xx entry point _start() defined in
* rtems/c/src/lib/libbsp/powerpc/mbx8xx/startup/start.S
*
* _start() has set up a stack, has zeroed the .bss section, has turned off
* interrupts, and placed the processor in the supervisor mode. boot_card()
* has left the processor in that state when bsp_start() was called.
*
* RUNS WITH ADDRESS TRANSLATION AND CACHING TURNED OFF!
* ASSUMES THAT THE VIRTUAL ADDRESSES WILL BE IDENTICAL TO THE PHYSICAL
* ADDRESSES. Software-controlled address translation would be required
* otherwise.
*
* Input parameters: NONE
*
* Output parameters: NONE
*
* Return values: NONE
*/
void bsp_start(void)
{
ppc_cpu_id_t myCpu;
ppc_cpu_revision_t myCpuRevision;
/*
* Get CPU identification dynamically. Note that the get_ppc_cpu_type() function
* store the result in global variables so that it can be used latter...
*/
myCpu = get_ppc_cpu_type();
myCpuRevision = get_ppc_cpu_revision();
mmu_init();
/*
* Enable instruction and data caches. Do not force writethrough mode.
*/
#if NVRAM_CONFIGURE == 1
if ( nvram->cache_mode & 0x02 )
rtems_cache_enable_instruction();
if ( nvram->cache_mode & 0x01 )
rtems_cache_enable_data();
#else
#if BSP_INSTRUCTION_CACHE_ENABLED
rtems_cache_enable_instruction();
#endif
#if BSP_DATA_CACHE_ENABLED
rtems_cache_enable_data();
#endif
#endif
/* Initialize exception handler */
ppc_exc_initialize(
(uintptr_t) IntrStack_start,
(uintptr_t) intrStack - (uintptr_t) IntrStack_start
);
/* Initalize interrupt support */
bsp_interrupt_initialize();
/*
* initialize the device driver parameters
*/
#if ( defined(mbx860_001b) || \
defined(mbx860_002b) || \
defined(mbx860_003b) || \
defined(mbx860_003b) || \
defined(mbx860_004b) || \
defined(mbx860_005b) || \
defined(mbx860_006b) || \
defined(mbx821_001b) || \
defined(mbx821_002b) || \
defined(mbx821_003b) || \
defined(mbx821_004b) || \
defined(mbx821_005b) || \
defined(mbx821_006b))
bsp_clicks_per_usec = 0; /* for 32768Hz extclk */
#else
bsp_clicks_per_usec = 1; /* for 4MHz extclk */
#endif
rtems_counter_initialize_converter(bsp_clicks_per_usec * 1000000);
bsp_serial_per_sec = 10000000;
bsp_serial_external_clock = true;
bsp_serial_xon_xoff = false;
bsp_serial_cts_rts = true;
bsp_serial_rate = 9600;
#if ( defined(mbx821_001) || defined(mbx821_001b) || defined(mbx860_001b) )
bsp_clock_speed = 50000000;
bsp_timer_average_overhead = 3;
bsp_timer_least_valid = 3;
#else
bsp_clock_speed = 40000000;
bsp_timer_average_overhead = 3;
bsp_timer_least_valid = 3;
#endif
m8xx.scc2.sccm=0;
m8xx.scc2p.rbase=0;
m8xx.scc2p.tbase=0;
m8xx_cp_execute_cmd( M8xx_CR_OP_STOP_TX | M8xx_CR_CHAN_SCC2 );
#ifdef SHOW_MORE_INIT_SETTINGS
printk("Exit from bspstart\n");
#endif
}
void bsp_start( void )
{
#if !defined(mvme2100)
unsigned l2cr;
#endif
uintptr_t intrStackStart;
uintptr_t intrStackSize;
prep_t boardManufacturer;
motorolaBoard myBoard;
Triv121PgTbl pt=0;
/*
* Get CPU identification dynamically. Note that the get_ppc_cpu_type()
* function store the result in global variables so that it can be used
* later...
*/
get_ppc_cpu_type();
get_ppc_cpu_revision();
/*
* Init MMU block address translation to enable hardware access
*/
#if !defined(mvme2100)
/*
* PC legacy IO space used for inb/outb and all PC compatible hardware
*/
setdbat(1, _IO_BASE, _IO_BASE, 0x10000000, IO_PAGE);
#endif
/*
* PCI devices memory area. Needed to access OpenPIC features
* provided by the Raven
*
* T. Straumann: give more PCI address space
*/
setdbat(2, PCI_MEM_BASE+PCI_MEM_WIN0, PCI_MEM_BASE+PCI_MEM_WIN0, 0x10000000, IO_PAGE);
/*
* Must have acces to open pic PCI ACK registers provided by the RAVEN
*/
#ifndef qemu
setdbat(3, 0xf0000000, 0xf0000000, 0x10000000, IO_PAGE);
#else
setdbat(3, 0xb0000000, 0xb0000000, 0x10000000, IO_PAGE);
#endif
#if defined(mvme2100)
/* Need 0xfec00000 mapped for this */
EUMBBAR = get_eumbbar();
#endif
/*
* enables L1 Cache. Note that the L1_caches_enables() codes checks for
* relevant CPU type so that the reason why there is no use of myCpu...
*/
L1_caches_enables();
select_console(CONSOLE_LOG);
/*
* We check that the keyboard is present and immediately
* select the serial console if not.
*/
#if defined(BSP_KBD_IOBASE)
{ int err;
err = kbdreset();
if (err) select_console(CONSOLE_SERIAL);
}
#else
select_console(CONSOLE_SERIAL);
#endif
#if !defined(mvme2100)
/*
* Enable L2 Cache. Note that the set_L2CR(L2CR) codes checks for
* relevant CPU type (mpc750)...
*/
l2cr = get_L2CR();
#ifdef SHOW_LCR2_REGISTER
printk("Initial L2CR value = %x\n", l2cr);
#endif
if ( (! (l2cr & 0x80000000)) && ((int) l2cr == -1))
set_L2CR(0xb9A14000);
#endif
/*
* Initialize the interrupt related settings.
*/
intrStackStart = (uintptr_t) __rtems_end;
intrStackSize = rtems_configuration_get_interrupt_stack_size();
/*
* Initialize default raw exception handlers.
*/
ppc_exc_initialize(intrStackStart, intrStackSize);
boardManufacturer = checkPrepBoardType(&residualCopy);
if (boardManufacturer != PREP_Motorola) {
printk("Unsupported hardware vendor\n");
while (1);
}
myBoard = getMotorolaBoard();
printk("-----------------------------------------\n");
printk("Welcome to %s on %s\n", _RTEMS_version,
motorolaBoardToString(myBoard));
printk("-----------------------------------------\n");
#ifdef SHOW_MORE_INIT_SETTINGS
printk("Residuals are located at %x\n", (unsigned) &residualCopy);
printk("Additionnal boot options are %s\n", loaderParam);
printk("Software IRQ stack starts at %x with size %u\n", intrStackStart, intrStackSize);
printk("-----------------------------------------\n");
#endif
#ifdef TEST_RETURN_TO_PPCBUG
printk("Hit <Enter> to return to PPCBUG monitor\n");
printk("When Finished hit GO. It should print <Back from monitor>\n");
debug_getc();
_return_to_ppcbug();
printk("Back from monitor\n");
_return_to_ppcbug();
#endif /* TEST_RETURN_TO_PPCBUG */
#ifdef SHOW_MORE_INIT_SETTINGS
printk("Going to start PCI buses scanning and initialization\n");
#endif
pci_initialize();
{
const struct _int_map *bspmap = motorolaIntMap(currentBoard);
if( bspmap ) {
printk("pci : Configuring interrupt routing for '%s'\n",
motorolaBoardToString(currentBoard));
FixupPCI(bspmap, motorolaIntSwizzle(currentBoard));
}
else
printk("pci : Interrupt routing not available for this bsp\n");
}
#ifdef SHOW_MORE_INIT_SETTINGS
printk("Number of PCI buses found is : %d\n", pci_bus_count());
#endif
#ifdef TEST_RAW_EXCEPTION_CODE
printk("Testing exception handling Part 1\n");
/*
* Cause a software exception
*/
__asm__ __volatile ("sc");
/*
* Check we can still catch exceptions and return coorectly.
*/
printk("Testing exception handling Part 2\n");
__asm__ __volatile ("sc");
/*
* Somehow doing the above seems to clobber SPRG0 on the mvme2100. The
* interrupt disable mask is stored in SPRG0. Is this a problem?
*/
ppc_interrupt_set_disable_mask( PPC_INTERRUPT_DISABLE_MASK_DEFAULT);
#endif
/* See above */
BSP_mem_size = residualCopy.TotalMemory;
BSP_bus_frequency = residualCopy.VitalProductData.ProcessorBusHz;
BSP_processor_frequency = residualCopy.VitalProductData.ProcessorHz;
BSP_time_base_divisor = (residualCopy.VitalProductData.TimeBaseDivisor?
residualCopy.VitalProductData.TimeBaseDivisor : 4000);
/* clear hostbridge errors but leave MCP disabled -
* PCI config space scanning code will trip otherwise :-(
*/
_BSP_clear_hostbridge_errors(0 /* enableMCP */, 0/*quiet*/);
/* Allocate and set up the page table mappings
* This is only available on >604 CPUs.
*
* NOTE: This setup routine may modify the available memory
* size. It is essential to call it before
* calculating the workspace etc.
*/
pt = BSP_pgtbl_setup(&BSP_mem_size);
if (!pt || TRIV121_MAP_SUCCESS != triv121PgTblMap(
pt, TRIV121_121_VSID,
#ifndef qemu
0xfeff0000,
#else
0xbffff000,
#endif
1,
TRIV121_ATTR_IO_PAGE, TRIV121_PP_RW_PAGE)) {
printk("WARNING: unable to setup page tables VME "
"bridge must share PCI space\n");
}
/*
* initialize the device driver parameters
*/
bsp_clicks_per_usec = BSP_bus_frequency/(BSP_time_base_divisor * 1000);
rtems_counter_initialize_converter(
BSP_bus_frequency / (BSP_time_base_divisor / 1000)
);
/*
* Initalize RTEMS IRQ system
*/
BSP_rtems_irq_mng_init(0);
/* Activate the page table mappings only after
* initializing interrupts because the irq_mng_init()
* routine needs to modify the text
*/
if (pt) {
#ifdef SHOW_MORE_INIT_SETTINGS
printk("Page table setup finished; will activate it NOW...\n");
#endif
BSP_pgtbl_activate(pt);
/* finally, switch off DBAT3 */
setdbat(3, 0, 0, 0, 0);
}
#if defined(DEBUG_BATS)
ShowBATS();
#endif
#ifdef SHOW_MORE_INIT_SETTINGS
printk("Exit from bspstart\n");
#endif
}
/*
* BSP start routine. Called by boot_card().
*
* This routine does the bulk of the system initialization.
*/
void bsp_start(void)
{
uintptr_t intrStackStart;
uintptr_t intrStackSize;
ppc_cpu_id_t myCpu;
ppc_cpu_revision_t myCpuRevision;
/* Set the character output function; The application may override this */
BSP_output_char = __bsp_outchar_to_memory;
printk("RTEMS %s\n", rtems_get_version_string());
/*
* Get CPU identification dynamically. Note that the get_ppc_cpu_type()
* function stores the result in global variables so that it can be used later...
*/
myCpu = get_ppc_cpu_type();
myCpuRevision = get_ppc_cpu_revision();
printk("CPU: 0x%04x, Revision: 0x%04x = %d, Name: %s\n",
myCpu, myCpuRevision, myCpuRevision, get_ppc_cpu_type_name(myCpu));
/*
* Initialize the device driver parameters
*/
/* Timebase register ticks/microsecond; The application may override these */
bsp_clicks_per_usec = 350;
bsp_timer_internal_clock = true;
bsp_timer_average_overhead = 2;
bsp_timer_least_valid = 3;
rtems_counter_initialize_converter(bsp_clicks_per_usec * 1000000);
/*
* Initialize the interrupt related settings.
*/
intrStackStart = CPU_UP_ALIGN((uint32_t)__bsp_ram_start);
intrStackSize = rtems_configuration_get_interrupt_stack_size();
ppc_exc_initialize(intrStackStart, intrStackSize);
/* Let the user know what parameters we were compiled with */
printk(" Base/Start End Size\n"
"RAM: 0x%08x 0x%x\n"
"RTEMS: 0x%08x\n"
"Interrupt Stack: 0x%08x 0x%x\n"
"Stack: 0x%08x 0x%08x 0x%x\n"
"Workspace: 0x%08x 0x%08x\n"
"MsgArea: 0x%08x 0x%x\n"
"Physical RAM 0x%08x\n",
(uint32_t)RamBase, (uint32_t)RamSize,
(uint32_t)__rtems_end,
intrStackStart, intrStackSize,
(uint32_t)__stack_base, (uint32_t)_stack, (uint32_t)StackSize,
(uint32_t)WorkAreaBase, (uint32_t)__bsp_ram_end,
(uint32_t)MsgAreaBase, (uint32_t)MsgAreaSize,
(uint32_t)__phy_ram_end);
/*
* Initialize RTEMS IRQ system
*/
BSP_rtems_irq_mngt_init(0);
/* Continue with application-specific initialization */
app_bsp_start();
}
void bsp_start(void)
{
unsigned long i = 0;
/*
* Get CPU identification dynamically. Note that the get_ppc_cpu_type() function
* store the result in global variables so that it can be used latter...
*/
get_ppc_cpu_type();
get_ppc_cpu_revision();
/* Initialize some device driver parameters */
#ifdef HAS_UBOOT
BSP_bus_frequency = bsp_uboot_board_info.bi_busfreq
/ QORIQ_BUS_CLOCK_DIVIDER;
bsp_clicks_per_usec = BSP_bus_frequency / 8000000;
rtems_counter_initialize_converter(
#ifdef __PPC_CPU_E6500__
bsp_uboot_board_info.bi_intfreq
#else
BSP_bus_frequency / 8
#endif
);
#endif /* HAS_UBOOT */
/* Initialize some console parameters */
for (i = 0; i < console_device_count; ++i) {
const console_device *dev = &console_device_table[i];
const rtems_termios_device_handler *ns16550 =
#ifdef BSP_USE_UART_INTERRUPTS
&ns16550_handler_interrupt;
#else
&ns16550_handler_polled;
#endif
if (dev->handler == ns16550) {
ns16550_context *ctx = (ns16550_context *) dev->context;
ctx->clock = BSP_bus_frequency;
#ifdef HAS_UBOOT
#ifdef U_BOOT_GENERIC_BOARD_INFO
ctx->initial_baud = 115200;
#else
ctx->initial_baud = bsp_uboot_board_info.bi_baudrate;
#endif
#endif
}
}
/* Initialize exception handler */
ppc_exc_initialize_with_vector_base(
(uintptr_t) bsp_section_work_begin,
rtems_configuration_get_interrupt_stack_size(),
bsp_exc_vector_base
);
/* Now it is possible to make the code execute only */
qoriq_mmu_change_perm(
FSL_EIS_MAS3_SR | FSL_EIS_MAS3_SX,
FSL_EIS_MAS3_SX,
FSL_EIS_MAS3_SR
);
/* Initalize interrupt support */
bsp_interrupt_initialize();
rtems_cache_coherent_add_area(
bsp_section_nocacheheap_begin,
(uintptr_t) bsp_section_nocacheheap_size
);
/* Disable boot page translation */
#if QORIQ_CHIP_IS_T_VARIANT(QORIQ_CHIP_VARIANT)
qoriq.lcc.bstar &= ~LCC_BSTAR_EN;
#else
qoriq.lcc.bptr &= ~BPTR_EN;
#endif
}
/**
* @brief Initialize the HW peripheral for clock driver
*
* Clock driver is implemented by RTI module
*
* @retval Void
*/
static void tms570_clock_driver_support_initialize_hardware( void )
{
uint32_t microsec_per_tick;
uint32_t tc_frequency;
uint32_t tc_prescaler;
uint32_t tc_increments_per_tick;
microsec_per_tick = rtems_configuration_get_microseconds_per_tick();
tc_frequency = TMS570_PREFERRED_TC_FREQUENCY;
rtems_counter_initialize_converter(BSP_PLL_OUT_CLOCK);
tc_prescaler = (BSP_PLL_OUT_CLOCK + tc_frequency) / (tc_frequency * 2);
/* Recompute actual most close frequency which can be realized */
tc_frequency = (BSP_PLL_OUT_CLOCK + tc_prescaler) / (tc_prescaler * 2);
/*
* Recompute tick period to adjust for configurable or exact
* preferred time base 1 usec resolution.
*/
tc_increments_per_tick = ((uint64_t)microsec_per_tick * tc_frequency +
500000) / 1000000;
/* Hardware specific initialize */
TMS570_RTI.GCTRL = 0;
TMS570_RTI.CNT[0].CPUCx = tc_prescaler - 1;
TMS570_RTI.TBCTRL = TMS570_RTI_TBCTRL_INC;
TMS570_RTI.CAPCTRL = 0;
TMS570_RTI.COMPCTRL = 0;
/* set counter to zero */
TMS570_RTI.CNT[0].UCx = 0;
TMS570_RTI.CNT[0].FRCx = 0;
/* clear interrupts*/
TMS570_RTI.CLEARINTENA = TMS570_RTI_CLEARINTENA_CLEAROVL1INT |
TMS570_RTI_CLEARINTENA_CLEAROVL0INT |
TMS570_RTI_CLEARINTENA_CLEARTBINT |
TMS570_RTI_CLEARINTENA_CLEARDMA3 |
TMS570_RTI_CLEARINTENA_CLEARDMA2 |
TMS570_RTI_CLEARINTENA_CLEARDMA1 |
TMS570_RTI_CLEARINTENA_CLEARDMA0 |
TMS570_RTI_CLEARINTENA_CLEARINT3 |
TMS570_RTI_CLEARINTENA_CLEARINT2 |
TMS570_RTI_CLEARINTENA_CLEARINT1 |
TMS570_RTI_CLEARINTENA_CLEARINT0;
TMS570_RTI.INTFLAG = TMS570_RTI_INTFLAG_OVL1INT |
TMS570_RTI_INTFLAG_OVL0INT |
TMS570_RTI_INTFLAG_TBINT |
TMS570_RTI_INTFLAG_INT3 |
TMS570_RTI_INTFLAG_INT2 |
TMS570_RTI_INTFLAG_INT1 |
TMS570_RTI_INTFLAG_INT0;
/* set timer */
TMS570_RTI.CMP[0].COMPx = TMS570_RTI.CNT[0].FRCx + tc_increments_per_tick;
TMS570_RTI.COMP0CLR = TMS570_RTI.CMP[0].COMPx + tc_increments_per_tick / 2;
TMS570_RTI.CMP[0].UDCPx = tc_increments_per_tick;
/* enable interupt */
TMS570_RTI.SETINTENA = TMS570_RTI_SETINTENA_SETINT0;
/* enable timer */
TMS570_RTI.GCTRL = TMS570_RTI_GCTRL_CNT0EN;
/* set timecounter */
tms570_rti_tc.tc_get_timecount = tms570_rti_get_timecount;
tms570_rti_tc.tc_counter_mask = 0xffffffff;
tms570_rti_tc.tc_frequency = tc_frequency;
tms570_rti_tc.tc_quality = RTEMS_TIMECOUNTER_QUALITY_CLOCK_DRIVER;
rtems_timecounter_install(&tms570_rti_tc);
}
