/*
* sh4uart_disable --
* This function disable the operations on SH-4 UART controller
*
* PARAMETERS:
* uart - pointer to UART channel descriptor structure
* disable_port - disable receive and transmit on the port
*
* RETURNS:
* RTEMS_SUCCESSFUL if UART closed successfuly, or error code in
* other case
*/
rtems_status_code
sh4uart_disable(sh4uart *uart, int disable_port)
{
rtems_status_code rc;
if (disable_port) {
if ( uart->chn == 1 ) {
volatile uint8_t *scr = (volatile uint8_t *)SH7750_SCSCR1;
*scr &= ~(SH7750_SCSCR_TE | SH7750_SCSCR_RE);
} else {
volatile uint16_t *scr = (volatile uint16_t *)SH7750_SCSCR2;
*scr &= ~(SH7750_SCSCR_TE | SH7750_SCSCR_RE);
}
}
if (uart->int_driven) {
rc = rtems_interrupt_catch(uart->old_handler_transmit,
uart->chn == SH4_SCI ? SH7750_EVT_SCI_TXI : SH7750_EVT_SCIF_TXI,
NULL);
if (rc != RTEMS_SUCCESSFUL)
return rc;
rc = rtems_interrupt_catch(uart->old_handler_receive,
uart->chn == SH4_SCI ? SH7750_EVT_SCI_RXI : SH7750_EVT_SCIF_RXI,
NULL);
if (rc != RTEMS_SUCCESSFUL)
return rc;
}
return RTEMS_SUCCESSFUL;
}
int rtems_minimac_driver_attach(struct rtems_bsdnet_ifconfig *config,
int attaching)
{
struct ifnet *ifp;
rtems_isr_entry dummy;
int i;
static int registered;
uint8_t *tx_buffer = (uint8_t *)MINIMAC_TX_BASE;
if(!attaching) {
printk("Minimac driver cannot be detached.\n");
return 0;
}
ifp = &(arpcom.ac_if);
if(registered) {
printk("Minimac driver already in use.\n");
return 0;
}
registered = 1;
memcpy(arpcom.ac_enaddr, get_mac_address(), 6);
ifp->if_mtu = ETHERMTU;
ifp->if_unit = 0;
ifp->if_name = "minimac";
ifp->if_init = minimac_init;
ifp->if_ioctl = minimac_ioctl;
ifp->if_start = minimac_start;
ifp->if_output = ether_output;
ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX;
ifp->if_snd.ifq_maxlen = ifqmaxlen;
if_attach(ifp);
ether_ifattach(ifp);
rx_daemon_id = rtems_bsdnet_newproc("mrxd", 4096, rx_daemon, NULL);
tx_daemon_id = rtems_bsdnet_newproc("mtxd", 4096, tx_daemon, NULL);
rtems_interrupt_catch(rx_interrupt_handler, MM_IRQ_ETHRX, &dummy);
rtems_interrupt_catch(tx_interrupt_handler, MM_IRQ_ETHTX, &dummy);
MM_WRITE(MM_MINIMAC_STATE0, MINIMAC_STATE_LOADED);
MM_WRITE(MM_MINIMAC_STATE1, MINIMAC_STATE_LOADED);
for(i=0;i<7; i++)
tx_buffer[i] = 0x55;
tx_buffer[7] = 0xd5;
MM_WRITE(MM_MINIMAC_SETUP, 0);
rtems_bsdnet_event_send(tx_daemon_id, CTS_EVENT);
bsp_interrupt_vector_enable(MM_IRQ_ETHRX);
bsp_interrupt_vector_enable(MM_IRQ_ETHTX);
return 1;
}
rtems_task Init(
rtems_task_argument argument
)
{
TEST_BEGIN();
#if (CPU_SIMPLE_VECTORED_INTERRUPTS == FALSE)
puts(
"TA1 - rtems_interrupt_catch - "
"bad handler RTEMS_INVALID_ADDRESS -- SKIPPED"
);
puts(
"TA1 - rtems_interrupt_catch - "
"old isr RTEMS_INVALID_ADDRESS - SKIPPED" );
#else
rtems_status_code status;
rtems_isr_entry old_service_routine;
status = rtems_interrupt_catch(
Service_routine,
CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER + 1,
&old_service_routine
);
fatal_directive_status(
status,
RTEMS_INVALID_NUMBER,
"rtems_interrupt_catch with invalid vector"
);
puts( "TA1 - rtems_interrupt_catch - RTEMS_INVALID_NUMBER" );
status = rtems_interrupt_catch( NULL, 3, &old_service_routine );
fatal_directive_status(
status,
RTEMS_INVALID_ADDRESS,
"rtems_interrupt_catch with invalid handler"
);
puts( "TA1 - rtems_interrupt_catch - bad handler RTEMS_INVALID_ADDRESS" );
status = rtems_interrupt_catch( Service_routine, 3, NULL );
fatal_directive_status(
status,
RTEMS_INVALID_ADDRESS,
"rtems_interrupt_catch with invalid old isr pointer"
);
puts( "TA1 - rtems_interrupt_catch - old isr RTEMS_INVALID_ADDRESS" );
#endif
TEST_END();
}
void
__gnat_install_handler_common (int t1, int t2)
{
uint32_t trap;
rtems_isr_entry previous_isr;
sigaction (SIGSEGV, &__gnat_error_vector, NULL);
sigaction (SIGFPE, &__gnat_error_vector, NULL);
sigaction (SIGILL, &__gnat_error_vector, NULL);
for (trap = 0; trap < 256; trap++)
{
/*
* Skip window overflow, underflow, and flush as well as software
* trap 0 which we will use as a shutdown. Also avoid trap 0x70 - 0x7f
* which cannot happen and where some of the space is used to pass
* paramaters to the program. 0x80 for system traps and
* 0x81 - 0x83 by the remote debugging stub.
* Avoid two bsp specific interrupts which normally are used
* by the real-time clock and UART B.
*/
if ((trap >= 0x11) && (trap <= 0x1f))
{
if ((trap != t1) && (trap != t2))
rtems_interrupt_catch (__gnat_interrupt_handler, trap, &previous_isr);
}
else if ((trap != 5 && trap != 6) && ((trap < 0x70) || (trap > 0x83)))
set_vector (__gnat_exception_handler, SPARC_SYNCHRONOUS_TRAP (trap), 1);
}
}
rtems_device_driver ir_initialize(
rtems_device_major_number major,
rtems_device_minor_number minor,
void *arg
)
{
rtems_status_code sc;
rtems_isr_entry dummy;
sc = rtems_io_register_name(DEVICE_NAME, major, 0);
RTEMS_CHECK_SC(sc, "create IR input device");
sc = rtems_message_queue_create(
rtems_build_name('R', 'C', '5', 'Q'),
64,
2,
0,
&ir_q
);
RTEMS_CHECK_SC(sc, "create IR queue");
rtems_interrupt_catch(interrupt_handler, MM_IRQ_IR, &dummy);
bsp_interrupt_vector_enable(MM_IRQ_IR);
return RTEMS_SUCCESSFUL;
}
int
rtems_gdb_tgt_install_ehandler(int action)
{
int rval = 0, i;
/* initialize breakpoint table */
for ( i=0; i<NUM_BPNTS-1; i++ )
bpntTab[i].next = bpntTab+i+1;
bpntsFree = bpntTab;
if ( action ) {
/* install */
for ( i = 0; i<sizeof(origHandlerTbl)/sizeof(origHandlerTbl[0]); i++ ) {
if ( rtems_interrupt_catch(_m68k_gdb_exception_wrapper, origHandlerTbl[i].vec, &origHandlerTbl[i].hdl) ) {
origHandlerTbl[i].hdl = 0;
isr_restore(i);
rval = -1;
break;
}
}
} else {
/* uninstall */
rval = isr_restore(sizeof(origHandlerTbl)/sizeof(origHandlerTbl[0]));
}
if ( rval ) {
ERRMSG("ERROR: exception handler %s\n",
action ? "already installed" : "cannot be removed; uninstall failed");
}
return rval;
}
rtems_device_driver pfpu_initialize(
rtems_device_major_number major,
rtems_device_minor_number minor,
void *arg
)
{
rtems_status_code sc;
rtems_isr_entry dummy;
sc = rtems_io_register_name(DEVICE_NAME, major, 0);
RTEMS_CHECK_SC(sc, "create PFPU device");
sc = rtems_semaphore_create(
rtems_build_name('P', 'F', 'P', 'U'),
0,
RTEMS_SIMPLE_BINARY_SEMAPHORE,
0,
&done_sem
);
RTEMS_CHECK_SC(sc, "create PFPU done semaphore");
rtems_interrupt_catch(done_handler, MM_IRQ_PFPU, &dummy);
bsp_interrupt_vector_enable(MM_IRQ_PFPU);
return RTEMS_SUCCESSFUL;
}
rtems_device_driver usbinput_initialize(
rtems_device_major_number major,
rtems_device_minor_number minor,
void *arg
)
{
rtems_status_code sc;
rtems_isr_entry dummy;
MM_WRITE(MM_SOFTUSB_CONTROL, SOFTUSB_CONTROL_RESET);
mouse_consume = 0;
keyboard_consume = 0;
midi_consume = 0;
sc = rtems_io_register_name(DEVICE_NAME, major, 0);
RTEMS_CHECK_SC(sc, "create USB input device");
sc = rtems_message_queue_create(
rtems_build_name('U', 'S', 'B', 'I'),
64,
8,
0,
&event_q
);
RTEMS_CHECK_SC(sc, "create USB event queue");
rtems_interrupt_catch(interrupt_handler, MM_IRQ_USB, &dummy);
bsp_interrupt_vector_enable(MM_IRQ_USB);
return RTEMS_SUCCESSFUL;
}
rtems_device_driver Clock_control(
rtems_device_major_number major,
rtems_device_minor_number minor,
void *pargp
)
{
uint32_t isrlevel;
rtems_libio_ioctl_args_t *args = pargp;
if (args != 0)
{
/*
* This is hokey, but until we get a defined interface
* to do this, it will just be this simple...
*/
if (args->command == rtems_build_name('I', 'S', 'R', ' '))
{
Clock_isr(CLOCK_VECTOR);
}
else if (args->command == rtems_build_name('N', 'E', 'W', ' '))
{
rtems_isr_entry ignored ;
rtems_interrupt_disable( isrlevel );
rtems_interrupt_catch( args->buffer, CLOCK_VECTOR, &ignored );
rtems_interrupt_enable( isrlevel );
}
}
return RTEMS_SUCCESSFUL;
}
rtems_isr_entry set_vector( /* returns old vector */
rtems_isr_entry handler, /* isr routine */
rtems_vector_number vector, /* vector number */
int type /* RTEMS or RAW intr */
)
{
rtems_isr_entry previous_isr;
uint32_t real_trap;
uint32_t source;
if ( type == SET_VECTOR_INT )
rtems_interrupt_catch( handler, vector, &previous_isr );
else
_CPU_ISR_install_raw_handler( vector, handler, (void *)&previous_isr );
real_trap = SPARC_REAL_TRAP_NUMBER( vector );
if ( ERC32_Is_MEC_Trap( real_trap ) ) {
source = ERC32_TRAP_SOURCE( real_trap );
ERC32_Clear_interrupt( source );
ERC32_Unmask_interrupt( source );
}
return previous_isr;
}
/*
* Initialization of interrupts
*
* Interrupts can be started only after opening a device, so interrupt
* flags are set up in sh_sci_first_open function
*/
void sh_sci_initialize_interrupts(int minor)
{
rtems_isr_entry old_isr;
rtems_status_code status;
sh_sci_init(minor);
/*
* Disable IRQ of SCIx
*/
status = sh_set_irq_priority( Console_Port_Tbl[minor]->ulIntVector, 0);
if (status != RTEMS_SUCCESSFUL)
rtems_fatal_error_occurred(status);
SH_SCI_REG_MASK(SCI_RIE, minor, SCI_SCR);
/*
* Catch apropriate vectors
*/
status = rtems_interrupt_catch(
sh_sci_rx_isr,
Console_Port_Tbl[minor]->ulIntVector,
&old_isr);
if (status != RTEMS_SUCCESSFUL)
rtems_fatal_error_occurred(status);
status = rtems_interrupt_catch(
sh_sci_tx_isr,
Console_Port_Tbl[minor]->ulDataPort,
&old_isr);
if (status != RTEMS_SUCCESSFUL)
rtems_fatal_error_occurred(status);
/*
* Enable IRQ of SCIx
*/
SH_SCI_REG_FLAG(SCI_RIE, minor, SCI_SCR);
status = sh_set_irq_priority(
Console_Port_Tbl[minor]->ulIntVector,
Console_Port_Tbl[minor]->ulCtrlPort2);
if (status != RTEMS_SUCCESSFUL)
rtems_fatal_error_occurred(status);
}
void
ReInstall_clock(rtems_isr_entry new_clock_isr)
{
rtems_isr_entry previous_isr;
rtems_unsigned32 isrlevel = 0;
rtems_interrupt_disable(isrlevel);
rtems_interrupt_catch(new_clock_isr, PPC_IRQ_LVL0, &previous_isr);
rtems_interrupt_enable(isrlevel);
}
rtems_isr_entry set_vector( /* returns old vector */
rtems_isr_entry handler, /* isr routine */
rtems_vector_number vector, /* vector number */
int type /* RTEMS or RAW intr */
)
{
rtems_isr_entry previous_isr;
if ( type )
rtems_interrupt_catch( handler, vector, &previous_isr );
else
_CPU_ISR_install_raw_handler( vector, handler, (void *)&previous_isr );
return previous_isr;
}
rtems_isr_entry set_vector( /* returns old vector */
rtems_isr_entry handler, /* isr routine */
rtems_vector_number vector, /* vector number */
int type /* RTEMS or RAW intr */
)
{
rtems_isr_entry previous_isr;
if ( type )
rtems_interrupt_catch( handler, vector, (rtems_isr_entry *) &previous_isr );
else {
/* XXX: install non-RTEMS ISR as "raw" interupt */
}
return previous_isr;
}
/* Initialize interrupts */
int BSP_shared_interrupt_init(void)
{
rtems_vector_number vector;
rtems_isr_entry previous_isr;
int sc, i;
for (i=0; i <= BSP_INTERRUPT_VECTOR_MAX_STD; i++) {
vector = SPARC_ASYNCHRONOUS_TRAP(i) + 0x10;
rtems_interrupt_catch(BSP_ISR_handler, vector, &previous_isr);
}
/* Initalize interrupt support */
sc = bsp_interrupt_initialize();
if (sc != RTEMS_SUCCESSFUL)
return -1;
return 0;
}
/*=========================================================================*\
| Function: |
\*-------------------------------------------------------------------------*/
void mcdma_glue_init
(
/*-------------------------------------------------------------------------*\
| Purpose: |
| initialize the mcdma module (if not yet done): |
| - load code |
| - initialize registers |
| - initialize bus arbiter |
| - initialize interrupt control |
+---------------------------------------------------------------------------+
| Input Parameters: |
\*-------------------------------------------------------------------------*/
void *sram_base /* base address for SRAM, to be used for DMA task */
)
/*-------------------------------------------------------------------------*\
| Return Value: |
| none |
\*=========================================================================*/
{
rtems_isr_entry old_handler;
if (!mcdma_glue_is_initialized) {
mcdma_glue_is_initialized = true;
MCD_initDma((dmaRegs *)&MCF548X_DMA_TASKBAR,
sram_base,
MCD_TT_FLAGS_DEF);
/*
* initialize interrupt dispatcher
*/
if(rtems_interrupt_catch(mcdma_glue_irq_dispatcher,
MCDMA_IRQ_VECTOR,
&old_handler)) {
rtems_panic ("Can't attach MFC548x MCDma interrupt handler\n");
}
MCF548X_INTC_ICRn(MCDMA_IRQ_VECTOR - 64) =
MCF548X_INTC_ICRn_IL(MCDMA_IRQ_LEVEL) |
MCF548X_INTC_ICRn_IP(MCDMA_IRQ_PRIORITY);
MCF548X_INTC_IMRH &= ~(1 << (MCDMA_IRQ_VECTOR % 32));
}
}
static int
isr_restore(int n)
{
int rval = 0;
rtems_isr (*dummy)(rtems_vector_number);
while (--n >= 0) {
if ( ! origHandlerTbl[n].hdl ) {
if ( ! rtems_gdb_nounload ) {
/* if no handler was registered earlier then we're hosed */
fprintf(stderr,"Cannot uninstall exception handler -- no old handler known\n");
fprintf(stderr,"I'll install a dummy handler and lock this module in memory\n");
rtems_gdb_nounload = 1;
}
origHandlerTbl[n].hdl = dummyHandler;
}
rval = (rval || rtems_interrupt_catch(origHandlerTbl[n].hdl, origHandlerTbl[n].vec, &dummy));
origHandlerTbl[n].hdl = 0;
}
return rval;
}
rtems_device_driver console_initialize(
rtems_device_major_number major,
rtems_device_minor_number minor,
void *arg
)
{
rtems_status_code status;
rtems_isr_entry dummy;
rtems_termios_initialize();
status = rtems_io_register_name("/dev/console", major, 0);
if (status != RTEMS_SUCCESSFUL)
rtems_fatal_error_occurred(status);
rtems_interrupt_catch(mmconsole_interrupt, MM_IRQ_UART, &dummy);
bsp_interrupt_vector_enable(MM_IRQ_UART);
MM_WRITE(MM_UART_CTRL, UART_CTRL_RX_INT|UART_CTRL_TX_INT);
return RTEMS_SUCCESSFUL;
}
void Install_clock(rtems_isr_entry clock_isr)
{
rtems_isr_entry previous_isr;
rtems_unsigned32 pit_value;
Clock_driver_ticks = 0;
pit_value = rtems_configuration_get_microseconds_per_tick() /
rtems_cpu_configuration_get_clicks_per_usec();
if (pit_value == 0) {
pit_value = 0xffff;
} else {
pit_value--;
}
if (pit_value > 0xffff) { /* pit is only 16 bits long */
rtems_fatal_error_occurred(-1);
}
/*
* initialize the interval here
* First tick is set to right amount of time in the future
* Future ticks will be incremented over last value set
* in order to provide consistent clicks in the face of
* interrupt overhead
*/
rtems_interrupt_catch(clock_isr, PPC_IRQ_LVL0, &previous_isr);
m821.sccr &= ~(1<<24);
m821.pitc = pit_value;
/* set PIT irq level, enable PIT, PIT interrupts */
/* and clear int. status */
m821.piscr = M821_PISCR_PIRQ(0) |
M821_PISCR_PTE | M821_PISCR_PS | M821_PISCR_PIE;
m821.simask |= M821_SIMASK_LVM0;
atexit(Clock_exit);
}
rtems_device_driver video_initialize(
rtems_device_major_number major,
rtems_device_minor_number minor,
void *arg
)
{
rtems_status_code sc;
rtems_isr_entry dummy;
int i;
MM_WRITE(MM_BT656_I2C, BT656_I2C_SDC);
sc = rtems_io_register_name(DEVICE_NAME, major, 0);
RTEMS_CHECK_SC(sc, "create video input device");
rtems_interrupt_catch(frame_handler, MM_IRQ_VIDEOIN, &dummy);
bsp_interrupt_vector_enable(MM_IRQ_VIDEOIN);
for(i=0;i<sizeof(vreg_addr);i++)
write_reg(vreg_addr[i], vreg_dat[i]);
return RTEMS_SUCCESSFUL;
}
/*
* sh4uart_reset --
* This function perform the hardware initialization of SH-4
* on-chip UART controller using parameters
* filled by the sh4uart_init function.
*
* PARAMETERS:
* uart - pointer to UART channel descriptor structure
*
* RETURNS:
* RTEMS_SUCCESSFUL if channel is initialized successfully, error
* code in other case
*/
rtems_status_code
sh4uart_reset(sh4uart *uart)
{
register int chn;
register int int_driven;
rtems_status_code rc;
uint16_t tmp;
if (uart == NULL)
return RTEMS_INVALID_ADDRESS;
chn = uart->chn;
int_driven = uart->int_driven;
if ( chn == 1 ) {
volatile uint8_t *scr1 = (volatile uint8_t *)SH7750_SCSCR1;
volatile uint8_t *smr1 = (volatile uint8_t *)SH7750_SCSMR1;
*scr1 = 0x0; /* Is set properly at the end of this function */
*smr1 = 0x0; /* 8-bit, non-parity, 1 stop bit, pf/1 clock */
} else {
volatile uint16_t *scr2 = (volatile uint16_t *)SH7750_SCSCR2;
volatile uint16_t *smr2 = (volatile uint16_t *)SH7750_SCSMR2;
*scr2 = 0x0; /* Is set properly at the end of this function */
*smr2 = 0x0; /* 8-bit, non-parity, 1 stop bit, pf/1 clock */
}
if (chn == SH4_SCIF)
SCFCR2 = SH7750_SCFCR2_TFRST | SH7750_SCFCR2_RFRST |
SH7750_SCFCR2_RTRG_1 | SH7750_SCFCR2_TTRG_4;
if (chn == SH4_SCI)
SCSPTR1 = int_driven ? 0x0 : SH7750_SCSPTR1_EIO;
else
SCSPTR2 = SH7750_SCSPTR2_RTSDT;
if (int_driven) {
uint16_t ipr;
if (chn == SH4_SCI) {
ipr = IPRB;
ipr &= ~SH7750_IPRB_SCI1;
ipr |= SH4_UART_INTERRUPT_LEVEL << SH7750_IPRB_SCI1_S;
IPRB = ipr;
rc = rtems_interrupt_catch(sh4uart1_interrupt_transmit,
SH7750_EVT_TO_NUM(SH7750_EVT_SCI_TXI),
&uart->old_handler_transmit);
if (rc != RTEMS_SUCCESSFUL)
return rc;
rc = rtems_interrupt_catch(sh4uart1_interrupt_receive,
SH7750_EVT_TO_NUM(SH7750_EVT_SCI_RXI),
&uart->old_handler_receive);
if (rc != RTEMS_SUCCESSFUL)
return rc;
} else {
ipr = IPRC;
ipr &= ~SH7750_IPRC_SCIF;
ipr |= SH4_UART_INTERRUPT_LEVEL << SH7750_IPRC_SCIF_S;
IPRC = ipr;
rc = rtems_interrupt_catch(sh4uart2_interrupt_transmit,
SH7750_EVT_TO_NUM(SH7750_EVT_SCIF_TXI),
&uart->old_handler_transmit);
if (rc != RTEMS_SUCCESSFUL)
return rc;
rc = rtems_interrupt_catch(sh4uart2_interrupt_receive,
SH7750_EVT_TO_NUM(SH7750_EVT_SCIF_RXI),
&uart->old_handler_receive);
if (rc != RTEMS_SUCCESSFUL)
return rc;
}
uart->tx_buf = NULL;
uart->tx_ptr = uart->tx_buf_len = 0;
}
sh4uart_set_baudrate(uart, B38400); /* debug defaults (unfortunately,
it is differ to termios default */
tmp = SH7750_SCSCR_TE | SH7750_SCSCR_RE |
(chn == SH4_SCI ? 0x0 : SH7750_SCSCR2_REIE) |
(int_driven ? (SH7750_SCSCR_RIE | SH7750_SCSCR_TIE) : 0x0);
if ( chn == 1 ) {
volatile uint8_t *scr = (volatile uint8_t *)SH7750_SCSCR1;
*scr = tmp;
} else {
volatile uint16_t *scr = (volatile uint16_t *)SH7750_SCSCR2;
*scr = tmp;
}
return RTEMS_SUCCESSFUL;
}
/**
* Should be called at the beginning of the program to set up the
* network interface. It does the
* actual setup of the hardware.
*
* This function should be passed as a parameter to netif_add().
*
* @param netif the lwip network interface structure for this ethernetif
* @return ERR_OK if the interface is initialized
* We always return ERR_OK
*/
err_t
mcf5225xif_init(struct netif *netif)
{
rtems_isr_entry old_isr_handler;
struct if_config* if_config=netif->state;
net_task_id=if_config->net_task;
/* We directly use etharp_output() here to save a function call.
* You can instead declare your own function an call etharp_output()
* from it if you have to do some checks before sending (e.g. if link
* is available...) */
netif->output = etharp_output;
netif->linkoutput = low_level_output;
#if LWIP_NETIF_STATUS_CALLBACK
netif->status_callback = mcf5225xif_status;
#endif
#if LWIP_NETIF_LINK_CALLBACK
netif->link_callback = mcf5225xif_link;
#endif
netif->name[0]=if_config->name[0];
netif->name[1]=if_config->name[1];
netif->hwaddr_len = if_config->hwaddr_len;
memcpy(netif->hwaddr,if_config->hwaddr,ETHARP_HWADDR_LEN); /* set the mac address configured by the application */
netif->mtu = if_config->mtu ; /* maximum transfer unit, configured by application */
netif->flags = if_config->flags; /* device capabilities, configured by application */
MCF_FEC_ECR |= MCF_FEC_ECR_RESET;
while (MCF_FEC_ECR&MCF_FEC_ECR_RESET) __asm__ ("nop");
if (if_config->phy_init) if_config->phy_init(); /* call application specific optional extern phy initialization function */
MCF_FEC_EIMR = 0;
MCF_FEC_EIR= 0xFFFFFFFF;
//~ Set MAC hardware address:
MCF_FEC_PALR = (u32_t)( (netif->hwaddr[0] << 24)
| (netif->hwaddr[1] << 16)
| (netif->hwaddr[2] << 8 )
| (netif->hwaddr[3] << 0 ) );
MCF_FEC_PAUR = (u32_t)( (netif->hwaddr[4] << 24)
| (netif->hwaddr[5] << 16) );
/* Do whatever else is needed to initialize interface. */
MCF_FEC_OPD |= MCF_FEC_OPD_PAUSE_DUR(2); /* pause duration: send 2 pause frames */
MCF_FEC_IAUR = 0;
MCF_FEC_IALR = 0;
MCF_FEC_GAUR = 0;
MCF_FEC_GALR = 0;
MCF_FEC_EMRBR = ((MAX_FRAME_LEN+15)&~15); //<<4; //RX_RING_SIZE*PBUF_POOL_BUFSIZE; //1536;
MCF_FEC_ERDSR = (uint32_t)&rx_bd;
MCF_FEC_ETDSR = (uint32_t)&tx_bd;
MCF_FEC_RCR = (MAX_FRAME_LEN << 16) | MCF_FEC_RCR_MII_MODE;
MCF_FEC_FRSR = 0x48<<2; /* avoid address clashing of receive and transmit data in FEC fifo */
MCF_FEC_TCR = MCF_FEC_TCR_FDEN | MCF_FEC_TCR_HBC;
MCF_FEC_MIBC = MCF_FEC_MIBC_MIB_DISABLE;
/* TODO: clear MIB RAM??? */
MCF_FEC_MIBC =~MCF_FEC_MIBC_MIB_DISABLE; /* enable MIBC */
MCF_FEC_EIMR = 0;
rtems_interrupt_catch(rx_frame_handler,91,&old_isr_handler); /* register ISR for RX_INTF interrupt*/
MCF_INTC0_ICR27=0x10; /* set interrupt level */
MCF_FEC_EIR= 0xFFFFFFFF; /* clear all pending interrupts */
MCF_FEC_EIMR |= MCF_FEC_EIR_RXF; /* enable RX_INTF interrupt */
MCF_INTC0_IMRL &= ~MCF_INTC_IMRL_MASK27; /* enable FEC RX_INTF interrupt */
/* enable FEC */
MCF_FEC_ECR |= MCF_FEC_ECR_ETHER_EN;
/* Start reception, if it's not started already */
MCF_FEC_RDAR = 0;
return ERR_OK;
}
/*
* Install_clock
*
* Install a clock tick handler and reprograms the chip. This
* is used to initially establish the clock tick.
*
* SIDE EFFECTS:
* Establish clock interrupt handler, configure Timer 0 hardware
*/
static void Install_clock(rtems_isr_entry clock_isr)
{
int cpudiv = 1; /* CPU frequency divider */
int tidiv = 1; /* Timer input frequency divider */
uint32_t timer_divider; /* Calculated Timer Divider value */
uint8_t temp8;
uint16_t temp16;
/*
* Initialize the clock tick device driver variables
*/
Clock_driver_ticks = 0;
/* Get CPU frequency divider from clock unit */
switch (read16(SH7750_FRQCR) & SH7750_FRQCR_IFC) {
case SH7750_FRQCR_IFCDIV1:
cpudiv = 1;
break;
case SH7750_FRQCR_IFCDIV2:
cpudiv = 2;
break;
case SH7750_FRQCR_IFCDIV3:
cpudiv = 3;
break;
case SH7750_FRQCR_IFCDIV4:
cpudiv = 4;
break;
case SH7750_FRQCR_IFCDIV6:
cpudiv = 6;
break;
case SH7750_FRQCR_IFCDIV8:
cpudiv = 8;
break;
default:
rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED);
}
/* Get peripheral module frequency divider from clock unit */
switch (read16(SH7750_FRQCR) & SH7750_FRQCR_PFC) {
case SH7750_FRQCR_PFCDIV2:
tidiv = 2 * CLOCK_PRESCALER;
break;
case SH7750_FRQCR_PFCDIV3:
tidiv = 3 * CLOCK_PRESCALER;
break;
case SH7750_FRQCR_PFCDIV4:
tidiv = 4 * CLOCK_PRESCALER;
break;
case SH7750_FRQCR_PFCDIV6:
tidiv = 6 * CLOCK_PRESCALER;
break;
case SH7750_FRQCR_PFCDIV8:
tidiv = 8 * CLOCK_PRESCALER;
break;
default:
rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED);
}
timer_divider =
(bsp_clicks_per_second * cpudiv / (tidiv*1000000)) *
rtems_configuration_get_microseconds_per_tick();
/*
* Hardware specific initialization
*/
/* Stop the Timer 0 */
temp8 = read8(SH7750_TSTR);
temp8 &= ~SH7750_TSTR_STR0;
write8(temp8, SH7750_TSTR);
/* Establish interrupt handler */
rtems_interrupt_catch( Clock_isr, CLOCK_VECTOR, &Old_ticker );
/* Reset counter */
write32(timer_divider, SH7750_TCNT0);
/* Load divider */
write32(timer_divider, SH7750_TCOR0);
write16(
SH7750_TCR_UNIE | /* Enable Underflow Interrupt */
SH7750_TCR_CKEG_RAISE | /* Count on rising edge */
TCR0_TPSC, /* Timer prescaler ratio */
SH7750_TCR0);
/* Set clock interrupt priority */
temp16 = read16(SH7750_IPRA);
temp16 = (temp16 & ~SH7750_IPRA_TMU0) | (CLOCKPRIO << SH7750_IPRA_TMU0_S);
write16(temp16, SH7750_IPRA);
/* Start the Timer 0 */
temp8 = read8(SH7750_TSTR);
temp8 |= SH7750_TSTR_STR0;
write8(temp8, SH7750_TSTR);
/*
* Schedule the clock cleanup routine to execute if the application exits.
*/
atexit( Clock_exit );
}
rtems_task Task_1(
rtems_task_argument argument
)
{
rtems_name name RTEMS_GCC_NOWARN_UNUSED;
uint32_t index RTEMS_GCC_NOWARN_UNUSED;
rtems_id id RTEMS_GCC_NOWARN_UNUSED;
rtems_task_priority in_priority RTEMS_GCC_NOWARN_UNUSED;
rtems_task_priority out_priority RTEMS_GCC_NOWARN_UNUSED;
rtems_mode in_mode RTEMS_GCC_NOWARN_UNUSED;
rtems_mode mask RTEMS_GCC_NOWARN_UNUSED;
rtems_mode out_mode RTEMS_GCC_NOWARN_UNUSED;
rtems_time_of_day time RTEMS_GCC_NOWARN_UNUSED;
rtems_interval timeout RTEMS_GCC_NOWARN_UNUSED;
rtems_signal_set signals RTEMS_GCC_NOWARN_UNUSED;
void *address_1 RTEMS_GCC_NOWARN_UNUSED;
rtems_event_set events RTEMS_GCC_NOWARN_UNUSED;
long buffer[ 4 ] RTEMS_GCC_NOWARN_UNUSED;
uint32_t count RTEMS_GCC_NOWARN_UNUSED;
rtems_device_major_number major RTEMS_GCC_NOWARN_UNUSED;
rtems_device_minor_number minor RTEMS_GCC_NOWARN_UNUSED;
uint32_t io_result RTEMS_GCC_NOWARN_UNUSED;
uint32_t error RTEMS_GCC_NOWARN_UNUSED;
rtems_clock_get_options options RTEMS_GCC_NOWARN_UNUSED;
name = rtems_build_name( 'N', 'A', 'M', 'E' );
in_priority = 250;
in_mode = RTEMS_NO_PREEMPT;
mask = RTEMS_PREEMPT_MASK;
timeout = 100;
signals = RTEMS_SIGNAL_1 | RTEMS_SIGNAL_3;
major = 10;
minor = 0;
error = 100;
options = 0;
/* rtems_shutdown_executive */
benchmark_timer_initialize();
for ( index=1 ; index <= OPERATION_COUNT ; index++ )
(void) rtems_shutdown_executive( error );
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_shutdown_executive",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_task_create */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_task_create(
name,
in_priority,
RTEMS_MINIMUM_STACK_SIZE,
RTEMS_DEFAULT_MODES,
RTEMS_DEFAULT_ATTRIBUTES,
&id
);
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_task_create",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_task_ident */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_task_ident( name, RTEMS_SEARCH_ALL_NODES, id );
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_task_ident",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_task_start */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_task_start( id, Task_1, 0 );
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_task_start",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_task_restart */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_task_restart( id, 0 );
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_task_restart",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_task_delete */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_task_delete( id );
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_task_delete",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_task_suspend */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_task_suspend( id );
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_task_suspend",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_task_resume */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_task_resume( id );
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_task_resume",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_task_set_priority */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_task_set_priority( id, in_priority, &out_priority );
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_task_set_priority",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_task_mode */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_task_mode( in_mode, mask, &out_mode );
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_task_mode",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_task_wake_when */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_task_wake_when( time );
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_task_wake_when",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_task_wake_after */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_task_wake_after( timeout );
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_task_wake_after",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_interrupt_catch */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_interrupt_catch( Isr_handler, 5, address_1 );
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_interrupt_catch",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_clock_get */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_clock_get( options, time );
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_clock_get",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_clock_set */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_clock_set( time );
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_clock_set",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_clock_tick */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_clock_tick();
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_clock_tick",
end_time,
OPERATION_COUNT,
overhead,
0
);
rtems_test_pause();
/* rtems_timer_create */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_timer_create( name, &id );
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_timer_create",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_timer_delete */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_timer_delete( id );
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_timer_delete",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_timer_ident */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_timer_ident( name, id );
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_timer_ident",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_timer_fire_after */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_timer_fire_after(
id,
timeout,
Timer_handler,
NULL
);
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_timer_fire_after",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_timer_fire_when */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_timer_fire_when(
id,
time,
Timer_handler,
NULL
);
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_timer_fire_when",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_timer_reset */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_timer_reset( id );
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_timer_reset",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_timer_cancel */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_timer_cancel( id );
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_timer_cancel",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_semaphore_create */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_semaphore_create(
name,
128,
RTEMS_DEFAULT_ATTRIBUTES,
RTEMS_NO_PRIORITY,
&id
);
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_semaphore_create",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_semaphore_delete */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_semaphore_delete( id );
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_semaphore_delete",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_semaphore_ident */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_semaphore_ident( name, RTEMS_SEARCH_ALL_NODES, id );
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_semaphore_ident",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_semaphore_obtain */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_semaphore_obtain( id, RTEMS_DEFAULT_OPTIONS, timeout );
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_semaphore_obtain",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_semaphore_release */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_semaphore_release( id );
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_semaphore_release",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_message_queue_create */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_message_queue_create(
name,
128,
RTEMS_DEFAULT_ATTRIBUTES,
&id
);
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_message_queue_create",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_message_queue_ident */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_message_queue_ident(
name,
RTEMS_SEARCH_ALL_NODES,
id
);
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_message_queue_ident",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_message_queue_delete */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_message_queue_delete( id );
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_message_queue_delete",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_message_queue_send */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_message_queue_send( id, (long (*)[4])buffer );
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_message_queue_send",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_message_queue_urgent */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_message_queue_urgent( id, (long (*)[4])buffer );
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_message_queue_urgent",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_message_queue_broadcast */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_message_queue_broadcast(
id,
(long (*)[4])buffer,
&count
);
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_message_queue_broadcast",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_message_queue_receive */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_message_queue_receive(
id,
(long (*)[4])buffer,
RTEMS_DEFAULT_OPTIONS,
timeout
);
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_message_queue_receive",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_message_queue_flush */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_message_queue_flush( id, &count );
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_message_queue_flush",
end_time,
OPERATION_COUNT,
overhead,
0
);
rtems_test_pause();
/* rtems_event_send */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_event_send( id, events );
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_event_send",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_event_receive */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_event_receive(
RTEMS_EVENT_16,
RTEMS_DEFAULT_OPTIONS,
timeout,
&events
);
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_event_receive",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_signal_catch */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_signal_catch( Asr_handler, RTEMS_DEFAULT_MODES );
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_signal_catch",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_signal_send */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_signal_send( id, signals );
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_signal_send",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_partition_create */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_partition_create(
name,
Memory_area,
2048,
128,
RTEMS_DEFAULT_ATTRIBUTES,
&id
);
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_partition_create",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_partition_ident */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_partition_ident( name, RTEMS_SEARCH_ALL_NODES, id );
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_partition_ident",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_partition_delete */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_partition_delete( id );
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_partition_delete",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_partition_get_buffer */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_partition_get_buffer( id, address_1 );
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_partition_get_buffer",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_partition_return_buffer */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_partition_return_buffer( id, address_1 );
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_partition_return_buffer",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_region_create */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_region_create(
name,
Memory_area,
2048,
128,
RTEMS_DEFAULT_ATTRIBUTES,
&id
);
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_region_create",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_region_ident */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_region_ident( name, id );
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_region_ident",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_region_delete */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_region_delete( id );
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_region_delete",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_region_get_segment */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_region_get_segment(
id,
243,
RTEMS_DEFAULT_OPTIONS,
timeout,
&address_1
);
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_region_get_segment",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_region_return_segment */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_region_return_segment( id, address_1 );
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_region_return_segment",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_port_create */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_port_create(
name,
Internal_port_area,
External_port_area,
0xff,
&id
);
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_port_create",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_port_ident */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_port_ident( name, id );
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_port_ident",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_port_delete */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_port_delete( id );
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_port_delete",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_port_external_to_internal */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_port_external_to_internal(
id,
&External_port_area[ 7 ],
address_1
);
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_port_external_to_internal",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_port_internal_to_external */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_port_internal_to_external(
id,
&Internal_port_area[ 7 ],
address_1
);
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_port_internal_to_external",
end_time,
OPERATION_COUNT,
overhead,
0
);
rtems_test_pause();
/* rtems_io_initialize */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_io_initialize(
major,
minor,
address_1,
&io_result
);
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_io_initialize",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_io_open */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_io_open(
major,
minor,
address_1,
&io_result
);
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_io_open",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_io_close */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_io_close(
major,
minor,
address_1,
&io_result
);
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_io_close",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_io_read */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_io_read(
major,
minor,
address_1,
&io_result
);
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_io_read",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_io_write */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_io_write(
major,
minor,
address_1,
&io_result
);
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_io_write",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_io_control */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_io_control(
major,
minor,
address_1,
&io_result
);
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_io_control",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_fatal_error_occurred */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_fatal_error_occurred( error );
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_fatal_error_occurred",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_rate_monotonic_create */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_rate_monotonic_create( name, &id );
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_rate_monotonic_create",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_rate_monotonic_ident */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_rate_monotonic_ident( name, id );
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_rate_monotonic_ident",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_rate_monotonic_delete */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_rate_monotonic_delete( id );
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_rate_monotonic_delete",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_rate_monotonic_cancel */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_rate_monotonic_cancel( id );
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_rate_monotonic_cancel",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_rate_monotonic_period */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_rate_monotonic_period( id, timeout );
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_rate_monotonic_period",
end_time,
OPERATION_COUNT,
overhead,
0
);
/* rtems_multiprocessing_announce */
benchmark_timer_initialize();
for ( index = 1 ; index <= OPERATION_COUNT ; index ++ )
(void) rtems_multiprocessing_announce();
end_time = benchmark_timer_read();
put_time(
"overhead: rtems_multiprocessing_announce",
end_time,
OPERATION_COUNT,
overhead,
0
);
TEST_END();
rtems_test_exit( 0 );
}
/******************************************************
Name: Fifo_Full_benchmark_timer_initialize
Input parameters: -
Output parameters: -
Description: initialize Timer 1 for FIFO full mode
*****************************************************/
void Fifo_Full_benchmark_timer_initialize (void)
{
float max_baud_rate;
int prescaler_output_tap = -1;
int nb_of_clock_ticks = 0;
/*
* USE TIMER 1 for UART FIFO FULL mode
*/
if ( Fifo_Full_on_A || Fifo_Full_on_B )
{
/* Disable the timer */
TCR1 &= ~m340_SWR;
/* Reset the interrupts */
TSR1 &= ~(m340_TO | m340_TG | m340_TC);
/* Init the stop bit for normal operation, ignore FREEZE, user privileges,
set interrupt arbitration */
TMCR1 = TIMER1_INTERRUPT_ARBITRATION;
/* interrupt priority level and interrupt vector */
TIR1 = TIMER1_VECTOR | (TIMER1_IRQ_LEVEL << 8);
/* compute prescaler */
if ( Fifo_Full_on_A && Fifo_Full_on_B)
max_baud_rate = max(m340_uart_config[UART_CHANNEL_A].rx_baudrate, m340_uart_config[UART_CHANNEL_B].rx_baudrate);
else if ( Fifo_Full_on_A )
max_baud_rate = m340_uart_config[UART_CHANNEL_A].rx_baudrate;
else max_baud_rate = m340_uart_config[UART_CHANNEL_B].rx_baudrate;
/* find out config */
nb_of_clock_ticks = (10/max_baud_rate)*(CLOCK_SPEED*1000000)*1.2;
if (nb_of_clock_ticks < 0xFFFF) {
preload = nb_of_clock_ticks;
prescaler_output_tap = -1;
} else if (nb_of_clock_ticks/2 < 0xFFFF) {
preload = nb_of_clock_ticks/2;
prescaler_output_tap = m340_Divide_by_2;
} else if (nb_of_clock_ticks/4 < 0xFFFF) {
preload = nb_of_clock_ticks/4;
prescaler_output_tap = m340_Divide_by_4;
} else if (nb_of_clock_ticks/8 < 0xFFFF) {
preload = nb_of_clock_ticks/8;
prescaler_output_tap = m340_Divide_by_16;
} else if (nb_of_clock_ticks/16 < 0xFFFF) {
preload = nb_of_clock_ticks/16;
prescaler_output_tap = m340_Divide_by_16;
} else if (nb_of_clock_ticks/32 < 0xFFFF) {
preload = nb_of_clock_ticks/32;
prescaler_output_tap = m340_Divide_by_32;
} else if (nb_of_clock_ticks/64 < 0xFFFF) {
preload = nb_of_clock_ticks/64;
prescaler_output_tap = m340_Divide_by_64;
} else if (nb_of_clock_ticks/128 < 0xFFFF) {
preload = nb_of_clock_ticks/128;
prescaler_output_tap = m340_Divide_by_128;
} else if (nb_of_clock_ticks/256 < 0xFFFF) {
preload = nb_of_clock_ticks/256;
prescaler_output_tap = m340_Divide_by_256;
}
/* Input Capture/Output Compare (ICOC) */
TCR1 = m340_SWR | m340_TO_Enabled | m340_ICOC;
if (prescaler_output_tap!=-1) TCR1 |= prescaler_output_tap | m340_PSE;
/* install interrupt vector */
{
rtems_isr_entry old_handler;
rtems_status_code sc;
sc = rtems_interrupt_catch (InterruptHandler,
TIMER1_VECTOR,
&old_handler);
/* uncomment this if you want to pass control to your own ISR handler
it may be usefull to do so to check for performances with an oscilloscope */
/*
{
proc_ptr ignored;
_CPU_ISR_install_raw_handler( TIMER1_VECTOR, _Debug_ISR_Handler_Console, &ignored );
}
*/
}
} /* fifo full mode on a uart */
/* install routines */
Restart_Check_A_Timer = Fifo_Full_on_A ? __Restart_Check_Timer : __do_nothing;
Restart_Fifo_Full_A_Timer = Fifo_Full_on_A ? __Restart_Fifo_Full_Timer : __do_nothing;
Restart_Check_B_Timer = Fifo_Full_on_B ? __Restart_Check_Timer : __do_nothing;
Restart_Fifo_Full_B_Timer = Fifo_Full_on_B ? __Restart_Fifo_Full_Timer : __do_nothing;
/* start checking timer */
Restart_Check_A_Timer();
Restart_Check_B_Timer();
}
void Screen9()
{
void *converted;
rtems_status_code status;
#if ((CPU_SIMPLE_VECTORED_INTERRUPTS == FALSE) || \
defined(_C3x) || defined(_C4x))
puts(
"TA1 - rtems_interrupt_catch - "
"bad handler RTEMS_INVALID_ADDRESS -- SKIPPED"
);
puts(
"TA1 - rtems_interrupt_catch - "
"old isr RTEMS_INVALID_ADDRESS - SKIPPED" );
#else
rtems_isr_entry old_service_routine;
status = rtems_interrupt_catch(
Service_routine,
ISR_INTERRUPT_MAXIMUM_VECTOR_NUMBER + 10,
&old_service_routine
);
fatal_directive_status(
status,
RTEMS_INVALID_NUMBER,
"rtems_interrupt_catch with invalid vector"
);
puts( "TA1 - rtems_interrupt_catch - RTEMS_INVALID_NUMBER" );
status = rtems_interrupt_catch( NULL, 3, &old_service_routine );
fatal_directive_status(
status,
RTEMS_INVALID_ADDRESS,
"rtems_interrupt_catch with invalid handler"
);
puts( "TA1 - rtems_interrupt_catch - bad handler RTEMS_INVALID_ADDRESS" );
status = rtems_interrupt_catch( Service_routine, 3, NULL );
fatal_directive_status(
status,
RTEMS_INVALID_ADDRESS,
"rtems_interrupt_catch with invalid old isr pointer"
);
puts( "TA1 - rtems_interrupt_catch - old isr RTEMS_INVALID_ADDRESS" );
#endif
/* send invalid id */
status = rtems_signal_send( 100, RTEMS_SIGNAL_1 );
fatal_directive_status(
status,
RTEMS_INVALID_ID,
"rtems_signal_send with illegal id"
);
puts( "TA1 - rtems_signal_send - RTEMS_INVALID_ID" );
/* no signal in set */
status = rtems_signal_send( RTEMS_SELF, 0 );
fatal_directive_status(
status,
RTEMS_INVALID_NUMBER,
"rtems_signal_send with no signals"
);
puts( "TA1 - rtems_signal_send - RTEMS_INVALID_NUMBER" );
/* no signal handler */
status = rtems_signal_send( RTEMS_SELF, RTEMS_SIGNAL_16 );
fatal_directive_status(
status,
RTEMS_NOT_DEFINED,
"rtems_signal_send with no handler"
);
puts( "TA1 - rtems_signal_send - RTEMS_NOT_DEFINED" );
status = rtems_port_create(
0,
Internal_port_area,
External_port_area,
sizeof( Internal_port_area ),
&Junk_id
);
fatal_directive_status(
status,
RTEMS_INVALID_NAME,
"rtems_port_create with illegal name"
);
puts( "TA1 - rtems_port_create - RTEMS_INVALID_NAME" );
#if defined(_C3x) || defined(_C4x)
puts( "TA1 - rtems_port_create - RTEMS_INVALID_ADDRESS - SKIPPED" );
#else
status = rtems_port_create(
Port_name[ 1 ],
&((char *)Internal_port_area)[ 1 ],
External_port_area,
sizeof( Internal_port_area ),
&Junk_id
);
fatal_directive_status(
status,
RTEMS_INVALID_ADDRESS,
"rtems_port_create with illegal address"
);
puts( "TA1 - rtems_port_create - bad range - RTEMS_INVALID_ADDRESS" );
#endif
status = rtems_port_create(
Port_name[ 1 ],
Internal_port_area,
External_port_area,
sizeof( Internal_port_area ),
NULL
);
fatal_directive_status(
status,
RTEMS_INVALID_ADDRESS,
"rtems_port_create null Id"
);
puts( "TA1 - rtems_port_create - null id - RTEMS_INVALID_ADDRESS" );
status = rtems_port_create(
Port_name[ 1 ],
Internal_port_area,
External_port_area,
sizeof( Internal_port_area ),
&Junk_id
);
fatal_directive_status(
status,
RTEMS_TOO_MANY,
"rtems_port_create of too many"
);
puts( "TA1 - rtems_port_create - RTEMS_TOO_MANY" );
status = rtems_port_delete( 0 );
fatal_directive_status(
status,
RTEMS_INVALID_ID,
"rtems_port_delete with illegal id"
);
puts( "TA1 - rtems_port_delete - RTEMS_INVALID_ID" );
status = rtems_port_ident( 0, &Junk_id );
fatal_directive_status(
status,
RTEMS_INVALID_NAME,
"rtems_port_ident with illegal name"
);
puts( "TA1 - rtems_port_ident - RTEMS_INVALID_NAME" );
status = rtems_port_external_to_internal(
100,
Internal_port_area,
&converted
);
fatal_directive_status(
status,
RTEMS_INVALID_ID,
"rtems_port_external_to_internal with illegal id"
);
status = rtems_port_external_to_internal(
100,
Internal_port_area,
NULL
);
fatal_directive_status(
status,
RTEMS_INVALID_ADDRESS,
"rtems_port_external_to_internal with NULL param"
);
puts( "TA1 - rtems_port_external_to_internal - RTEMS_INVALID_ADDRESS" );
status = rtems_port_internal_to_external(
100,
Internal_port_area,
&converted
);
fatal_directive_status(
status,
RTEMS_INVALID_ID,
"rtems_port_internal_to_external with illegal id"
);
puts( "TA1 - rtems_port_internal_to_external - RTEMS_INVALID_ID" );
status = rtems_port_internal_to_external(
100,
Internal_port_area,
NULL
);
fatal_directive_status(
status,
RTEMS_INVALID_ADDRESS,
"rtems_port_internal_to_external with NULL param"
);
puts( "TA1 - rtems_port_external_to_internal - RTEMS_INVALID_ADDRESS" );
}
static void
mcf5282_fec_initialize_hardware(struct mcf5282_enet_struct *sc)
{
int i;
const unsigned char *hwaddr;
rtems_status_code status;
rtems_isr_entry old_handler;
uint32_t clock_speed = bsp_get_CPU_clock_speed();
/*
* Issue reset to FEC
*/
MCF5282_FEC_ECR = MCF5282_FEC_ECR_RESET;
rtems_task_wake_after(2);
MCF5282_FEC_ECR = 0;
/*
* Configuration of I/O ports is done outside of this function
*/
#if 0
imm->gpio.pbcnt |= MCF5282_GPIO_PBCNT_SET_FEC; /* Set up port b FEC pins */
#endif
/*
* Set our physical address
*/
hwaddr = sc->arpcom.ac_enaddr;
MCF5282_FEC_PALR = (hwaddr[0] << 24) | (hwaddr[1] << 16) |
(hwaddr[2] << 8) | (hwaddr[3] << 0);
MCF5282_FEC_PAUR = (hwaddr[4] << 24) | (hwaddr[5] << 16);
/*
* Clear the hash table
*/
MCF5282_FEC_GAUR = 0;
MCF5282_FEC_GALR = 0;
/*
* Set up receive buffer size
*/
MCF5282_FEC_EMRBR = 1520; /* Standard Ethernet */
/*
* Allocate mbuf pointers
*/
sc->rxMbuf = malloc(sc->rxBdCount * sizeof *sc->rxMbuf, M_MBUF, M_NOWAIT);
sc->txMbuf = malloc(sc->txBdCount * sizeof *sc->txMbuf, M_MBUF, M_NOWAIT);
if (!sc->rxMbuf || !sc->txMbuf)
rtems_panic("No memory for mbuf pointers");
/*
* Set receiver and transmitter buffer descriptor bases
*/
sc->rxBdBase = mcf5282_bd_allocate(sc->rxBdCount);
sc->txBdBase = mcf5282_bd_allocate(sc->txBdCount);
MCF5282_FEC_ERDSR = (int)sc->rxBdBase;
MCF5282_FEC_ETDSR = (int)sc->txBdBase;
/*
* Set up Receive Control Register:
* Not promiscuous
* MII mode
* Full duplex
* No loopback
*/
MCF5282_FEC_RCR = MCF5282_FEC_RCR_MAX_FL(MAX_MTU_SIZE) |
MCF5282_FEC_RCR_MII_MODE;
/*
* Set up Transmit Control Register:
* Full or half duplex
* No heartbeat
*/
if (sc->link == link_10Half)
MCF5282_FEC_TCR = 0;
else
MCF5282_FEC_TCR = MCF5282_FEC_TCR_FDEN;
/*
* Initialize statistic counters
*/
MCF5282_FEC_MIBC = MCF5282_FEC_MIBC_MIB_DISABLE;
{
vuint32 *vuip = &MCF5282_FEC_RMON_T_DROP;
while (vuip <= &MCF5282_FEC_IEEE_R_OCTETS_OK)
*vuip++ = 0;
}
MCF5282_FEC_MIBC = 0;
/*
* Set MII speed to <= 2.5 MHz
*/
i = (clock_speed + 5000000 - 1) / 5000000;
MCF5282_FEC_MSCR = MCF5282_FEC_MSCR_MII_SPEED(i);
/*
* Set PHYS
* LED1 receive status, LED2 link status, LEDs stretched
* Advertise 100 Mb/s, full-duplex, IEEE-802.3
* Turn off auto-negotiate
* Clear status
*/
setMII(1, 20, 0x24F2);
setMII(1, 4, 0x0181);
setMII(1, 0, 0x0);
rtems_task_wake_after(2);
sc->mii_sr2 = getMII(1, 17);
switch (sc->link) {
case link_auto:
/*
* Enable speed-change, duplex-change and link-status-change interrupts
* Enable auto-negotiate (start at 100/FULL)
*/
setMII(1, 18, 0x0072);
setMII(1, 0, 0x3100);
break;
case link_10Half:
/*
* Force 10/HALF
*/
setMII(1, 0, 0x0);
break;
case link_100Full:
/*
* Force 100/FULL
*/
setMII(1, 0, 0x2100);
break;
}
sc->mii_cr = getMII(1, 0);
/*
* Set up receive buffer descriptors
*/
for (i = 0 ; i < sc->rxBdCount ; i++)
(sc->rxBdBase + i)->status = 0;
/*
* Set up transmit buffer descriptors
*/
for (i = 0 ; i < sc->txBdCount ; i++) {
sc->txBdBase[i].status = 0;
sc->txMbuf[i] = NULL;
}
sc->txBdHead = sc->txBdTail = 0;
sc->txBdActiveCount = 0;
/*
* Set up interrupts
*/
status = rtems_interrupt_catch( mcf5282_fec_tx_interrupt_handler, FEC_INTC0_TX_VECTOR, &old_handler );
if (status != RTEMS_SUCCESSFUL)
rtems_panic ("Can't attach MCF5282 FEC TX interrupt handler: %s\n",
rtems_status_text(status));
bsp_allocate_interrupt(FEC_IRQ_LEVEL, FEC_IRQ_TX_PRIORITY);
MCF5282_INTC0_ICR23 = MCF5282_INTC_ICR_IL(FEC_IRQ_LEVEL) |
MCF5282_INTC_ICR_IP(FEC_IRQ_TX_PRIORITY);
MCF5282_INTC0_IMRL &= ~(MCF5282_INTC_IMRL_INT23 | MCF5282_INTC_IMRL_MASKALL);
status = rtems_interrupt_catch(mcf5282_fec_rx_interrupt_handler, FEC_INTC0_RX_VECTOR, &old_handler);
if (status != RTEMS_SUCCESSFUL)
rtems_panic ("Can't attach MCF5282 FEC RX interrupt handler: %s\n",
rtems_status_text(status));
bsp_allocate_interrupt(FEC_IRQ_LEVEL, FEC_IRQ_RX_PRIORITY);
MCF5282_INTC0_ICR27 = MCF5282_INTC_ICR_IL(FEC_IRQ_LEVEL) |
MCF5282_INTC_ICR_IP(FEC_IRQ_RX_PRIORITY);
MCF5282_INTC0_IMRL &= ~(MCF5282_INTC_IMRL_INT27 | MCF5282_INTC_IMRL_MASKALL);
status = rtems_interrupt_catch(mcf5282_mii_interrupt_handler, MII_VECTOR, &old_handler);
if (status != RTEMS_SUCCESSFUL)
rtems_panic ("Can't attach MCF5282 FEC MII interrupt handler: %s\n",
rtems_status_text(status));
MCF5282_EPORT_EPPAR &= ~MII_EPPAR;
MCF5282_EPORT_EPDDR &= ~MII_EPDDR;
MCF5282_EPORT_EPIER |= MII_EPIER;
MCF5282_INTC0_IMRL &= ~(MCF5282_INTC_IMRL_INT7 | MCF5282_INTC_IMRL_MASKALL);
}
/******************************************************
Name: dbugInitialise
Input parameters: -
Output parameters: -
Description: Init the UART
*****************************************************/
static void
dbugInitialise (void)
{
t_baud_speed_table uart_config; /* configuration of UARTS */
/*
* Reset Receiver
*/
DUCRA = m340_Reset_Receiver;
DUCRB = m340_Reset_Receiver;
/*
* Reset Transmitter
*/
DUCRA = m340_Reset_Transmitter;
DUCRB = m340_Reset_Transmitter;
/*
* Enable serial module for normal operation, ignore FREEZE, select the crystal clock,
* supervisor/user serial registers unrestricted
* interrupt arbitration at priority CONSOLE_INTERRUPT_ARBITRATION
* WARNING : 8 bits access only on this UART!
*/
DUMCRH = 0x00;
DUMCRL = CONSOLE_INTERRUPT_ARBITRATION;
/*
* Interrupt level register
*/
DUILR = CONSOLE_IRQ_LEVEL;
/* sets the IVR */
DUIVR = CONSOLE_VECTOR;
/* search for a correct m340 uart configuration */
uart_config = Find_Right_m340_UART_Config(m340_uart_config[UART_CHANNEL_A].rx_baudrate,
m340_uart_config[UART_CHANNEL_A].tx_baudrate,
CHANNEL_ENABLED_A,
m340_uart_config[UART_CHANNEL_B].rx_baudrate,
m340_uart_config[UART_CHANNEL_B].tx_baudrate,
CHANNEL_ENABLED_B);
/*****************************************************************************
** CHANNEL A **
*****************************************************************************/
if (CHANNEL_ENABLED_A) {
if (USE_INTERRUPTS_A) {
rtems_isr_entry old_handler;
rtems_status_code sc;
sc = rtems_interrupt_catch (InterruptHandler,
CONSOLE_VECTOR,
&old_handler);
/* uncomment this if you want to pass control to your own ISR handler
it may be usefull to do so to check for performances with an oscilloscope */
/*
{
proc_ptr ignored;
_CPU_ISR_install_raw_handler( CONSOLE_VECTOR, _Debug_ISR_Handler_Console, &ignored );
}
*/
/*
* Interrupt Enable Register
* Enable Interrupts on Channel A Receiver Ready
*/
set_DUIER(m340_RxRDYA);
}
else {
/*
* Disable Interrupts on channel A
*/
unset_DUIER(m340_RxRDYA&m340_TxRDYA);
}
/*
* Change set of baud speeds
* disable input control
*/
/* no good uart configuration ? */
if (uart_config.nb<1) rtems_fatal_error_occurred (-1);
if (uart_config.baud_speed_table[UART_CHANNEL_A].set==1)
DUACR = m340_BRG_Set1;
else
DUACR = m340_BRG_Set2;
/*
* make OPCR an auxiliary function serving the communication channels
*/
DUOPCR = m340_OPCR_Aux;
/* poll the XTAL_RDY bit until it is cleared to ensure that an unstable crystal
input is not applied to the baud rate generator */
while (DUISR & m340_XTAL_RDY) continue;
/*
* Serial Channel Baud Speed
*/
DUCSRA = (uart_config.baud_speed_table[UART_CHANNEL_A].rcs << 4)
| (uart_config.baud_speed_table[UART_CHANNEL_A].tcs);
/*
* Serial Channel Configuration
*/
DUMR1A = m340_uart_config[UART_CHANNEL_A].parity_mode
| m340_uart_config[UART_CHANNEL_A].bits_per_char
| m340_RxRTS;
if (m340_uart_config[UART_CHANNEL_A].rx_mode==UART_FIFO_FULL) DUMR1A |= m340_R_F | m340_ERR;
/*
* Serial Channel Configuration 2
*/
DUMR2A |= m340_normal;
/*
* Enable Channel A: transmitter and receiver
*/
DUCRA = m340_Transmitter_Enable | m340_Receiver_Enable;
} /* channel A enabled */
/*****************************************************************************
** CHANNEL B **
*****************************************************************************/
if (CHANNEL_ENABLED_B) {
/* we mustn't set the console vector twice! */
if ((USE_INTERRUPTS_B && !(CHANNEL_ENABLED_A))
|| (USE_INTERRUPTS_B && CHANNEL_ENABLED_A && !USE_INTERRUPTS_A)) {
rtems_isr_entry old_handler;
rtems_status_code sc;
sc = rtems_interrupt_catch (InterruptHandler,
CONSOLE_VECTOR,
&old_handler);
/* uncomment this if you want to pass control to your own ISR handler
it may be usefull to do so to check for performances with an oscilloscope */
/*
{
proc_ptr ignored;
_CPU_ISR_install_raw_handler( CONSOLE_VECTOR, _Debug_ISR_Handler_Console, &ignored );
}
*/
/*
* Interrupt Enable Register
* Enable Interrupts on Channel A Receiver Ready
*/
set_DUIER(m340_RxRDYB);
}
else {
/*
* Disable Interrupts on channel B
*/
unset_DUIER(m340_RxRDYB&m340_TxRDYB);
}
/*
* Change set of baud speeds
* disable input control
*/
/* no good uart configuration ? */
if (uart_config.nb<2) rtems_fatal_error_occurred (-1);
/* don't set DUACR twice! */
if (!CHANNEL_ENABLED_A) {
if (uart_config.baud_speed_table[UART_CHANNEL_B].set==1)
DUACR = m340_BRG_Set1;
else
DUACR = m340_BRG_Set2;
}
/*
* make OPCR an auxiliary function serving the communication channels
*/
if (!CHANNEL_ENABLED_A) DUOPCR = m340_OPCR_Aux;
/* poll the XTAL_RDY bit until it is cleared to ensure that an unstable crystal
input is not applied to the baud rate generator */
while (DUISR & m340_XTAL_RDY) continue;
/*
* Serial Channel Baud Speed
*/
DUCSRB = (uart_config.baud_speed_table[UART_CHANNEL_B].rcs << 4)
| (uart_config.baud_speed_table[UART_CHANNEL_B].tcs);
/*
* Serial Channel Configuration
*/
DUMR1B = m340_uart_config[UART_CHANNEL_B].parity_mode
| m340_uart_config[UART_CHANNEL_B].bits_per_char
| m340_RxRTS;
if (m340_uart_config[UART_CHANNEL_B].rx_mode==UART_FIFO_FULL) DUMR1B |= m340_R_F | m340_ERR;
/*
* Serial Channel Configuration 2
*/
DUMR2B |= m340_normal;
/*
* Enable Channel A: transmitter and receiver
*/
DUCRB = m340_Transmitter_Enable | m340_Receiver_Enable;
} /* channel B enabled */
}
/*
* Initialize the ethernet hardware
*/
static void
m360Enet_initialize_hardware (struct scc_softc *sc)
{
int i;
unsigned char *hwaddr;
rtems_status_code status;
rtems_isr_entry old_handler;
/*
* Configure port A CLK1, CLK2, TXD1 and RXD1 pins
*/
m360.papar |= 0x303;
m360.padir &= ~0x303;
m360.paodr &= ~0x303;
/*
* Configure port C CTS1* and CD1* pins
*/
m360.pcpar &= ~0x30;
m360.pcdir &= ~0x30;
m360.pcso |= 0x30;
/*
* Connect CLK1 and CLK2 to SCC1
*/
m360.sicr &= ~0xFF;
m360.sicr |= (5 << 3) | 4;
/*
* Allocate mbuf pointers
*/
sc->rxMbuf = malloc (sc->rxBdCount * sizeof *sc->rxMbuf, M_MBUF, M_NOWAIT);
sc->txMbuf = malloc (sc->txBdCount * sizeof *sc->txMbuf, M_MBUF, M_NOWAIT);
if (!sc->rxMbuf || !sc->txMbuf)
rtems_panic ("No memory for mbuf pointers");
/*
* Set receiver and transmitter buffer descriptor bases
*/
sc->rxBdBase = M360AllocateBufferDescriptors(sc->rxBdCount);
sc->txBdBase = M360AllocateBufferDescriptors(sc->txBdCount);
m360.scc1p.rbase = (char *)sc->rxBdBase - (char *)&m360;
m360.scc1p.tbase = (char *)sc->txBdBase - (char *)&m360;
/*
* Send "Init parameters" command
*/
M360ExecuteRISC (M360_CR_OP_INIT_RX_TX | M360_CR_CHAN_SCC1);
/*
* Set receive and transmit function codes
*/
m360.scc1p.rfcr = M360_RFCR_MOT | M360_RFCR_DMA_SPACE;
m360.scc1p.tfcr = M360_TFCR_MOT | M360_TFCR_DMA_SPACE;
/*
* Set maximum receive buffer length
*/
m360.scc1p.mrblr = RBUF_SIZE;
/*
* Set CRC parameters
*/
m360.scc1p.un.ethernet.c_pres = 0xFFFFFFFF;
m360.scc1p.un.ethernet.c_mask = 0xDEBB20E3;
/*
* Clear diagnostic counters
*/
m360.scc1p.un.ethernet.crcec = 0;
m360.scc1p.un.ethernet.alec = 0;
m360.scc1p.un.ethernet.disfc = 0;
/*
* Set pad value
*/
m360.scc1p.un.ethernet.pads = 0x8888;
/*
* Set retry limit
*/
m360.scc1p.un.ethernet.ret_lim = 15;
/*
* Set maximum and minimum frame length
*/
m360.scc1p.un.ethernet.mflr = 1518;
m360.scc1p.un.ethernet.minflr = 64;
m360.scc1p.un.ethernet.maxd1 = RBUF_SIZE;
m360.scc1p.un.ethernet.maxd2 = RBUF_SIZE;
/*
* Clear group address hash table
*/
m360.scc1p.un.ethernet.gaddr1 = 0;
m360.scc1p.un.ethernet.gaddr2 = 0;
m360.scc1p.un.ethernet.gaddr3 = 0;
m360.scc1p.un.ethernet.gaddr4 = 0;
/*
* Set our physical address
*/
hwaddr = sc->arpcom.ac_enaddr;
m360.scc1p.un.ethernet.paddr_h = (hwaddr[5] << 8) | hwaddr[4];
m360.scc1p.un.ethernet.paddr_m = (hwaddr[3] << 8) | hwaddr[2];
m360.scc1p.un.ethernet.paddr_l = (hwaddr[1] << 8) | hwaddr[0];
/*
* Aggressive retry
*/
m360.scc1p.un.ethernet.p_per = 0;
/*
* Clear individual address hash table
*/
m360.scc1p.un.ethernet.iaddr1 = 0;
m360.scc1p.un.ethernet.iaddr2 = 0;
m360.scc1p.un.ethernet.iaddr3 = 0;
m360.scc1p.un.ethernet.iaddr4 = 0;
/*
* Set up receive buffer descriptors
*/
for (i = 0 ; i < sc->rxBdCount ; i++)
(sc->rxBdBase + i)->status = 0;
/*
* Set up transmit buffer descriptors
*/
for (i = 0 ; i < sc->txBdCount ; i++) {
(sc->txBdBase + i)->status = 0;
sc->txMbuf[i] = NULL;
}
sc->txBdHead = sc->txBdTail = 0;
sc->txBdActiveCount = 0;
/*
* Clear any outstanding events
*/
m360.scc1.scce = 0xFFFF;
/*
* Set up interrupts
*/
status = rtems_interrupt_catch (m360Enet_interrupt_handler,
(m360.cicr & 0xE0) | 0x1E,
&old_handler);
if (status != RTEMS_SUCCESSFUL)
rtems_panic ("Can't attach M360 SCC1 interrupt handler: %s\n",
rtems_status_text (status));
m360.scc1.sccm = 0; /* No interrupts unmasked till necessary */
m360.cimr |= (1UL << 30); /* Enable SCC1 interrupt */
/*
* Set up General SCC Mode Register
* Ethernet configuration
*/
m360.scc1.gsmr_h = 0x0;
m360.scc1.gsmr_l = 0x1088000c;
/*
* Set up data synchronization register
* Ethernet synchronization pattern
*/
m360.scc1.dsr = 0xd555;
/*
* Set up protocol-specific mode register
* Heartbeat check
* No force collision
* Discard short frames
* Individual address mode
* Ethernet CRC
* Not promisuous
* Ignore/accept broadcast packets as specified
* Normal backoff timer
* No loopback
* No input sample at end of frame
* 64-byte limit for late collision
* Wait 22 bits before looking for start of frame delimiter
* Disable full-duplex operation
*/
m360.scc1.psmr = 0x880A | (sc->acceptBroadcast ? 0 : 0x100);
/*
* Enable the TENA (RTS1*) pin
*/
#if (defined (M68360_ATLAS_HSB))
m360.pbpar |= 0x1000;
m360.pbdir |= 0x1000;
#else
m360.pcpar |= 0x1;
m360.pcdir &= ~0x1;
#endif
}
/*=========================================================================*\
| Function: |
\*-------------------------------------------------------------------------*/
static void m360_spi_install_irq_handler
(
/*-------------------------------------------------------------------------*\
| Purpose: |
| (un-)install the interrupt handler |
+---------------------------------------------------------------------------+
| Input Parameters: |
\*-------------------------------------------------------------------------*/
m360_spi_softc_t *softc_ptr, /* ptr to control structure */
int install /* TRUE: install, FALSE: remove */
)
/*-------------------------------------------------------------------------*\
| Return Value: |
| <none> |
\*=========================================================================*/
{
rtems_status_code rc = RTEMS_SUCCESSFUL;
/*
* (un-)install handler for SPI device
*/
if (install) {
/*
* create semaphore for IRQ synchronization
*/
rc = rtems_semaphore_create(rtems_build_name('s','p','i','s'),
0,
RTEMS_FIFO
| RTEMS_SIMPLE_BINARY_SEMAPHORE,
0,
&softc_ptr->irq_sema_id);
if (rc != RTEMS_SUCCESSFUL) {
rtems_panic("SPI: cannot create semaphore");
}
if (rc == RTEMS_SUCCESSFUL) {
rc = rtems_interrupt_catch (m360_spi_irq_handler,
(m360.cicr & 0xE0) | 0x05,
&softc_ptr->old_handler);
if (rc != RTEMS_SUCCESSFUL) {
rtems_panic("SPI: cannot install IRQ handler");
}
}
/*
* enable IRQ in CPIC
*/
if (rc == RTEMS_SUCCESSFUL) {
m360.cimr |= (1 << 5);
}
}
else {
rtems_isr_entry old_handler;
/*
* disable IRQ in CPIC
*/
if (rc == RTEMS_SUCCESSFUL) {
m360.cimr &= ~(1 << 5);
}
rc = rtems_interrupt_catch (softc_ptr->old_handler,
(m360.cicr & 0xE0) | 0x05,
&old_handler);
if (rc != RTEMS_SUCCESSFUL) {
rtems_panic("SPI: cannot uninstall IRQ handler");
}
/*
* delete sync semaphore
*/
if (softc_ptr->irq_sema_id != 0) {
rc = rtems_semaphore_delete(softc_ptr->irq_sema_id);
if (rc != RTEMS_SUCCESSFUL) {
rtems_panic("SPI: cannot delete semaphore");
}
}
}
}