Example #1
0
rtems_device_driver console_initialize(
    rtems_device_major_number  major,
    rtems_device_minor_number  minor,
    void                      *arg
)
{
    rtems_status_code status;
    int i;

    for (i = 0; i < NUM_DEVS; i++) {
        imx_uart_init(i);
    }

    rtems_termios_initialize();

    /* /dev/console and /dev/tty0 are the same */
    status = rtems_io_register_name("/dev/console", major, 0);
    if (status != RTEMS_SUCCESSFUL) {
        rtems_panic("%s:%d Error registering /dev/console :: %d\n",
                    __FUNCTION__, __LINE__, status);
    }

    status = rtems_io_register_name("/dev/tty0", major, 0);
    if (status != RTEMS_SUCCESSFUL) {
        rtems_panic("%s:%d Error registering /dev/tty0 :: %d\n",
                    __FUNCTION__, __LINE__, status);
    }

    status = rtems_io_register_name("/dev/tty1", major, 1);
    if (status != RTEMS_SUCCESSFUL) {
        rtems_panic("%s:%d Error registering /dev/tty1 :: %d\n",
                    __FUNCTION__, __LINE__, status);
    }
    return RTEMS_SUCCESSFUL;
}
Example #2
0
/*
 * Server Task
 */
static rtems_task serverTask(rtems_task_argument arg)
{
    int s, s1;
    socklen_t addrlen;
    struct sockaddr_in myAddr, farAddr;
    rtems_task_priority myPriority;

    printf("Create socket.\n");
    s = socket(AF_INET, SOCK_STREAM, 0);
    if (s < 0)
        rtems_panic("Can't create socket: %s\n", strerror(errno));
    memset(&myAddr, 0, sizeof myAddr);
    myAddr.sin_family = AF_INET;
    myAddr.sin_port = htons(1234);
    myAddr.sin_addr.s_addr = htonl(INADDR_ANY);
    printf("Bind socket.\n");
    if (bind(s, (struct sockaddr *)&myAddr, sizeof myAddr) < 0)
        rtems_panic("Can't bind socket: %s\n", strerror(errno));
    if (listen(s, 5) < 0)
        printf("Can't listen on socket: %s\n", strerror(errno));
    rtems_task_set_priority(RTEMS_SELF, RTEMS_CURRENT_PRIORITY, &myPriority);
    for(;;) {
        addrlen = sizeof farAddr;
        s1 = accept(s, (struct sockaddr *)&farAddr, &addrlen);
        if (s1 < 0)
            if (errno == ENXIO)
                rtems_task_delete(RTEMS_SELF);
            else
                rtems_panic("Can't accept connection: %s", strerror(errno));
        else
            printf("ACCEPTED:%lX\n", ntohl(farAddr.sin_addr.s_addr));
        spawnTask(workerTask, myPriority, s1);
    }
}
Example #3
0
static size_t remove_reserved_memory(
  const void *fdt,
  Heap_Area *areas,
  size_t area_count
)
{
  int node;

  node = fdt_path_offset_namelen(
    fdt,
    reserved_memory_path,
    (int) sizeof(reserved_memory_path) - 1
  );

  if (node >= 0) {
    node = fdt_first_subnode(fdt, node);

    while (node >= 0) {
      int len;
      const void *val;
      uintptr_t area_begin;
      uintptr_t area_end;
      uintptr_t hole_begin;
      uintptr_t hole_end;
      Heap_Area *area;

      val = fdt_getprop(fdt, node, "reg", &len);
      if (len == 8) {
        hole_begin = fdt32_to_cpu(((fdt32_t *) val)[0]);
        hole_end = hole_begin + fdt32_to_cpu(((fdt32_t *) val)[1]);
      } else {
        rtems_panic("unexpected reserved memory area");
      }

      area = find_area(areas, area_count, hole_begin);
      area_begin = (uintptr_t) area->begin;
      area_end = area_begin + (uintptr_t) area->size;
      area->size = hole_begin - area_begin;

      if (hole_end <= area_end) {
        if (area_count >= AREA_COUNT_MAX) {
          rtems_panic("too many reserved memory areas");
        }

        area = &areas[area_count];
        ++area_count;
        area->begin = (void *) hole_end;
        area->size = area_end - hole_end;
      }

      node = fdt_next_subnode(fdt, node);
    }
  }

  return area_count;
}
Example #4
0
/*
 * Set the UART's baud rate. The calculation is:
 *   (baud * 16) / ref_freq  = num/demom
 *
 *   ref_freq = perclk1 / RFDIV[2:0]
 *   BIR = num - 1
 *   BMR = demom - 1
 *
 * Setting 'num' to 16 yields this equation:
 *    demom = ref_freq / baud
 */
static void imx_uart_set_baud(int minor, int baud)
{
    unsigned int perclk1;
    unsigned int denom;
    unsigned int ref_freq = 0;
    uint32_t fcr;

    perclk1 = get_perclk1_freq();
    fcr = imx_uart_data[minor].regs->fcr;

    switch(fcr & MC9328MXL_UART_FCR_RFDIV_MASK) {
    case MC9328MXL_UART_FCR_RFDIV_1:  ref_freq = perclk1/1; break;
    case MC9328MXL_UART_FCR_RFDIV_2:  ref_freq = perclk1/2; break;
    case MC9328MXL_UART_FCR_RFDIV_3:  ref_freq = perclk1/3; break;
    case MC9328MXL_UART_FCR_RFDIV_4:  ref_freq = perclk1/4; break;
    case MC9328MXL_UART_FCR_RFDIV_5:  ref_freq = perclk1/5; break;
    case MC9328MXL_UART_FCR_RFDIV_6:  ref_freq = perclk1/6; break;
    case MC9328MXL_UART_FCR_RFDIV_7:  ref_freq = perclk1/7; break;
    default:
        rtems_panic("%s:%d Unknown RFDIV: 0x%x",
                    __FUNCTION__, __LINE__,
                    fcr & MC9328MXL_UART_FCR_RFDIV_MASK);
        break;
    }

    denom = ref_freq / baud;

    imx_uart_data[minor].regs->bir = 0xf;
    imx_uart_data[minor].regs->bmr = denom;
}
Example #5
0
/* interrupt handler */
static void at91rm9200_emac_isr (rtems_irq_hdl_param unused)
{
    unsigned long status32;

    /* get the ISR status and determine RX or TX */
    status32 = EMAC_REG(EMAC_ISR);

    if (status32 & EMAC_INT_ABT) {
        EMAC_REG(EMAC_IDR) = EMAC_INT_ABT; /* disable it */
        rtems_panic("AT91RM9200 Ethernet MAC has received an Abort.\n");
    }

    if (status32 & (EMAC_INT_RCOM |    /* Receive complete */
                    EMAC_INT_RBNA |    /* Receive buffer not available */
                    EMAC_INT_ROVR)) {  /* Receive overrun */

        /* disable the RX interrupts */
        EMAC_REG(EMAC_IDR) = (EMAC_INT_RCOM |  /* Receive complete */
                              EMAC_INT_RBNA |  /* Receive buf not available */
                              EMAC_INT_ROVR);  /* Receive overrun */

        rtems_event_send (softc.rxDaemonTid, START_RECEIVE_EVENT);
    }

    if (status32 & EMAC_INT_TCOM) {      /* Transmit buffer register empty */

        /* disable the TX interrupts */
        EMAC_REG(EMAC_IDR) = EMAC_INT_TCOM;

        rtems_event_send (softc.txDaemonTid, START_TRANSMIT_EVENT);
    }
}
Example #6
0
/*=========================================================================*\
| Function:                                                                 |
\*-------------------------------------------------------------------------*/
static void m8xx_spi_install_irq_handler
(
/*-------------------------------------------------------------------------*\
| Purpose:                                                                  |
|   install the interrupt handler                                           |
+---------------------------------------------------------------------------+
| Input Parameters:                                                         |
\*-------------------------------------------------------------------------*/
 m8xx_spi_softc_t *softc_ptr,           /* ptr to control structure        */
 int install                            /* TRUE: install, FALSE: remove    */
)
/*-------------------------------------------------------------------------*\
| Return Value:                                                             |
|    <none>                                                                 |
\*=========================================================================*/
{
  rtems_status_code rc = RTEMS_SUCCESSFUL;

  /*
   * install handler for SPI device
   */
  /*
   * create semaphore for IRQ synchronization
   */
  rc = rtems_semaphore_create(rtems_build_name('s','p','i','s'),
			      0,
			      RTEMS_FIFO
			      | RTEMS_SIMPLE_BINARY_SEMAPHORE,
			      0,
			      &softc_ptr->irq_sema_id);
  if (rc != RTEMS_SUCCESSFUL) {
    rtems_panic("SPI: cannot create semaphore");
  }
  if (rc == RTEMS_SUCCESSFUL) {
    rtems_irq_connect_data irq_conn_data = {
      BSP_CPM_IRQ_SPI,
      m8xx_spi_irq_handler,            /* rtems_irq_hdl           */
      (rtems_irq_hdl_param)softc_ptr,  /* (rtems_irq_hdl_param)   */
      mpc8xx_spi_irq_on,               /* (rtems_irq_enable)      */
      mpc8xx_spi_irq_off,              /* (rtems_irq_disable)     */
      mpc8xx_spi_irq_isOn              /* (rtems_irq_is_enabled)  */
    };
    if (!BSP_install_rtems_irq_handler (&irq_conn_data)) {
      rtems_panic("SPI: cannot install IRQ handler");
    }
  }
}
Example #7
0
/*
 * Delay for a while, then terminate
 */
static void
delayedPanic (const char *msg)
{
    extern rtems_interval rtemsTicksPerSecond;

    rtems_task_wake_after (rtemsTicksPerSecond);
    rtems_panic (msg);
}
Example #8
0
/*
 * Spawn a task
 */
static void spawnTask(rtems_task_entry entryPoint, rtems_task_priority priority, rtems_task_argument arg)
{
    rtems_status_code sc;
    rtems_id tid;

    sc = rtems_task_create(rtems_build_name('t','a','s','k'),
                           priority,
                           RTEMS_MINIMUM_STACK_SIZE+(8*1024),
                           RTEMS_PREEMPT|RTEMS_TIMESLICE|RTEMS_NO_ASR|RTEMS_INTERRUPT_LEVEL(0),
                           RTEMS_FLOATING_POINT|RTEMS_LOCAL,
                           &tid);
    if (sc != RTEMS_SUCCESSFUL)
        rtems_panic("Can't create task: %s", rtems_status_text(sc));
    sc = rtems_task_start(tid, entryPoint, arg);
    if (sc != RTEMS_SUCCESSFUL)
        rtems_panic("Can't start task: %s", rtems_status_text(sc));
}
Example #9
0
static int qemuppc_exception_handler(
  BSP_Exception_frame *frame,
  unsigned exception_number
)
{
  rtems_panic("Unexpected interrupt occured");
  return 0;
}
Example #10
0
/**
 * Checks WHO_AM_I register content of L34200D gyroscope.
 */
static void check_whoami(int minor)
{
  unsigned char reg;

  l3g4200d_read_registers(minor, L3G4200D_WHO_AM_I, &reg, 1);

  if (reg != L3G4200D_WHO_AM_I_VALUE)
    rtems_panic("Invalid L3G4200 WHO AM I value");
}
Example #11
0
static void
rtems_httpd_daemon(rtems_task_argument args)
{
/*
 *	Initialize the memory allocator. Allow use of malloc and start with a 
 *	10K heap.
 */
	bopen(NULL, (10 * 1024), B_USE_MALLOC);

/*
 *	Initialize the web server
 */
	if (initWebs() < 0) {
	  rtems_panic("Unable to initialize Web server !!\n");
	}

#ifdef WEBS_SSL_SUPPORT
	websSSLOpen();
#endif

/*
 *	Basic event loop. SocketReady returns true when a socket is ready for
 *	service. SocketSelect will block until an event occurs. SocketProcess
 *	will actually do the servicing.
 */
	while (!finished) {
	  if (socketReady(-1) || socketSelect(-1, 2000)) {
			socketProcess(-1);
	  }
	  /*websCgiCleanup();*/
	  emfSchedProcess();
	}

#ifdef WEBS_SSL_SUPPORT
	websSSLClose();
#endif

#ifdef USER_MANAGEMENT_SUPPORT
	umClose();
#endif

/*
 *	Close the socket module, report memory leaks and close the memory allocator
 */
	websCloseServer();
	websDefaultClose();
	socketClose();
	symSubClose();
#if B_STATS
	memLeaks();
#endif
	bclose();
        rtems_task_delete( RTEMS_SELF );
}
Example #12
0
rtems_task Init(
  rtems_task_argument argument
)
{
  TEST_BEGIN();

  rtems_panic(
    "Dummy panic\n"
  );

  rtems_test_assert(0);
}
Example #13
0
/*
 * Send a command to the CPM RISC processer
 */
void *
M360AllocateBufferDescriptors (M68360_t ptr, int count)
{
  unsigned int i;
  ISR_Level    level;
  void         *bdp  = NULL;
  unsigned int want  = count * sizeof(m360BufferDescriptor_t);
  int          have;

  /*
   * Running with interrupts disabled is usually considered bad
   * form, but this routine is probably being run as part of an
   * initialization sequence so the effect shouldn't be too severe.
   */
  _ISR_Disable (level);

  for (i = 0 ; i < M360_NUM_DPRAM_REAGONS ; i++) {

    /*
     * Verify that the region exists.
     * This test is necessary since some chips have
     * less dual-port RAM.
     */
    if (ptr->bdregions[i].used == 0) {
      volatile unsigned char *cp = ptr->bdregions[i].base;
      *cp = 0xAA;
      if (*cp != 0xAA) {
        ptr->bdregions[i].used = ptr->bdregions[i].size;
        continue;
      }
      *cp = 0x55;
      if (*cp != 0x55) {
        ptr->bdregions[i].used = ptr->bdregions[i].size;
        continue;
      }
      *cp = 0x0;
    }

    have = ptr->bdregions[i].size - ptr->bdregions[i].used;
    if (have >= want) {
      bdp = ptr->bdregions[i].base + ptr->bdregions[i].used;
      ptr->bdregions[i].used += want;
      break;
    }
  }
  _ISR_Enable (level);
  if (bdp == NULL){
    printk("rtems_panic can't allocate %d buffer descriptor(s).\n");
    rtems_panic ("Can't allocate %d buffer descriptor(s).\n", count);
  }
  return bdp;
}
Example #14
0
rtems_task Init(
  rtems_task_argument argument
)
{
  puts( "\n\n*** TEST Tests for error reporting routines - 03 ***" );

  rtems_panic(
    "Dummy panic\n"
    "*** END OF TEST Tests for error reporting routines - 03 ***\n"
  );
  

  rtems_test_exit(0);
}
Example #15
0
static uint16_t ReadPHY(EMACLocals* ep, uint8_t reg)
{
  int n = 0;
  uint32_t t;
  
  reg &= 0x1F;
  
  /* 405EX-specific! */
  while ((ep->EMAC->STAcontrol & keSTARun) != 0)
    { ; }
  ep->EMAC->STAcontrol = keSTADirectRd + (ep->phyAddr<<5) + reg;
  ep->EMAC->STAcontrol |= keSTARun;
  /* Wait for the read to complete, should take ~25usec */
  do {
    t = ep->EMAC->STAcontrol;
    if (++n > 200000) 
      rtems_panic("PHY read timed out");
  } while ((t & keSTARun) != 0);
  
  if (t & kSTAErr) 
    rtems_panic("PHY read failed");
  return t >> 16;
}
Example #16
0
static void InstallIRQHandler(rtems_irq_number id,
                rtems_irq_hdl handler,
                rtems_irq_enable turnOn,
                rtems_irq_disable turnOff)
{
  rtems_irq_connect_data params;
  
  params.name = id;
  params.hdl = handler;
  params.on = turnOn;
  params.off = turnOff;
  params.isOn = NULL;
  params.handle = NULL;
  if (! BSP_install_rtems_irq_handler(&params))
    rtems_panic ("Can't install interrupt handler");
}
Example #17
0
  /*
   * This code assumes the exceptions management setup has already
   * been done. We just need to replace the exceptions that will
   * be handled like interrupt. On mcp750/mpc750 and many PPC processors
   * this means the decrementer exception and the external exception.
   */
void BSP_rtems_irq_mng_init(unsigned cpuId)
{
  int i;

  /*
   * First initialize the Interrupt management hardware
   */
  OpenPIC = (void*)PSIM.OpenPIC;
  openpic_init(1,0,0,16,0,0);

  /*
   * Initialize Rtems management interrupt table
   */
  /*
   * re-init the rtemsIrq table
   */
  for (i = 0; i < BSP_IRQ_NUMBER; i++) {
    rtemsIrq[i]      = defaultIrq;
    rtemsIrq[i].name = i;
  }
  /*
   * Init initial Interrupt management config
   */
  initial_config.irqNb        = BSP_IRQ_NUMBER;
  initial_config.defaultEntry = defaultIrq;
  initial_config.irqHdlTbl    = rtemsIrq;
  initial_config.irqBase      = BSP_LOWEST_OFFSET;
  initial_config.irqPrioTbl   = irqPrioTable;

  for (i = BSP_PCI_IRQ_LOWEST_OFFSET; i< BSP_PCI_IRQ_NUMBER; i++ ) {
  	irqPrioTable[i] = 8;
  }

  if (!BSP_rtems_irq_mngt_set(&initial_config)) {
    /*
     * put something here that will show the failure...
     */
    rtems_panic(
      "Unable to initialize RTEMS interrupt Management!!! System locked\n"
    );
  }

  #ifdef TRACE_IRQ_INIT
    printk("RTEMS IRQ management is now operationnal\n");
  #endif
}
Example #18
0
/*
 * RTEMS Startup Task
 */
rtems_task
Init (rtems_task_argument ignored)
{
    rtems_status_code sc;

    rtems_print_printer_printf(&rtems_test_printer);

    rtems_test_begin();

    sc = rtems_semaphore_create(rtems_build_name('P','m','t','x'),
                                1,
                                RTEMS_PRIORITY|RTEMS_BINARY_SEMAPHORE|RTEMS_INHERIT_PRIORITY|
                                RTEMS_NO_PRIORITY_CEILING|RTEMS_LOCAL,
                                0,
                                &printMutex);
    if (sc != RTEMS_SUCCESSFUL)
        rtems_panic("Can't create printf mutex:", rtems_status_text(sc));
    printf("\"Network\" initializing!\n");
    rtems_bsdnet_initialize_network();
    printf("\"Network\" initialized!\n");

    printf("Try running client with no server present.\n");
    printf("Should fail with `connection refused'.\n");
    clientWorker(0);

    printf("\nStart server.\n");
    spawnTask(serverTask, 150, 0);

    printf("\nTry running client with server present.\n");
    spawnTask(clientTask, 120, 1);
    rtems_task_wake_after(500);

    printf("\nTry running two clients.\n");
    spawnTask(clientTask, 120, 2);
    spawnTask(clientTask, 120, 3);
    rtems_task_wake_after(500);

    printf("\nTry running three clients.\n");
    spawnTask(clientTask, 120, 4);
    spawnTask(clientTask, 120, 5);
    spawnTask(clientTask, 120, 6);

    rtems_task_wake_after(500);
    rtems_test_end();
    exit( 0 );
}
Example #19
0
/*
 * Send a command to the CPM RISC processer
 */
void *
M360AllocateBufferDescriptors (int count)
{
	unsigned int i;
	ISR_Level level;
	void *bdp = NULL;
	unsigned int want = count * sizeof(m360BufferDescriptor_t);

	/*
	 * Running with interrupts disabled is usually considered bad
	 * form, but this routine is probably being run as part of an
	 * initialization sequence so the effect shouldn't be too severe.
	 */
	_ISR_Local_disable (level);
	for (i = 0 ; i < sizeof(bdregions) / sizeof(bdregions[0]) ; i++) {
		/*
		 * Verify that the region exists.
		 * This test is necessary since some chips have
		 * less dual-port RAM.
		 */
		if (bdregions[i].used == 0) {
			volatile uint8_t *cp = bdregions[i].base;
			*cp = 0xAA;
			if (*cp != 0xAA) {
				bdregions[i].used = bdregions[i].size;
				continue;
			}
			*cp = 0x55;
			if (*cp != 0x55) {
				bdregions[i].used = bdregions[i].size;
				continue;
			}
			*cp = 0x0;
		}
		if (bdregions[i].size - bdregions[i].used >= want) {
			bdp = bdregions[i].base + bdregions[i].used;
			bdregions[i].used += want;
			break;
		}
	}
	_ISR_Local_enable (level);
	if (bdp == NULL)
		rtems_panic ("Can't allocate %d buffer descriptor(s).\n", count);
	return bdp;
}
Example #20
0
/*=========================================================================*\
| Function:                                                                 |
\*-------------------------------------------------------------------------*/
void mcdma_glue_init
(
/*-------------------------------------------------------------------------*\
| Purpose:                                                                  |
|   initialize the mcdma module (if not yet done):                          |
|   - load code                                                             |
|   - initialize registers                                                  |
|   - initialize bus arbiter                                                |
|   - initialize interrupt control                                          |
+---------------------------------------------------------------------------+
| Input Parameters:                                                         |
\*-------------------------------------------------------------------------*/
 void *sram_base         /* base address for SRAM, to be used for DMA task */
)
/*-------------------------------------------------------------------------*\
| Return Value:                                                             |
|    none                                                                   |
\*=========================================================================*/
{
  rtems_isr_entry old_handler;
  if (!mcdma_glue_is_initialized) {
    mcdma_glue_is_initialized = true;

    MCD_initDma((dmaRegs *)&MCF548X_DMA_TASKBAR,
		sram_base,
		MCD_TT_FLAGS_DEF);

    /*
     * initialize interrupt dispatcher
     */
    if(rtems_interrupt_catch(mcdma_glue_irq_dispatcher,
			     MCDMA_IRQ_VECTOR,
			     &old_handler)) {
      rtems_panic ("Can't attach MFC548x MCDma interrupt handler\n");
    }
    MCF548X_INTC_ICRn(MCDMA_IRQ_VECTOR - 64) =
      MCF548X_INTC_ICRn_IL(MCDMA_IRQ_LEVEL) |
      MCF548X_INTC_ICRn_IP(MCDMA_IRQ_PRIORITY);

    MCF548X_INTC_IMRH &= ~(1 << (MCDMA_IRQ_VECTOR % 32));
  }
}
Example #21
0
void rx_init(void)
{
  rtems_semaphore_create(rtems_build_name('s', 'R', 'X', ' '), 0,
      RTEMS_DEFAULT_ATTRIBUTES, 1, &rx_sem);

  rtems_status_code sc = rtems_interrupt_handler_install(LM3S69XX_IRQ_GPIO_PORT_D,
      "PORT D",
      RTEMS_INTERRUPT_UNIQUE,
      rx_irq_handler,
      NULL);

  if (sc != RTEMS_SUCCESSFUL)
    rtems_panic("failed to install handler!\n");

  rtems_interrupt_level level;
  rtems_interrupt_disable(level);
  volatile lm3s69xx_gpio *portd = LM3S69XX_GPIO(LM3S69XX_PORT_D);
  portd->im |= (1U << 3);
  rtems_interrupt_enable(level);
}
Example #22
0
/*
 * Initialize the ethernet hardware
 */
static void
m8xx_enet_initialize (struct m8xx_enet_struct *sc)
{
  int i;
  unsigned char *hwaddr;

  /*
   * Configure port A
   * PA15 is enet RxD. Set PAPAR(15) to 1, PADIR(15) to 0.
   * PA14 is enet TxD. Set PAPAR(14) to 1, PADIR(14) to 0, PAODR(14) to 0.
   * PA7 is input CLK1. Set PAPAR(7) to 1, PADIR(7) to 0.
   * PA6 is input CLK2. Set PAPAR(6) to 1, PADIR(6) to 0.
   */
  m8xx.papar |=  0x303;
  m8xx.padir &= ~0x303;
  m8xx.paodr &= ~0x2;

  /*
   * Configure port C
   * PC11 is CTS1*. Set PCPAR(11) to 0, PCDIR(11) to 0, and PCSO(11) to 1.
   * PC10 is CD1*. Set PCPAR(10) to 0, PCDIR(10) to 0, and PCSO(10) to 1.
   */
  m8xx.pcpar &= ~0x30;
  m8xx.pcdir &= ~0x30;
  m8xx.pcso  |=  0x30;

  /*
   * Connect CLK1 and CLK2 to SCC1 in the SICR.
   * CLK1 is TxClk, CLK2 is RxClk. No grant mechanism, SCC1 is directly
   * connected to the NMSI pins.
   * R1CS = 0b101 (CLK2)
   * T1CS = 0b100 (CLK1)
   */
  m8xx.sicr |= 0x2C;

  /*
   * Initialize SDMA configuration register
   */
  m8xx.sdcr = 1;

  /*
   * Allocate mbuf pointers
   */
  sc->rxMbuf = malloc (sc->rxBdCount * sizeof *sc->rxMbuf,
		       M_MBUF, M_NOWAIT);
  sc->txMbuf = malloc (sc->txBdCount * sizeof *sc->txMbuf,
		       M_MBUF, M_NOWAIT);
  if (!sc->rxMbuf || !sc->txMbuf)
    rtems_panic ("No memory for mbuf pointers");

  /*
   * Set receiver and transmitter buffer descriptor bases
   */
  sc->rxBdBase = m8xx_bd_allocate(sc->rxBdCount);
  sc->txBdBase = m8xx_bd_allocate(sc->txBdCount);
  m8xx.scc1p.rbase = (char *)sc->rxBdBase - (char *)&m8xx;
  m8xx.scc1p.tbase = (char *)sc->txBdBase - (char *)&m8xx;

  /*
   * Send "Init parameters" command
   */
  m8xx_cp_execute_cmd (M8xx_CR_OP_INIT_RX_TX | M8xx_CR_CHAN_SCC1);

  /*
   * Set receive and transmit function codes
   */
  m8xx.scc1p.rfcr = M8xx_RFCR_MOT | M8xx_RFCR_DMA_SPACE(0);
  m8xx.scc1p.tfcr = M8xx_TFCR_MOT | M8xx_TFCR_DMA_SPACE(0);

  /*
   * Set maximum receive buffer length
   */
  m8xx.scc1p.mrblr = RBUF_SIZE;

  /*
   * Set CRC parameters
   */
  m8xx.scc1p.un.ethernet.c_pres = 0xFFFFFFFF;
  m8xx.scc1p.un.ethernet.c_mask = 0xDEBB20E3;

  /*
   * Clear diagnostic counters
   */
  m8xx.scc1p.un.ethernet.crcec = 0;
  m8xx.scc1p.un.ethernet.alec = 0;
  m8xx.scc1p.un.ethernet.disfc = 0;

  /*
   * Set pad value
   */
  m8xx.scc1p.un.ethernet.pads = 0x8888;

  /*
   * Set retry limit
   */
  m8xx.scc1p.un.ethernet.ret_lim = 15;

  /*
   * Set maximum and minimum frame length
   */
  m8xx.scc1p.un.ethernet.mflr = 1518;
  m8xx.scc1p.un.ethernet.minflr = 64;
  m8xx.scc1p.un.ethernet.maxd1 = MAX_MTU_SIZE;
  m8xx.scc1p.un.ethernet.maxd2 = MAX_MTU_SIZE;

  /*
   * Clear group address hash table
   */
  m8xx.scc1p.un.ethernet.gaddr1 = 0;
  m8xx.scc1p.un.ethernet.gaddr2 = 0;
  m8xx.scc1p.un.ethernet.gaddr3 = 0;
  m8xx.scc1p.un.ethernet.gaddr4 = 0;

  /*
   * Set our physical address
   */
  hwaddr = sc->arpcom.ac_enaddr;

  m8xx.scc1p.un.ethernet.paddr_h = (hwaddr[5] << 8) | hwaddr[4];
  m8xx.scc1p.un.ethernet.paddr_m = (hwaddr[3] << 8) | hwaddr[2];
  m8xx.scc1p.un.ethernet.paddr_l = (hwaddr[1] << 8) | hwaddr[0];

  /*
   * Aggressive retry
   */
  m8xx.scc1p.un.ethernet.p_per = 0;

  /*
   * Clear individual address hash table
   */
  m8xx.scc1p.un.ethernet.iaddr1 = 0;
  m8xx.scc1p.un.ethernet.iaddr2 = 0;
  m8xx.scc1p.un.ethernet.iaddr3 = 0;
  m8xx.scc1p.un.ethernet.iaddr4 = 0;

  /*
   * Clear temp address
   */
  m8xx.scc1p.un.ethernet.taddr_l = 0;
  m8xx.scc1p.un.ethernet.taddr_m = 0;
  m8xx.scc1p.un.ethernet.taddr_h = 0;

  /*
   * Set up receive buffer descriptors
   */
  for (i = 0 ; i < sc->rxBdCount ; i++) {
    (sc->rxBdBase + i)->status = 0;
  }

  /*
   * Set up transmit buffer descriptors
   */
  for (i = 0 ; i < sc->txBdCount ; i++) {
    (sc->txBdBase + i)->status = 0;
    sc->txMbuf[i] = NULL;
  }
  sc->txBdHead = sc->txBdTail = 0;
  sc->txBdActiveCount = 0;

  /*
   * Clear any outstanding events
   */
  m8xx.scc1.scce = 0xFFFF;

  /*
   * Set up interrupts
   */
  if (!BSP_install_rtems_irq_handler (&ethernetSCC1IrqData)) {
    rtems_panic ("Can't attach M8xx SCC1 interrupt handler\n");
  }
  m8xx.scc1.sccm = 0;     /* No interrupts unmasked till necessary */

  /*
   * Set up General SCC Mode Register
   * Ethernet configuration
   */
  m8xx.scc1.gsmr_h = 0x0;
  m8xx.scc1.gsmr_l = 0x1088000c;

  /*
   * Set up data synchronization register
   * Ethernet synchronization pattern
   */
  m8xx.scc1.dsr = 0xd555;

  /*
   * Set up protocol-specific mode register
   *      No Heartbeat check
   *      No force collision
   *      Discard short frames
   *      Individual address mode
   *      Ethernet CRC
   *      Not promisuous
   *      Ignore/accept broadcast packets as specified
   *      Normal backoff timer
   *      No loopback
   *      No input sample at end of frame
   *      64-byte limit for late collision
   *      Wait 22 bits before looking for start of frame delimiter
   *      Disable full-duplex operation
   */
  m8xx.scc1.psmr = 0x080A | (sc->acceptBroadcast ? 0 : 0x100);

  /*
   * Enable the TENA (RTS1*) pin
   */
  m8xx.pcpar |=  0x1;
  m8xx.pcdir &= ~0x1;

  /*
   * Enable receiver and transmitter
   */
  m8xx.scc1.gsmr_l = 0x1088003c;
}
Example #23
0
static void
mcf5282_fec_initialize_hardware(struct mcf5282_enet_struct *sc)
{
    int i;
    const unsigned char *hwaddr;
    rtems_status_code status;
    rtems_isr_entry old_handler;
	uint32_t clock_speed = bsp_get_CPU_clock_speed();

    /*
     * Issue reset to FEC
     */
    MCF5282_FEC_ECR = MCF5282_FEC_ECR_RESET;
    rtems_task_wake_after(2);
    MCF5282_FEC_ECR = 0;

    /*
     * Configuration of I/O ports is done outside of this function
     */
#if 0
    imm->gpio.pbcnt |= MCF5282_GPIO_PBCNT_SET_FEC;        /* Set up port b FEC pins */
#endif

    /*
     * Set our physical address
     */
    hwaddr = sc->arpcom.ac_enaddr;
    MCF5282_FEC_PALR = (hwaddr[0] << 24) | (hwaddr[1] << 16) |
                       (hwaddr[2] << 8)  | (hwaddr[3] << 0);
    MCF5282_FEC_PAUR = (hwaddr[4] << 24) | (hwaddr[5] << 16);


    /*
     * Clear the hash table
     */
    MCF5282_FEC_GAUR = 0;
    MCF5282_FEC_GALR = 0;

    /*
     * Set up receive buffer size
     */
    MCF5282_FEC_EMRBR = 1520; /* Standard Ethernet */

    /*
     * Allocate mbuf pointers
     */
    sc->rxMbuf = malloc(sc->rxBdCount * sizeof *sc->rxMbuf, M_MBUF, M_NOWAIT);
    sc->txMbuf = malloc(sc->txBdCount * sizeof *sc->txMbuf, M_MBUF, M_NOWAIT);
    if (!sc->rxMbuf || !sc->txMbuf)
        rtems_panic("No memory for mbuf pointers");

    /*
     * Set receiver and transmitter buffer descriptor bases
     */
    sc->rxBdBase = mcf5282_bd_allocate(sc->rxBdCount);
    sc->txBdBase = mcf5282_bd_allocate(sc->txBdCount);
    MCF5282_FEC_ERDSR = (int)sc->rxBdBase;
    MCF5282_FEC_ETDSR = (int)sc->txBdBase;

    /*
     * Set up Receive Control Register:
     *   Not promiscuous
     *   MII mode
     *   Full duplex
     *   No loopback
     */
    MCF5282_FEC_RCR = MCF5282_FEC_RCR_MAX_FL(MAX_MTU_SIZE) |
                      MCF5282_FEC_RCR_MII_MODE;

    /*
     * Set up Transmit Control Register:
     *   Full or half duplex
     *   No heartbeat
     */
    if (sc->link == link_10Half)
        MCF5282_FEC_TCR = 0;
    else
    MCF5282_FEC_TCR = MCF5282_FEC_TCR_FDEN;

    /*
     * Initialize statistic counters
     */
    MCF5282_FEC_MIBC = MCF5282_FEC_MIBC_MIB_DISABLE;
    {
    vuint32 *vuip = &MCF5282_FEC_RMON_T_DROP;
    while (vuip <= &MCF5282_FEC_IEEE_R_OCTETS_OK)
        *vuip++ = 0;
    }
    MCF5282_FEC_MIBC = 0;

    /*
     * Set MII speed to <= 2.5 MHz
     */
    i = (clock_speed + 5000000 - 1) / 5000000;
    MCF5282_FEC_MSCR = MCF5282_FEC_MSCR_MII_SPEED(i);

    /*
     * Set PHYS
     *  LED1 receive status, LED2 link status, LEDs stretched
     *  Advertise 100 Mb/s, full-duplex, IEEE-802.3
     *  Turn off auto-negotiate
     *  Clear status
     */
    setMII(1, 20, 0x24F2);
    setMII(1,  4, 0x0181);
    setMII(1,  0, 0x0);
    rtems_task_wake_after(2);
    sc->mii_sr2 = getMII(1, 17);
    switch (sc->link) {
    case link_auto:
        /*
         * Enable speed-change, duplex-change and link-status-change interrupts
         * Enable auto-negotiate (start at 100/FULL)
         */
    setMII(1, 18, 0x0072);
        setMII(1, 0, 0x3100);
        break;

    case link_10Half:
        /*
         * Force 10/HALF
         */
        setMII(1, 0, 0x0);
        break;

    case link_100Full:
        /*
         * Force 100/FULL
         */
        setMII(1, 0, 0x2100);
        break;
    }
    sc->mii_cr = getMII(1, 0);

    /*
     * Set up receive buffer descriptors
     */
    for (i = 0 ; i < sc->rxBdCount ; i++)
        (sc->rxBdBase + i)->status = 0;

    /*
     * Set up transmit buffer descriptors
     */
    for (i = 0 ; i < sc->txBdCount ; i++) {
        sc->txBdBase[i].status = 0;
        sc->txMbuf[i] = NULL;
    }
    sc->txBdHead = sc->txBdTail = 0;
    sc->txBdActiveCount = 0;

    /*
     * Set up interrupts
     */
    status = rtems_interrupt_catch( mcf5282_fec_tx_interrupt_handler, FEC_INTC0_TX_VECTOR, &old_handler );
    if (status != RTEMS_SUCCESSFUL)
        rtems_panic ("Can't attach MCF5282 FEC TX interrupt handler: %s\n",
                                                 rtems_status_text(status));
    bsp_allocate_interrupt(FEC_IRQ_LEVEL, FEC_IRQ_TX_PRIORITY);
    MCF5282_INTC0_ICR23 = MCF5282_INTC_ICR_IL(FEC_IRQ_LEVEL) |
                          MCF5282_INTC_ICR_IP(FEC_IRQ_TX_PRIORITY);
    MCF5282_INTC0_IMRL &= ~(MCF5282_INTC_IMRL_INT23 | MCF5282_INTC_IMRL_MASKALL);

    status = rtems_interrupt_catch(mcf5282_fec_rx_interrupt_handler, FEC_INTC0_RX_VECTOR, &old_handler);
    if (status != RTEMS_SUCCESSFUL)
        rtems_panic ("Can't attach MCF5282 FEC RX interrupt handler: %s\n",
                                                 rtems_status_text(status));
    bsp_allocate_interrupt(FEC_IRQ_LEVEL, FEC_IRQ_RX_PRIORITY);
    MCF5282_INTC0_ICR27 = MCF5282_INTC_ICR_IL(FEC_IRQ_LEVEL) |
                          MCF5282_INTC_ICR_IP(FEC_IRQ_RX_PRIORITY);
    MCF5282_INTC0_IMRL &= ~(MCF5282_INTC_IMRL_INT27 | MCF5282_INTC_IMRL_MASKALL);

    status = rtems_interrupt_catch(mcf5282_mii_interrupt_handler, MII_VECTOR, &old_handler);
    if (status != RTEMS_SUCCESSFUL)
        rtems_panic ("Can't attach MCF5282 FEC MII interrupt handler: %s\n",
                                                 rtems_status_text(status));
    MCF5282_EPORT_EPPAR &= ~MII_EPPAR;
    MCF5282_EPORT_EPDDR &= ~MII_EPDDR;
    MCF5282_EPORT_EPIER |=  MII_EPIER;
    MCF5282_INTC0_IMRL &= ~(MCF5282_INTC_IMRL_INT7 | MCF5282_INTC_IMRL_MASKALL);
}
Example #24
0
void bsp_start( void)
{
  rtems_status_code sc = RTEMS_SUCCESSFUL;
  unsigned long i = 0;

  /*
   * Get CPU identification dynamically. Note that the get_ppc_cpu_type() function
   * store the result in global variables so that it can be used latter...
   */
  get_ppc_cpu_type();
  get_ppc_cpu_revision();

  /* Basic CPU initialization */
  cpu_init();

  /*
   * Enable instruction and data caches. Do not force writethrough mode.
   */

#ifdef BSP_INSTRUCTION_CACHE_ENABLED
  rtems_cache_enable_instruction();
#endif

#ifdef BSP_DATA_CACHE_ENABLED
  rtems_cache_enable_data();
#endif

  /*
   * This is evaluated during runtime, so it should be ok to set it
   * before we initialize the drivers.
   */

  /* Initialize some device driver parameters */

#ifdef HAS_UBOOT
  BSP_bus_frequency = bsp_uboot_board_info.bi_busfreq;
#else /* HAS_UBOOT */
  BSP_bus_frequency = BSP_CLKIN_FRQ * BSP_SYSPLL_MF / BSP_SYSPLL_CKID;
#endif /* HAS_UBOOT */
  bsp_time_base_frequency = BSP_bus_frequency / 4;
  bsp_clicks_per_usec = bsp_time_base_frequency / 1000000;
  rtems_counter_initialize_converter(bsp_time_base_frequency);

  /* Initialize some console parameters */
  for (i = 0; i < console_device_count; ++i) {
    ns16550_context *ctx = (ns16550_context *) console_device_table[i].context;

    ctx->clock = BSP_bus_frequency;

    #ifdef HAS_UBOOT
      ctx->initial_baud = bsp_uboot_board_info.bi_baudrate;
    #endif
  }

  /* Initialize exception handler */
#ifndef BSP_DATA_CACHE_ENABLED
  ppc_exc_cache_wb_check = 0;
#endif
  ppc_exc_initialize(
    (uintptr_t) bsp_section_work_begin,
    rtems_configuration_get_interrupt_stack_size()
  );

  /* Install default handler for the decrementer exception */
  sc = ppc_exc_set_handler( ASM_DEC_VECTOR, mpc83xx_decrementer_exception_handler);
  if (sc != RTEMS_SUCCESSFUL) {
    rtems_panic("cannot install decrementer exception handler");
  }

  /* Initalize interrupt support */
  bsp_interrupt_initialize();

#ifdef SHOW_MORE_INIT_SETTINGS
  printk("Exit from bspstart\n");
#endif
}
Example #25
0
/*
 * Initialize the SCC hardware
 * Configure I/O ports for SCC3
 * Internal Tx clock, External Rx clock
 */
static void
m8260_scc_initialize_hardware (struct m8260_hdlc_struct *sc)
{
  int i;
  int brg;

  rtems_status_code status;

  /* RxD PB14 */
  m8260.pparb |=  0x00020000;
  m8260.psorb &= ~0x00020000;
  m8260.pdirb &= ~0x00020000;

  /* RxC (CLK5) PC27 */
  m8260.pparc |=  0x00000010;
  m8260.psorc &= ~0x00000010;
  m8260.pdirc &= ~0x00000010;

  /* TxD PD24 and TxC PD10 (BRG4) */
  m8260.ppard |=  0x00200080;
  m8260.psord |=  0x00200000;
  m8260.psord &= ~0x00000080;
  m8260.pdird |=  0x00200080;

  /* External Rx Clock from CLK5 */
  if( m8xx_get_clk( M8xx_CLK_5 ) == -1 )
    printk( "Error allocating CLK5 for network device.\n" );
  else
    m8260.cmxscr |= 0x00002000;

  /* Internal Tx Clock from BRG4 */
  if( (brg = m8xx_get_brg(M8xx_BRG_4, 8000000 )) == -1 )
    printk( "Error allocating BRG for network device\n" );
  else
    m8260.cmxscr |= ((unsigned)brg << 8);

  /*
   * Allocate mbuf pointers
   */
  sc->rxMbuf = malloc (sc->rxBdCount * sizeof *sc->rxMbuf,
		       M_MBUF, M_NOWAIT);
  sc->txMbuf = malloc (sc->txBdCount * sizeof *sc->txMbuf,
		       M_MBUF, M_NOWAIT);
  if (!sc->rxMbuf || !sc->txMbuf)
    rtems_panic ("No memory for mbuf pointers");

  /*
   * Set receiver and transmitter buffer descriptor bases
   */
  sc->rxBdBase = m8xx_bd_allocate (sc->rxBdCount);
  sc->txBdBase = m8xx_bd_allocate (sc->txBdCount);

  m8260.scc3p.rbase = (char *)sc->rxBdBase - (char *)&m8260;
  m8260.scc3p.tbase = (char *)sc->txBdBase - (char *)&m8260;

  /*
   * Send "Init parameters" command
   */

  m8xx_cp_execute_cmd (M8260_CR_OP_INIT_RX_TX | M8260_CR_SCC3 );

  /*
   * Set receive and transmit function codes
   */
  m8260.scc3p.rfcr = M8260_RFCR_MOT | M8260_RFCR_60X_BUS;
  m8260.scc3p.tfcr = M8260_TFCR_MOT | M8260_TFCR_60X_BUS;

  /*
   * Set maximum receive buffer length
   */
  m8260.scc3p.mrblr = RBUF_SIZE;

  m8260.scc3p.un.hdlc.c_mask = 0xF0B8;
  m8260.scc3p.un.hdlc.c_pres = 0xFFFF;
  m8260.scc3p.un.hdlc.disfc  = 0;
  m8260.scc3p.un.hdlc.crcec  = 0;
  m8260.scc3p.un.hdlc.abtsc  = 0;
  m8260.scc3p.un.hdlc.nmarc  = 0;
  m8260.scc3p.un.hdlc.retrc  = 0;
  m8260.scc3p.un.hdlc.rfthr  = 1;
  m8260.scc3p.un.hdlc.mflr   = RBUF_SIZE;

  m8260.scc3p.un.hdlc.hmask  = 0x0000;	/* promiscuous */

  m8260.scc3p.un.hdlc.haddr1 = 0xFFFF;	/* Broadcast address */
  m8260.scc3p.un.hdlc.haddr2 = 0xFFFF;	/* Station address */
  m8260.scc3p.un.hdlc.haddr3 = 0xFFFF;	/* Dummy */
  m8260.scc3p.un.hdlc.haddr4 = 0xFFFF;	/* Dummy */

  /*
   * Send "Init parameters" command
   */
/*
  m8xx_cp_execute_cmd (M8260_CR_OP_INIT_RX_TX | M8260_CR_SCC3 );
*/

  /*
   * Set up receive buffer descriptors
   */
  for (i = 0 ; i < sc->rxBdCount ; i++) {
    (sc->rxBdBase + i)->status = 0;
  }

  /*
   * Set up transmit buffer descriptors
   */
  for (i = 0 ; i < sc->txBdCount ; i++) {
    (sc->txBdBase + i)->status = 0;
    sc->txMbuf[i] = NULL;
  }
  sc->txBdHead = sc->txBdTail = 0;
  sc->txBdActiveCount = 0;

  m8260.scc3.sccm = 0;     /* No interrupts unmasked till necessary */

  /*
   * Clear any outstanding events
   */
  m8260.scc3.scce = 0xFFFF;

  /*
   * Set up interrupts
   */
  status = BSP_install_rtems_irq_handler (&hdlcSCC3IrqData);
/*
  printk( "status = %d, Success = %d\n", status, RTEMS_SUCCESSFUL );
*/
  if (status != 1 /*RTEMS_SUCCESSFUL*/ ) {
    rtems_panic ("Can't attach M8260 SCC3 interrupt handler: %s\n",
		 rtems_status_text (status));
  }
  m8260.scc3.sccm = 0;     /* No interrupts unmasked till necessary */

  m8260.scc3.gsmr_h  = 0;
  m8260.scc3.gsmr_l  = 0x10000000;
  m8260.scc3.dsr     = 0x7E7E;	/* flag character */
  m8260.scc3.psmr    = 0x2000;	/* 2 flags between Tx'd frames */

/*  printk("scc3 init\n" ); */

  m8260.scc3.gsmr_l |=  0x00000030;  /* Set ENR and ENT to enable Rx and Tx */

}
Example #26
0
void bsp_start( void)
{

  uintptr_t interrupt_stack_start = (uintptr_t) bsp_interrupt_stack_start;
  uintptr_t interrupt_stack_size = (uintptr_t) bsp_interrupt_stack_size;

  /*
   * Get CPU identification dynamically. Note that the get_ppc_cpu_type()
   * function stores the result in global variables so that it can be used
   * later...
   */
  get_ppc_cpu_type();
  get_ppc_cpu_revision();

  /* Basic CPU initialization */
  cpu_init();

  /*
   * Enable instruction and data caches. Do not force writethrough mode.
   */

#if BSP_INSTRUCTION_CACHE_ENABLED
  rtems_cache_enable_instruction();
#endif

#if BSP_DATA_CACHE_ENABLED
  rtems_cache_enable_data();
#endif

  /*
   * This is evaluated during runtime, so it should be ok to set it
   * before we initialize the drivers.
   */

  /* Initialize some device driver parameters */
  /*
   * get the (internal) bus frequency
   * NOTE: the external bus may be clocked at a lower speed
   * but this does not concern the internal units like PIT,
   * DEC, baudrate generator etc)
   */
  if (RTEMS_SUCCESSFUL !=
      bsp_tqm_get_cib_uint32("cu",
			     &BSP_bus_frequency)) {
    rtems_panic("Cannot determine BUS frequency\n");
  }

  bsp_time_base_frequency = BSP_bus_frequency / 16;
  bsp_clicks_per_usec = bsp_time_base_frequency / 1000000;
  bsp_timer_least_valid = 3;
  bsp_timer_average_overhead = 3;
  rtems_counter_initialize_converter(bsp_time_base_frequency);

  /* Initialize exception handler */
  ppc_exc_initialize(interrupt_stack_start, interrupt_stack_size);

  /* Initalize interrupt support */
  bsp_interrupt_initialize();

#ifdef SHOW_MORE_INIT_SETTINGS
  printk("Exit from bspstart\n");
#endif
}
Example #27
0
static void
sccInitialize (int chan)
{
  int i;
  /*
   * allocate buffers
   * FIXME: use a cache-line size boundary alloc here
   */
  rxBuf[chan] = malloc(sizeof(*rxBuf[chan]) + 2*PPC_CACHE_ALIGNMENT);
  if (rxBuf[chan] == NULL) {
    BSP_panic("Cannot allocate console rx buffer\n");
  }
  else {
    /*
     * round up rxBuf[chan] to start at a cache line size
     */
    rxBuf[chan] = (sccRxBuf_t *)
      (((uint32_t)rxBuf[chan]) +
       (PPC_CACHE_ALIGNMENT
	- ((uint32_t)rxBuf[chan]) % PPC_CACHE_ALIGNMENT));
  }
  /*
   * Allocate buffer descriptors
   */
  sccCurrRxBd[chan] =
    sccFrstRxBd[chan] = m8xx_bd_allocate(SCC_RXBD_CNT);
  sccPrepTxBd[chan] =
    sccDequTxBd[chan] =
    sccFrstTxBd[chan] = m8xx_bd_allocate(SCC_TXBD_CNT);
  switch(chan) {
  case CONS_CHN_SCC1:
    /*
     * Configure port A pins to enable TXD1 and RXD1 pins
     * FIXME: add setup for modem control lines....
     */
    m8xx.papar |=  0x03;
    m8xx.padir &= ~0x03;

    /*
     * Configure port C pins to enable RTS1 pins (static active low)
     */
    m8xx.pcpar &= ~0x01;
    m8xx.pcso  &= ~0x01;
    m8xx.pcdir |=  0x01;
    m8xx.pcdat &= ~0x01;
    break;
  case CONS_CHN_SCC2:
    /*
     * Configure port A pins to enable TXD2 and RXD2 pins
     * FIXME: add setup for modem control lines....
     */
    m8xx.papar |=  0x0C;
    m8xx.padir &= ~0x0C;

    /*
     * Configure port C pins to enable RTS2 pins (static active low)
     */
    m8xx.pcpar &= ~0x02;
    m8xx.pcso  &= ~0x02;
    m8xx.pcdir |=  0x02;
    m8xx.pcdat &= ~0x02;
    break;
  case CONS_CHN_SCC3:
    /*
     * Configure port A pins to enable TXD3 and RXD3 pins
     * FIXME: add setup for modem control lines....
     */
    m8xx.papar |=  0x30;
    m8xx.padir &= ~0x30;

    /*
     * Configure port C pins to enable RTS3 (static active low)
     */
    m8xx.pcpar &= ~0x04;
    m8xx.pcso  &= ~0x04;
    m8xx.pcdir |=  0x04;
    m8xx.pcdat &= ~0x04;
    break;
  case CONS_CHN_SCC4:
    /*
     * Configure port A pins to enable TXD4 and RXD4 pins
     * FIXME: add setup for modem control lines....
     */
    m8xx.papar |=  0xC0;
    m8xx.padir &= ~0xC0;

    /*
     * Configure port C pins to enable RTS4 pins (static active low)
     */
    m8xx.pcpar &= ~0x08;
    m8xx.pcso  &= ~0x08;
    m8xx.pcdir |=  0x08;
    m8xx.pcdat &= ~0x08;
    break;
  case CONS_CHN_SMC1:
    /*
     * Configure port B pins to enable SMTXD1 and SMRXD1 pins
     */
    m8xx.pbpar |=  0xC0;
    m8xx.pbdir &= ~0xC0;
    break;
  case CONS_CHN_SMC2:
    /*
     * Configure port B pins to enable SMTXD2 and SMRXD2 pins
     */
    m8xx.pbpar |=  0xC00;
    m8xx.pbdir &= ~0xC00;
    break;
  }
  /*
   * allocate and connect BRG
   */
  sccBRGalloc(chan,9600);


  /*
   * Set up SCCx parameter RAM common to all protocols
   */
  CHN_PARAM_SET(chan,rbase,(char *)sccFrstRxBd[chan] - (char *)&m8xx);
  CHN_PARAM_SET(chan,tbase,(char *)sccFrstTxBd[chan] - (char *)&m8xx);
  CHN_PARAM_SET(chan,rfcr ,M8xx_RFCR_MOT | M8xx_RFCR_DMA_SPACE(0));
  CHN_PARAM_SET(chan,tfcr ,M8xx_TFCR_MOT | M8xx_TFCR_DMA_SPACE(0));
  if (m8xx_scc_mode[chan] != TERMIOS_POLLED)
    CHN_PARAM_SET(chan,mrblr,RXBUFSIZE);
  else
    CHN_PARAM_SET(chan,mrblr,1);

  /*
   * Set up SCCx parameter RAM UART-specific parameters
   */
  CHN_PARAM_SET(chan,un.uart.max_idl ,MAX_IDL_DEFAULT);
  CHN_PARAM_SET(chan,un.uart.brkln   ,0);
  CHN_PARAM_SET(chan,un.uart.brkec   ,0);
  CHN_PARAM_SET(chan,un.uart.brkcr   ,0);
  if (m8xx_console_chan_desc[chan].is_scc) {
    m8xx_console_chan_desc[chan].parms.sccp->un.uart.character[0]=0x8000; /* no char filter */
    m8xx_console_chan_desc[chan].parms.sccp->un.uart.rccm=0x80FF; /* control character mask */
  }

  /*
   * Set up the Receive Buffer Descriptors
   */
  for (i = 0;i < SCC_RXBD_CNT;i++) {
    sccFrstRxBd[chan][i].status = M8xx_BD_EMPTY | M8xx_BD_INTERRUPT;
    if (i == SCC_RXBD_CNT-1) {
      sccFrstRxBd[chan][i].status |= M8xx_BD_WRAP;
    }
    sccFrstRxBd[chan][i].length = 0;
    sccFrstRxBd[chan][i].buffer = (*rxBuf[chan])[i];
  }
  /*
   * Setup the Transmit Buffer Descriptor
   */
  for (i = 0;i < SCC_TXBD_CNT;i++) {
    sccFrstTxBd[chan][i].status = M8xx_BD_INTERRUPT;
    if (i == SCC_TXBD_CNT-1) {
      sccFrstTxBd[chan][i].status |= M8xx_BD_WRAP;
    }
    sccFrstTxBd[chan][i].length = 0;
    sccFrstTxBd[chan][i].buffer = NULL;
  }

  /*
   * Set up SCC general and protocol-specific mode registers
   */
  CHN_EVENT_CLR(chan,~0);	/* Clear any pending events */
  CHN_MASK_SET(chan,0);	        /* Mask all interrupt/event sources */

  if (m8xx_console_chan_desc[chan].is_scc) {
    m8xx_console_chan_desc[chan].regs.sccr->psmr = 0xb000; /* 8N1, CTS flow control */
    m8xx_console_chan_desc[chan].regs.sccr->gsmr_h = 0x00000000;
    m8xx_console_chan_desc[chan].regs.sccr->gsmr_l = 0x00028004; /* UART mode */
  }
  else {
    m8xx_console_chan_desc[chan].regs.smcr->smcmr = 0x4820;
  }
  /*
   * Send "Init parameters" command
   */
  m8xx_cp_execute_cmd(M8xx_CR_OP_INIT_RX_TX
		      | m8xx_console_chan_desc[chan].cr_chan_code);

  /*
   * Enable receiver and transmitter
   */
  if (m8xx_console_chan_desc[chan].is_scc) {
    m8xx_console_chan_desc[chan].regs.sccr->gsmr_l |= 0x00000030;
  }
  else {
    m8xx_console_chan_desc[chan].regs.smcr->smcmr |= 0x0003;
  }

  if (m8xx_scc_mode[chan] != TERMIOS_POLLED) {

    rtems_irq_connect_data irq_conn_data = {
      m8xx_console_chan_desc[chan].ivec_src,
      sccInterruptHandler,         /* rtems_irq_hdl           */
      (rtems_irq_hdl_param)chan,   /* (rtems_irq_hdl_param)   */
      mpc8xx_console_irq_on,       /* (rtems_irq_enable)      */
      mpc8xx_console_irq_off,      /* (rtems_irq_disable)     */
      mpc8xx_console_irq_isOn      /* (rtems_irq_is_enabled)  */
    };
    if (!BSP_install_rtems_irq_handler (&irq_conn_data)) {
      rtems_panic("console: cannot install IRQ handler");
    }
  }
}
Example #28
0
static void
mcf5272_enet_initialize_hardware (struct mcf5272_enet_struct *sc)
{
    int i;
    unsigned char *hwaddr;
    uint32_t icr;
    /*
     * Issue reset to FEC
     */
    g_enet_regs->ecr=0x1;

    /*
     * Set the TX and RX fifo sizes. For now, we'll split it evenly
     */
    /* If you uncomment these, the FEC will not work right.
       g_enet_regs->r_fstart = ((g_enet_regs->r_bound & 0x3ff) >> 2) & 0x3ff;
       g_enet_regs->x_fstart = 0;
    */

    /* Copy mac address to device */

    hwaddr = sc->arpcom.ac_enaddr;

    g_enet_regs->malr = (hwaddr[0] << 24 |
                         hwaddr[1] << 16 |
                         hwaddr[2] << 8 |
                         hwaddr[3]);
    g_enet_regs->maur = (hwaddr[4] << 24 |
                         hwaddr[5] << 16);

    /*
     * Clear the hash table
     */
    g_enet_regs->htlr = 0;
    g_enet_regs->htur  = 0;

    /*
     * Set up receive buffer size
     */
    g_enet_regs->emrbr = 0x5f0; /* set to 1520 */

    /*
     * Allocate mbuf pointers
     */
    sc->rxMbuf = malloc (sc->rxBdCount * sizeof *sc->rxMbuf,
                         M_MBUF, M_NOWAIT);
    sc->txMbuf = malloc (sc->txBdCount * sizeof *sc->txMbuf,
                         M_MBUF, M_NOWAIT);
    if (!sc->rxMbuf || !sc->txMbuf) {
        rtems_panic ("No memory for mbuf pointers");
    }

    /*
     * Set receiver and transmitter buffer descriptor bases
     */
    sc->rxBdBase = mcf5272_bd_allocate(sc->rxBdCount);
    sc->txBdBase = mcf5272_bd_allocate(sc->txBdCount);
    g_enet_regs->erdsr = (int)sc->rxBdBase;
    g_enet_regs->etdsr = (int)sc->txBdBase;

    /*
     * Set up Receive Control Register:
     *   Not promiscuous mode
     *   MII mode
     *   Full duplex
     *   No loopback
     */
    g_enet_regs->rcr = 0x00000004;

    /*
     * Set up Transmit Control Register:
     *   Full duplex
     *   No heartbeat
     */
    g_enet_regs->tcr = 0x00000004;

    /*
     * Set MII speed to 2.5 MHz for 25 Mhz system clock
     */
    g_enet_regs->mscr = 0x0a;
    g_enet_regs->mmfr = 0x58021000;

    /*
     * Set up receive buffer descriptors
     */
    for (i = 0 ; i < sc->rxBdCount ; i++) {
        (sc->rxBdBase + i)->status = 0;
    }

    /*
     * Set up transmit buffer descriptors
     */
    for (i = 0 ; i < sc->txBdCount ; i++) {
        (sc->txBdBase + i)->status = 0;
        sc->txMbuf[i] = NULL;
    }

    sc->txBdHead = sc->txBdTail = 0;
    sc->txBdActiveCount = 0;

    /*
     * Mask all FEC interrupts and clear events
     */
    g_enet_regs->eimr = (MCF5272_ENET_EIR_TXF |
                        MCF5272_ENET_EIR_RXF);
    g_enet_regs->eir = ~0;

    /*
     * Set up interrupts
     */
    set_vector(enet_rx_isr, BSP_INTVEC_ERX, 1);
    set_vector(enet_tx_isr, BSP_INTVEC_ETX, 1);

    /* Configure ethernet interrupts */
    icr = g_intctrl_regs->icr3;
    icr = icr & ~((MCF5272_ICR3_ERX_MASK | MCF5272_ICR3_ERX_PI) |
                  (MCF5272_ICR3_ETX_MASK | MCF5272_ICR3_ETX_PI));
    icr |= ((MCF5272_ICR3_ERX_IPL(BSP_INTLVL_ERX) | MCF5272_ICR3_ERX_PI)|
            (MCF5272_ICR3_ETX_IPL(BSP_INTLVL_ETX) | MCF5272_ICR3_ETX_PI));
    g_intctrl_regs->icr3 = icr;

}
Example #29
0
/*=========================================================================*\
| Function:                                                                 |
\*-------------------------------------------------------------------------*/
static void m360_spi_install_irq_handler
(
/*-------------------------------------------------------------------------*\
| Purpose:                                                                  |
|   (un-)install the interrupt handler                                      |
+---------------------------------------------------------------------------+
| Input Parameters:                                                         |
\*-------------------------------------------------------------------------*/
 m360_spi_softc_t *softc_ptr,           /* ptr to control structure        */
 int install                            /* TRUE: install, FALSE: remove    */
)
/*-------------------------------------------------------------------------*\
| Return Value:                                                             |
|    <none>                                                                 |
\*=========================================================================*/
{
  rtems_status_code rc = RTEMS_SUCCESSFUL;

  /*
   * (un-)install handler for SPI device
   */
  if (install) {
    /*
     * create semaphore for IRQ synchronization
     */
    rc = rtems_semaphore_create(rtems_build_name('s','p','i','s'),
				0,
				RTEMS_FIFO
				| RTEMS_SIMPLE_BINARY_SEMAPHORE,
				0,
				&softc_ptr->irq_sema_id);
    if (rc != RTEMS_SUCCESSFUL) {
      rtems_panic("SPI: cannot create semaphore");
    }
    if (rc == RTEMS_SUCCESSFUL) {
      rc = rtems_interrupt_catch (m360_spi_irq_handler,
				  (m360.cicr & 0xE0) | 0x05,
				  &softc_ptr->old_handler);
      if (rc != RTEMS_SUCCESSFUL) {
	rtems_panic("SPI: cannot install IRQ handler");
      }
    }
    /*
     * enable IRQ in CPIC
     */
    if (rc == RTEMS_SUCCESSFUL) {
      m360.cimr |= (1 << 5);
    }
  }
  else {
    rtems_isr_entry old_handler;
    /*
     * disable IRQ in CPIC
     */
    if (rc == RTEMS_SUCCESSFUL) {
      m360.cimr &= ~(1 << 5);
    }
    rc = rtems_interrupt_catch (softc_ptr->old_handler,
				(m360.cicr & 0xE0) | 0x05,
				&old_handler);
    if (rc != RTEMS_SUCCESSFUL) {
      rtems_panic("SPI: cannot uninstall IRQ handler");
    }
    /*
     * delete sync semaphore
     */
    if (softc_ptr->irq_sema_id != 0) {
      rc = rtems_semaphore_delete(softc_ptr->irq_sema_id);
      if (rc != RTEMS_SUCCESSFUL) {
	rtems_panic("SPI: cannot delete semaphore");
      }
    }
  }
}
/*
 * Initialize the ethernet hardware
 */
static void
m360Enet_initialize_hardware (struct scc_softc *sc)
{
	int i;
	unsigned char *hwaddr;
	rtems_status_code status;
	rtems_isr_entry old_handler;

	/*
	 * Configure port A CLK1, CLK2, TXD1 and RXD1 pins
	 */
	m360.papar |=  0x303;
	m360.padir &= ~0x303;
	m360.paodr &= ~0x303;

	/*
	 * Configure port C CTS1* and CD1* pins
	 */
	m360.pcpar &= ~0x30;
	m360.pcdir &= ~0x30;
	m360.pcso  |=  0x30;

	/*
	 * Connect CLK1 and CLK2 to SCC1
	 */
	m360.sicr &= ~0xFF;
	m360.sicr |= (5 << 3) | 4;

	/*
	 * Allocate mbuf pointers
	 */
	sc->rxMbuf = malloc (sc->rxBdCount * sizeof *sc->rxMbuf, M_MBUF, M_NOWAIT);
	sc->txMbuf = malloc (sc->txBdCount * sizeof *sc->txMbuf, M_MBUF, M_NOWAIT);
	if (!sc->rxMbuf || !sc->txMbuf)
		rtems_panic ("No memory for mbuf pointers");

	/*
	 * Set receiver and transmitter buffer descriptor bases
	 */
	sc->rxBdBase = M360AllocateBufferDescriptors(sc->rxBdCount);
	sc->txBdBase = M360AllocateBufferDescriptors(sc->txBdCount);
	m360.scc1p.rbase = (char *)sc->rxBdBase - (char *)&m360;
	m360.scc1p.tbase = (char *)sc->txBdBase - (char *)&m360;

	/*
	 * Send "Init parameters" command
	 */
	M360ExecuteRISC (M360_CR_OP_INIT_RX_TX | M360_CR_CHAN_SCC1);

	/*
	 * Set receive and transmit function codes
	 */
	m360.scc1p.rfcr = M360_RFCR_MOT | M360_RFCR_DMA_SPACE;
	m360.scc1p.tfcr = M360_TFCR_MOT | M360_TFCR_DMA_SPACE;

	/*
	 * Set maximum receive buffer length
	 */
	m360.scc1p.mrblr = RBUF_SIZE;

	/*
	 * Set CRC parameters
	 */
	m360.scc1p.un.ethernet.c_pres = 0xFFFFFFFF;
	m360.scc1p.un.ethernet.c_mask = 0xDEBB20E3;

	/*
	 * Clear diagnostic counters
	 */
	m360.scc1p.un.ethernet.crcec = 0;
	m360.scc1p.un.ethernet.alec = 0;
	m360.scc1p.un.ethernet.disfc = 0;

	/*
	 * Set pad value
	 */
	m360.scc1p.un.ethernet.pads = 0x8888;

	/*
	 * Set retry limit
	 */
	m360.scc1p.un.ethernet.ret_lim = 15;

	/*
	 * Set maximum and minimum frame length
	 */
	m360.scc1p.un.ethernet.mflr = 1518;
	m360.scc1p.un.ethernet.minflr = 64;
	m360.scc1p.un.ethernet.maxd1 = RBUF_SIZE;
	m360.scc1p.un.ethernet.maxd2 = RBUF_SIZE;

	/*
	 * Clear group address hash table
	 */
	m360.scc1p.un.ethernet.gaddr1 = 0;
	m360.scc1p.un.ethernet.gaddr2 = 0;
	m360.scc1p.un.ethernet.gaddr3 = 0;
	m360.scc1p.un.ethernet.gaddr4 = 0;

	/*
	 * Set our physical address
	 */
	hwaddr = sc->arpcom.ac_enaddr;
	m360.scc1p.un.ethernet.paddr_h = (hwaddr[5] << 8) | hwaddr[4];
	m360.scc1p.un.ethernet.paddr_m = (hwaddr[3] << 8) | hwaddr[2];
	m360.scc1p.un.ethernet.paddr_l = (hwaddr[1] << 8) | hwaddr[0];

	/*
	 * Aggressive retry
	 */
	m360.scc1p.un.ethernet.p_per = 0;

	/*
	 * Clear individual address hash table
	 */
	m360.scc1p.un.ethernet.iaddr1 = 0;
	m360.scc1p.un.ethernet.iaddr2 = 0;
	m360.scc1p.un.ethernet.iaddr3 = 0;
	m360.scc1p.un.ethernet.iaddr4 = 0;

	/*
	 * Set up receive buffer descriptors
	 */
	for (i = 0 ; i < sc->rxBdCount ; i++)
		(sc->rxBdBase + i)->status = 0;

	/*
	 * Set up transmit buffer descriptors
	 */
	for (i = 0 ; i < sc->txBdCount ; i++) {
		(sc->txBdBase + i)->status = 0;
		sc->txMbuf[i] = NULL;
	}
	sc->txBdHead = sc->txBdTail = 0;
	sc->txBdActiveCount = 0;

	/*
	 * Clear any outstanding events
	 */
	m360.scc1.scce = 0xFFFF;

	/*
	 * Set up interrupts
	 */
	status = rtems_interrupt_catch (m360Enet_interrupt_handler,
						(m360.cicr & 0xE0) | 0x1E,
						&old_handler);
	if (status != RTEMS_SUCCESSFUL)
		rtems_panic ("Can't attach M360 SCC1 interrupt handler: %s\n",
						rtems_status_text (status));
	m360.scc1.sccm = 0;	/* No interrupts unmasked till necessary */
	m360.cimr |= (1UL << 30);	/* Enable SCC1 interrupt */

	/*
	 * Set up General SCC Mode Register
	 * Ethernet configuration
	 */
	m360.scc1.gsmr_h = 0x0;
	m360.scc1.gsmr_l = 0x1088000c;

	/*
	 * Set up data synchronization register
	 * Ethernet synchronization pattern
	 */
	m360.scc1.dsr = 0xd555;

	/*
	 * Set up protocol-specific mode register
	 *	Heartbeat check
	 *	No force collision
	 *	Discard short frames
	 *	Individual address mode
	 *	Ethernet CRC
	 *	Not promisuous
	 *	Ignore/accept broadcast packets as specified
	 *	Normal backoff timer
	 *	No loopback
	 *	No input sample at end of frame
	 *	64-byte limit for late collision
	 *	Wait 22 bits before looking for start of frame delimiter
	 *	Disable full-duplex operation
	 */
	m360.scc1.psmr = 0x880A | (sc->acceptBroadcast ? 0 : 0x100);

	/*
	 * Enable the TENA (RTS1*) pin
	 */
#if (defined (M68360_ATLAS_HSB))
	m360.pbpar |= 0x1000;
	m360.pbdir |= 0x1000;
#else
	m360.pcpar |=  0x1;
	m360.pcdir &= ~0x1;
#endif
}