void setAntennaDiff( struct net_device* dev, u8* pFinalPowerIndex ) { struct r8192_priv *priv = rtllib_priv(dev); char ant_pwr_diff=0; u32 u4RegValue=0; if (priv->rf_type == RF_2T2R) { ant_pwr_diff = pFinalPowerIndex[1] - pFinalPowerIndex[0]; if(ant_pwr_diff > 7) ant_pwr_diff = 7; if(ant_pwr_diff < -8) ant_pwr_diff = -8; RT_TRACE(COMP_POWER,"Antenna Diff from RF-B to RF-A = %d (0x%x)\n", ant_pwr_diff, ant_pwr_diff&0xf); ant_pwr_diff &= 0xf; } priv->AntennaTxPwDiff[2] = 0; priv->AntennaTxPwDiff[1] = 0; priv->AntennaTxPwDiff[0] = (u8)(ant_pwr_diff); u4RegValue = (priv->AntennaTxPwDiff[2]<<8 | priv->AntennaTxPwDiff[1]<<4 | priv->AntennaTxPwDiff[0] ); rtl8192_setBBreg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue); RT_TRACE(COMP_POWER,"Write BCD-Diff(0x%x) = 0x%x\n", rFPGA0_TxGainStage, u4RegValue); }
extern void PHY_RF6052SetCckTxPower(struct net_device* dev, u8 powerlevel) { struct r8192_priv *priv = rtllib_priv(dev); u32 TxAGC=0; bool dontIncCCKOrTurboScanOff=false; if (((priv->eeprom_version >= 2) && (priv->TxPwrSafetyFlag == 1)) || ((priv->eeprom_version >= 2) && (priv->EEPROMRegulatory != 0))) { dontIncCCKOrTurboScanOff = true; } if(rtllib_act_scanning(priv->rtllib,true) == true){ TxAGC = 0x3f; if(dontIncCCKOrTurboScanOff ) TxAGC = powerlevel; } else { TxAGC = powerlevel; if(priv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1) TxAGC = 0x10; else if(priv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2) TxAGC = 0x0; } if(TxAGC > RF6052_MAX_TX_PWR) TxAGC = RF6052_MAX_TX_PWR; rtl8192_setBBreg(dev, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC); } /* PHY_RF6052SetCckTxPower */
/*----------------------------------------------------------------------------- * Function: PHY_RF6052SetCckTxPower * * Overview: * * Input: NONE * * Output: NONE * * Return: NONE * * Revised History: * When Who Remark * 11/05/2008 MHC Simulate 8192series.. * *---------------------------------------------------------------------------*/ extern void PHY_RF6052SetCckTxPower(struct net_device* dev, u8 powerlevel) { struct r8192_priv *priv = ieee80211_priv(dev); u32 TxAGC=0; bool dontIncCCK=FALSE; //cosa pHalData->bIgnoreDiffRateTxPowerOffset = FALSE; //cosa add this for passing safe spec for lenovo. //check bandedge enable bit, if enabled, don't increase tx power index. if ((priv->eeprom_version >= 2) && (priv->TxPwrSafetyFlag == 1)) dontIncCCK = TRUE; #if 0 if( priv->bScanInProgress == TRUE) TxAGC = 0x3f; #if 0//cosa else if(piv->bDynamicTxLowPower == TRUE) //cosa 04282008 for cck long range TxAGC = 0x22; #endif else #endif TxAGC = powerlevel; //cosa add for lenovo, to pass the safety spec, don't increase power index for different rates. if(dontIncCCK) TxAGC = powerlevel; if(TxAGC > RF6052_MAX_TX_PWR) TxAGC = RF6052_MAX_TX_PWR; rtl8192_setBBreg(dev, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC); } /* PHY_RF6052SetCckTxPower */
/****************************************************************************** * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * * You should have received a copy of the GNU General Public License along with * this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA * * The full GNU General Public License is included in this distribution in the * file called LICENSE. * * Contact Information: * wlanfae <*****@*****.**> ******************************************************************************/ // **************************************************************************** // // History: // Data Who Remark // // 09/25/2008 MHC Create initial version. // 11/05/2008 MHC Add API for tw power setting. // // // ***************************************************************************/ #include "r8192U.h" #include "r8192S_rtl6052.h" #ifdef RTL8192SU #include "r8192S_hw.h" #include "r8192S_phyreg.h" #include "r8192S_phy.h" #else #include "r8192U_hw.h" #include "r819xU_phyreg.h" #include "r819xU_phy.h" #endif //---------------------------Define Local Constant---------------------------*/ // Define local structure for debug!!!!! typedef struct RF_Shadow_Compare_Map { // Shadow register value u32 Value; // Compare or not flag u8 Compare; // Record If it had ever modified unpredicted u8 ErrorOrNot; // Recorver Flag u8 Recorver; // u8 Driver_Write; }RF_SHADOW_T; //---------------------------Define Local Constant---------------------------*/ //------------------------Define global variable-----------------------------*/ //------------------------Define global variable-----------------------------*/ //---------------------Define local function prototype-----------------------*/ void phy_RF6052_Config_HardCode(struct net_device* dev); RT_STATUS phy_RF6052_Config_ParaFile(struct net_device* dev); //---------------------Define local function prototype-----------------------*/ //------------------------Define function prototype--------------------------*/ extern void RF_ChangeTxPath(struct net_device* dev, u16 DataRate); //------------------------Define function prototype--------------------------*/ //------------------------Define local variable------------------------------*/ // 2008/11/20 MH For Debug only, RF static RF_SHADOW_T RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG];// = {{0}};//FIXLZM //------------------------Define local variable------------------------------*/ //------------------------Define function prototype--------------------------*/ //----------------------------------------------------------------------------- // Function: RF_ChangeTxPath // // Overview: For RL6052, we must change some RF settign for 1T or 2T. // // Input: u16 DataRate // 0x80-8f, 0x90-9f // // Output: NONE // // Return: NONE // // Revised History: // When Who Remark // 09/25/2008 MHC Create Version 0. // Firmwaer support the utility later. // //---------------------------------------------------------------------------*/ extern void RF_ChangeTxPath(struct net_device* dev, u16 DataRate) { // We do not support gain table change inACUT now !!!! Delete later !!! #if 0//(RTL92SE_FPGA_VERIFY == 0) static u1Byte RF_Path_Type = 2; // 1 = 1T 2= 2T static u4Byte tx_gain_tbl1[6] = {0x17f50, 0x11f40, 0x0cf30, 0x08720, 0x04310, 0x00100}; static u4Byte tx_gain_tbl2[6] = {0x15ea0, 0x10e90, 0x0c680, 0x08250, 0x04040, 0x00030}; u1Byte i; if (RF_Path_Type == 2 && (DataRate&0xF) <= 0x7) { // Set TX SYNC power G2G3 loop filter PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_TXPA_G2, bMask20Bits, 0x0f000); PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_TXPA_G3, bMask20Bits, 0xeacf1); // Change TX AGC gain table for (i = 0; i < 6; i++) PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_TX_AGC, bMask20Bits, tx_gain_tbl1[i]); // Set PA to high value PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_TXPA_G2, bMask20Bits, 0x01e39); } else if (RF_Path_Type == 1 && (DataRate&0xF) >= 0x8) { // Set TX SYNC power G2G3 loop filter PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_TXPA_G2, bMask20Bits, 0x04440); PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_TXPA_G3, bMask20Bits, 0xea4f1); // Change TX AGC gain table for (i = 0; i < 6; i++) PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_TX_AGC, bMask20Bits, tx_gain_tbl2[i]); // Set PA low gain PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_TXPA_G2, bMask20Bits, 0x01e19); } #endif } // RF_ChangeTxPath */ //----------------------------------------------------------------------------- // Function: PHY_RF6052SetBandwidth() // // Overview: This function is called by SetBWModeCallback8190Pci() only // // Input: PADAPTER Adapter // WIRELESS_BANDWIDTH_E Bandwidth //20M or 40M // // Output: NONE // // Return: NONE // // Note: For RF type 0222D //---------------------------------------------------------------------------*/ void PHY_RF6052SetBandwidth(struct net_device* dev, HT_CHANNEL_WIDTH Bandwidth) //20M or 40M { struct r8192_priv *priv = rtllib_priv(dev); #ifdef RTL8192SU //YJ,test,090113 //if (IS_HARDWARE_TYPE_8192S(dev)) { switch(Bandwidth) { case HT_CHANNEL_WIDTH_20: priv->RfRegChnlVal[0] = ((priv->RfRegChnlVal[0] & 0xfffff3ff) | 0x0400); rtl8192_phy_SetRFReg(dev, RF90_PATH_A, RF_CHNLBW, bRFRegOffsetMask, priv->RfRegChnlVal[0]); break; case HT_CHANNEL_WIDTH_20_40: priv->RfRegChnlVal[0] = ((priv->RfRegChnlVal[0] & 0xfffff3ff)); rtl8192_phy_SetRFReg(dev, RF90_PATH_A, RF_CHNLBW, bRFRegOffsetMask, priv->RfRegChnlVal[0]); break; default: RT_TRACE(COMP_DBG, "PHY_SetRF6052Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth); break; } } // else #else u8 eRFPath; { for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++) { switch(Bandwidth) { case HT_CHANNEL_WIDTH_20: //PHY_SetRFReg(Adapter, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, (BIT10|BIT11), 0x01); break; case HT_CHANNEL_WIDTH_20_40: //PHY_SetRFReg(Adapter, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, (BIT10|BIT11), 0x00); break; default: RT_TRACE(COMP_DBG, "PHY_SetRF8225Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth ); break; } } } #endif } //----------------------------------------------------------------------------- // Function: PHY_RF6052SetCckTxPower // // Overview: // // Input: NONE // // Output: NONE // // Return: NONE // // Revised History: // When Who Remark // 11/05/2008 MHC Simulate 8192series.. // //---------------------------------------------------------------------------*/ extern void PHY_RF6052SetCckTxPower(struct net_device* dev, u8 powerlevel) { struct r8192_priv *priv = rtllib_priv(dev); u32 TxAGC=0; bool TurboScanOff=false; if ((priv->EEPROMVersion >= 2) && (priv->EEPROMRegulatory != 0)) TurboScanOff = true; if(priv->rtllib->scanning == 1 || priv->rtllib->be_scan_inprogress == true) TxAGC = 0x3f; else TxAGC = powerlevel; if(TurboScanOff) TxAGC = powerlevel; //cosa add for lenovo, to pass the safety spec, don't increase power index for different rates. if(priv->bIgnoreDiffRateTxPowerOffset) TxAGC = powerlevel; if(TxAGC > RF6052_MAX_TX_PWR) TxAGC = RF6052_MAX_TX_PWR; //printk("CCK PWR= %x\n", TxAGC); rtl8192_setBBreg(dev, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC); } /* PHY_RF6052SetCckTxPower */
void PHY_SetRF8256CCKTxPower(struct net_device* dev, u8 powerlevel) { u32 TxAGC=0; struct r8192_priv *priv = ieee80211_priv(dev); #ifdef RTL8190P u8 byte0, byte1; TxAGC |= ((powerlevel<<8)|powerlevel); TxAGC += priv->CCKTxPowerLevelOriginalOffset; if(priv->bDynamicTxLowPower == true //cosa 04282008 for cck long range /*pMgntInfo->bScanInProgress == TRUE*/ ) //cosa 05/22/2008 for scan { if(priv->CustomerID == RT_CID_819x_Netcore) TxAGC = 0x2222; else TxAGC += ((priv->CckPwEnl<<8)|priv->CckPwEnl); } byte0 = (u8)(TxAGC & 0xff); byte1 = (u8)((TxAGC & 0xff00)>>8); if(byte0 > 0x24) byte0 = 0x24; if(byte1 > 0x24) byte1 = 0x24; if(priv->rf_type == RF_2T4R) //Only 2T4R you have to care the Antenna Tx Power offset { // check antenna C over the max index 0x24 if(priv->RF_C_TxPwDiff > 0) { if( (byte0 + (u8)priv->RF_C_TxPwDiff) > 0x24) byte0 = 0x24 - priv->RF_C_TxPwDiff; if( (byte1 + (u8)priv->RF_C_TxPwDiff) > 0x24) byte1 = 0x24 - priv->RF_C_TxPwDiff; } } TxAGC = (byte1<<8) |byte0; write_nic_dword(dev, CCK_TXAGC, TxAGC); #else #ifdef RTL8192E TxAGC = powerlevel; if(priv->bDynamicTxLowPower == true)//cosa 04282008 for cck long range { if(priv->CustomerID == RT_CID_819x_Netcore) TxAGC = 0x22; else TxAGC += priv->CckPwEnl; } if(TxAGC > 0x24) TxAGC = 0x24; rtl8192_setBBreg(dev, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC); #endif #endif }
void PHY_SetRF8256OFDMTxPower(struct net_device* dev, u8 powerlevel) { struct r8192_priv *priv = ieee80211_priv(dev); //Joseph TxPower for 8192 testing u32 writeVal, powerBase0, powerBase1, writeVal_tmp; u8 index = 0; u16 RegOffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c}; u8 byte0, byte1, byte2, byte3; powerBase0 = powerlevel + priv->TxPowerDiff; //OFDM rates powerBase0 = (powerBase0<<24) | (powerBase0<<16) |(powerBase0<<8) |powerBase0; powerBase1 = powerlevel; //MCS rates powerBase1 = (powerBase1<<24) | (powerBase1<<16) |(powerBase1<<8) |powerBase1; for(index=0; index<6; index++) { writeVal = priv->MCSTxPowerLevelOriginalOffset[index] + ((index<2)?powerBase0:powerBase1); byte0 = (u8)(writeVal & 0x7f); byte1 = (u8)((writeVal & 0x7f00)>>8); byte2 = (u8)((writeVal & 0x7f0000)>>16); byte3 = (u8)((writeVal & 0x7f000000)>>24); if(byte0 > 0x24) // Max power index = 0x24 byte0 = 0x24; if(byte1 > 0x24) byte1 = 0x24; if(byte2 > 0x24) byte2 = 0x24; if(byte3 > 0x24) byte3 = 0x24; //for tx power track if(index == 3) { writeVal_tmp = (byte3<<24) | (byte2<<16) |(byte1<<8) |byte0; priv->Pwr_Track = writeVal_tmp; } if(priv->bDynamicTxHighPower == TRUE) //Add by Jacken 2008/03/06 { // Emily, 20080613. Set low tx power for both MCS and legacy OFDM writeVal = 0x03030303; } else { writeVal = (byte3<<24) | (byte2<<16) |(byte1<<8) |byte0; } rtl8192_setBBreg(dev, RegOffset[index], 0x7f7f7f7f, writeVal); } return; }
void PHY_SetRF8256CCKTxPower(struct net_device *dev, u8 powerlevel) { u32 TxAGC = 0; struct r8192_priv *priv = rtllib_priv(dev); TxAGC = powerlevel; if (priv->bDynamicTxLowPower == true) { if (priv->CustomerID == RT_CID_819x_Netcore) TxAGC = 0x22; else TxAGC += priv->CckPwEnl; } if (TxAGC > 0x24) TxAGC = 0x24; rtl8192_setBBreg(dev, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC); }
void PHY_SetRF8256CCKTxPower(struct r8192_priv *priv, u8 powerlevel) { u32 TxAGC=0; TxAGC = powerlevel; if(priv->bDynamicTxLowPower == true)//cosa 04282008 for cck long range { if(priv->CustomerID == RT_CID_819x_Netcore) TxAGC = 0x22; else TxAGC += priv->CckPwEnl; } if(TxAGC > 0x24) TxAGC = 0x24; rtl8192_setBBreg(priv, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC); }
void PHY_SetRF8256OFDMTxPower(struct net_device *dev, u8 powerlevel) { struct r8192_priv *priv = rtllib_priv(dev); u32 writeVal, powerBase0, powerBase1, writeVal_tmp; u8 index = 0; u16 RegOffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c}; u8 byte0, byte1, byte2, byte3; powerBase0 = powerlevel + priv->LegacyHTTxPowerDiff; powerBase0 = (powerBase0 << 24) | (powerBase0 << 16) | (powerBase0 << 8) | powerBase0; powerBase1 = powerlevel; powerBase1 = (powerBase1 << 24) | (powerBase1 << 16) | (powerBase1 << 8) | powerBase1; for (index = 0; index < 6; index++) { writeVal = (u32)(priv->MCSTxPowerLevelOriginalOffset[index] + ((index < 2) ? powerBase0 : powerBase1)); byte0 = (u8)(writeVal & 0x7f); byte1 = (u8)((writeVal & 0x7f00)>>8); byte2 = (u8)((writeVal & 0x7f0000)>>16); byte3 = (u8)((writeVal & 0x7f000000)>>24); if (byte0 > 0x24) byte0 = 0x24; if (byte1 > 0x24) byte1 = 0x24; if (byte2 > 0x24) byte2 = 0x24; if (byte3 > 0x24) byte3 = 0x24; if (index == 3) { writeVal_tmp = (byte3 << 24) | (byte2 << 16) | (byte1 << 8) | byte0; priv->Pwr_Track = writeVal_tmp; } if (priv->bDynamicTxHighPower == true) writeVal = 0x03030303; else writeVal = (byte3 << 24) | (byte2 << 16) | (byte1 << 8) | byte0; rtl8192_setBBreg(dev, RegOffset[index], 0x7f7f7f7f, writeVal); } return; }
void PHY_SetRF8256OFDMTxPower(struct r8192_priv *priv, u8 powerlevel) { u32 writeVal, powerBase0, powerBase1, writeVal_tmp; u8 index = 0; u16 RegOffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c}; u8 byte0, byte1, byte2, byte3; powerBase0 = powerlevel + priv->LegacyHTTxPowerDiff; //OFDM rates powerBase0 = (powerBase0<<24) | (powerBase0<<16) |(powerBase0<<8) |powerBase0; powerBase1 = powerlevel; //MCS rates powerBase1 = (powerBase1<<24) | (powerBase1<<16) |(powerBase1<<8) |powerBase1; for(index=0; index<6; index++) { writeVal = priv->MCSTxPowerLevelOriginalOffset[index] + ((index<2)?powerBase0:powerBase1); byte0 = (u8)(writeVal & 0x7f); byte1 = (u8)((writeVal & 0x7f00)>>8); byte2 = (u8)((writeVal & 0x7f0000)>>16); byte3 = (u8)((writeVal & 0x7f000000)>>24); if(byte0 > 0x24) // Max power index = 0x24 byte0 = 0x24; if(byte1 > 0x24) byte1 = 0x24; if(byte2 > 0x24) byte2 = 0x24; if(byte3 > 0x24) byte3 = 0x24; if(index == 3) { writeVal_tmp = (byte3<<24) | (byte2<<16) |(byte1<<8) |byte0; priv->Pwr_Track = writeVal_tmp; } if(priv->bDynamicTxHighPower == true) //Add by Jacken 2008/03/06 //when DM implement, add this { writeVal = 0x03030303; } else { writeVal = (byte3<<24) | (byte2<<16) |(byte1<<8) |byte0; } rtl8192_setBBreg(priv, RegOffset[index], 0x7f7f7f7f, writeVal); } }
void PHY_SetRF8256CCKTxPower(struct net_device* dev, u8 powerlevel) { u32 TxAGC=0; struct r8192_priv *priv = ieee80211_priv(dev); //modified by vivi, 20080109 TxAGC = powerlevel; if(priv->bDynamicTxLowPower == TRUE ) //cosa 05/22/2008 for scan { if(priv->CustomerID == RT_CID_819x_Netcore) TxAGC = 0x22; else TxAGC += priv->CckPwEnl; } if(TxAGC > 0x24) TxAGC = 0x24; rtl8192_setBBreg(dev, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC); }
void setAntennaDiff( struct net_device* dev, u8* pFinalPowerIndex ) { struct r8192_priv *priv = rtllib_priv(dev); s8 ant_pwr_diff=0; u32 u4RegValue=0; if (priv->rf_type== RF_2T2R) { ant_pwr_diff = pFinalPowerIndex[1] - pFinalPowerIndex[0]; // range is from 7~-8, index = 0x0~0xf if(ant_pwr_diff > 7) ant_pwr_diff = 7; if(ant_pwr_diff < -8) ant_pwr_diff = -8; //RTPRINT(FPHY, PHY_TXPWR, ("Antenna Diff from RF-B to RF-A = %d (0x%x)\n", // ant_pwr_diff, ant_pwr_diff&0xf)); ant_pwr_diff &= 0xf; } // Antenna TX power difference priv->AntennaTxPwDiff[2] = 0;// RF-D, don't care priv->AntennaTxPwDiff[1] = 0;// RF-C, don't care priv->AntennaTxPwDiff[0] = (u8)(ant_pwr_diff); // RF-B //RTPRINT(FPHY, PHY_TXPWR, ("Antenna Diff from RF-B to RF-A = %d (0x%x)\n", //ant_pwr_diff, pHalData->AntennaTxPwDiff[0])); u4RegValue = (priv->AntennaTxPwDiff[2]<<8 | priv->AntennaTxPwDiff[1]<<4 | priv->AntennaTxPwDiff[0] ); rtl8192_setBBreg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue); //RTPRINT(FPHY, PHY_TXPWR, ("Write BCD-Diff(0x%x) = 0x%lx\n", // rFPGA0_TxGainStage, u4RegValue)); }
/*----------------------------------------------------------------------------- * Function: PHY_RF6052SetCckTxPower * * Overview: * * Input: NONE * * Output: NONE * * Return: NONE * * Revised History: * When Who Remark * 11/05/2008 MHC Simulate 8192series.. * *---------------------------------------------------------------------------*/ extern void PHY_RF6052SetCckTxPower(struct net_device* dev, u8 powerlevel) { struct r8192_priv *priv = ieee80211_priv(dev); u32 TxAGC=0; if(priv->ieee80211->scanning == 1) TxAGC = 0x3f; else if(priv->bDynamicTxLowPower == true)//cosa 04282008 for cck long range TxAGC = 0x22; else TxAGC = powerlevel; //cosa add for lenovo, to pass the safety spec, don't increase power index for different rates. if(priv->bIgnoreDiffRateTxPowerOffset) TxAGC = powerlevel; if(TxAGC > RF6052_MAX_TX_PWR) TxAGC = RF6052_MAX_TX_PWR; //printk("CCK PWR= %x\n", TxAGC); rtl8192_setBBreg(dev, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC); } /* PHY_RF6052SetCckTxPower */
extern void PHY_RF6052SetOFDMTxPower(struct net_device* dev, u8 powerlevel) { struct r8192_priv *priv = ieee80211_priv(dev); u32 writeVal, powerBase0, powerBase1; u8 index = 0; u16 RegOffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c}; u8 byte0, byte1, byte2, byte3; u8 channel = priv->ieee80211->current_network.channel; //Legacy OFDM rates powerBase0 = powerlevel + (priv->LegacyHTTxPowerDiff & 0xf); powerBase0 = (powerBase0<<24) | (powerBase0<<16) |(powerBase0<<8) |powerBase0; //MCS rates HT OFDM powerBase1 = powerlevel; powerBase1 = (powerBase1<<24) | (powerBase1<<16) |(powerBase1<<8) |powerBase1; //printk("Legacy/HT PWR= %x/%x\n", powerBase0, powerBase1); for(index=0; index<6; index++) { // // Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate // writeVal = priv->MCSTxPowerLevelOriginalOffset[index] + ((index<2)?powerBase0:powerBase1); //printk("Index = %d Original=%x writeVal=%x\n", index, priv->MCSTxPowerLevelOriginalOffset[index], writeVal); byte0 = (u8)(writeVal & 0x7f); byte1 = (u8)((writeVal & 0x7f00)>>8); byte2 = (u8)((writeVal & 0x7f0000)>>16); byte3 = (u8)((writeVal & 0x7f000000)>>24); // Max power index = 0x3F Range = 0-0x3F if(byte0 > RF6052_MAX_TX_PWR) byte0 = RF6052_MAX_TX_PWR; if(byte1 > RF6052_MAX_TX_PWR) byte1 = RF6052_MAX_TX_PWR; if(byte2 > RF6052_MAX_TX_PWR) byte2 = RF6052_MAX_TX_PWR; if(byte3 > RF6052_MAX_TX_PWR) byte3 = RF6052_MAX_TX_PWR; // // Add description: PWDB > threshold!!!High power issue!! // We must decrease tx power !! Why is the value ??? // if(priv->bDynamicTxHighPower == true) { // For MCS rate if(index > 1) { writeVal = 0x03030303; } // For Legacy rate else { writeVal = (byte3<<24) | (byte2<<16) |(byte1<<8) |byte0; } } else { writeVal = (byte3<<24) | (byte2<<16) |(byte1<<8) |byte0; } // // Write different rate set tx power index. // rtl8192_setBBreg(dev, RegOffset[index], 0x7f7f7f7f, writeVal); } } /* PHY_RF6052SetOFDMTxPower */
static bool SetRFPowerState8190( struct net_device* dev, RT_RF_POWER_STATE eRFPowerState ) { struct r8192_priv *priv = ieee80211_priv(dev); PRT_POWER_SAVE_CONTROL pPSC = (PRT_POWER_SAVE_CONTROL)(&(priv->ieee80211->PowerSaveControl)); bool bResult = true; //u8 eRFPath; u8 i = 0, QueueID = 0; ptx_ring head=NULL,tail=NULL; if(priv->SetRFPowerStateInProgress == true) return false; RT_TRACE(COMP_POWER, "===========> SetRFPowerState8190()!\n"); priv->SetRFPowerStateInProgress = true; switch(priv->rf_chip) { case RF_8256: switch( eRFPowerState ) { case eRfOn: RT_TRACE(COMP_POWER, "SetRFPowerState8190() eRfOn !\n"); //RXTX enable control: On //for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++) // PHY_SetRFReg(Adapter, (RF90_RADIO_PATH_E)eRFPath, 0x4, 0xC00, 0x2); #ifdef RTL8190P if(priv->rf_type == RF_2T4R) { //enable RF-Chip A/B rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x1); // 0x860[4] //enable RF-Chip C/D rtl8192_setBBreg(dev, rFPGA0_XC_RFInterfaceOE, BIT4, 0x1); // 0x868[4] //analog to digital on rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0xf);// 0x88c[11:8] //digital to analog on rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x1e0, 0xf); // 0x880[8:5] //rx antenna on rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0xf);// 0xc04[3:0] //rx antenna on rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0xf);// 0xd04[3:0] //analog to digital part2 on rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x1e00, 0xf); // 0x880[12:9] } else if(priv->rf_type == RF_1T2R) //RF-C, RF-D { //enable RF-Chip C/D rtl8192_setBBreg(dev, rFPGA0_XC_RFInterfaceOE, BIT4, 0x1); // 0x868[4] //analog to digital on rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xc00, 0x3);// 0x88c[11:10] //digital to analog on rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x180, 0x3); // 0x880[8:7] //rx antenna on rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xc, 0x3);// 0xc04[3:2] //rx antenna on rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xc, 0x3);// 0xd04[3:2] //analog to digital part2 on rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x1800, 0x3); // 0x880[12:11] } #else write_nic_byte(dev, ANAPAR, 0x37);//160MHz write_nic_byte(dev, MacBlkCtrl, 0x17); // 0x403 mdelay(1); //enable clock 80/88 MHz priv->bHwRfOffAction = 0; //} // Baseband reset 2008.09.30 add write_nic_byte(dev, BB_RESET, (read_nic_byte(dev, BB_RESET)|BIT0)); //2 AFE // 2008.09.30 add rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0x20000000, 0x1); // 0x884 //analog to digital part2 on rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x3); // 0x880[6:5] //digital to analog on rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x98, 0x13); // 0x880[4:3] //analog to digital on rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf03, 0xf03);// 0x88c[9:8] //rx antenna on //PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0x3, 0x3);// 0xc04[1:0] //rx antenna on 2008.09.30 mark //PHY_SetBBReg(Adapter, rOFDM1_TRxPathEnable, 0x3, 0x3);// 0xd04[1:0] //2 RF //enable RF-Chip A/B rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x1); // 0x860[4] rtl8192_setBBreg(dev, rFPGA0_XB_RFInterfaceOE, BIT4, 0x1); // 0x864[4] #endif break; // // In current solution, RFSleep=RFOff in order to save power under 802.11 power save. // By Bruce, 2008-01-16. // case eRfSleep: case eRfOff: RT_TRACE(COMP_POWER, "SetRFPowerState8190() eRfOff/Sleep !\n"); if (pPSC->bLeisurePs) { for(QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) { switch(QueueID) { case MGNT_QUEUE: tail=priv->txmapringtail; head=priv->txmapringhead; break; case BK_QUEUE: tail=priv->txbkpringtail; head=priv->txbkpringhead; break; case BE_QUEUE: tail=priv->txbepringtail; head=priv->txbepringhead; break; case VI_QUEUE: tail=priv->txvipringtail; head=priv->txvipringhead; break; case VO_QUEUE: tail=priv->txvopringtail; head=priv->txvopringhead; break; default: tail=head=NULL; break; } if(tail == head) { //DbgPrint("QueueID = %d", QueueID); QueueID++; continue; } else { RT_TRACE(COMP_POWER, "eRf Off/Sleep: %d times BusyQueue[%d] !=0 before doze!\n", (i+1), QueueID); udelay(10); i++; } if(i >= MAX_DOZE_WAITING_TIMES_9x) { RT_TRACE(COMP_POWER, "\n\n\n TimeOut!! SetRFPowerState8190(): eRfOff: %d times BusyQueue[%d] != 0 !!!\n\n\n", MAX_DOZE_WAITING_TIMES_9x, QueueID); break; } } } #ifdef RTL8190P if(priv->rf_type == RF_2T4R) { //disable RF-Chip A/B rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0); // 0x860[4] } //disable RF-Chip C/D rtl8192_setBBreg(dev, rFPGA0_XC_RFInterfaceOE, BIT4, 0x0); // 0x868[4] //analog to digital off, for power save rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8] //digital to analog off, for power save rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x1e0, 0x0); // 0x880[8:5] //rx antenna off rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0);// 0xc04[3:0] //rx antenna off rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0);// 0xd04[3:0] //analog to digital part2 off, for power save rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x1e00, 0x0); // 0x880[12:9] #else //8192E //2 RF //disable RF-Chip A/B rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0); // 0x860[4] rtl8192_setBBreg(dev, rFPGA0_XB_RFInterfaceOE, BIT4, 0x0); // 0x864[4] //2 AFE //analog to digital off, for power save //PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8] rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf03, 0x0); // 2008.09.30 Modify //digital to analog off, for power save //PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter1, 0x18, 0x0); // 0x880[4:3] rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x98, 0x0); // 0x880 2008.09.30 Modify //rx antenna off 2008.09.30 mark //PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf, 0x0);// 0xc04[3:0] //rx antenna off 2008.09.30 mark //PHY_SetBBReg(Adapter, rOFDM1_TRxPathEnable, 0xf, 0x0);// 0xd04[3:0] //analog to digital part2 off, for power save rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0); // 0x880[6:5] // 2008.09.30 add rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0x20000000, 0x0); // 0x884 //disable clock 80/88 MHz 2008.09.30 mark //PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter1, 0x4, 0x0); // 0x880[2] //2 BB // Baseband reset 2008.09.30 add write_nic_byte(dev, BB_RESET, (read_nic_byte(dev, BB_RESET)|BIT0)); // 0x101 //MAC: off write_nic_byte(dev, MacBlkCtrl, 0x0); // 0x403 //slow down cpu/lbus clock from 160MHz to Lower write_nic_byte(dev, ANAPAR, 0x07); // 0x 17 40MHz priv->bHwRfOffAction = 0; //} #endif break; default: bResult = false; RT_TRACE(COMP_ERR, "SetRFPowerState8190(): unknow state to set: 0x%X!!!\n", eRFPowerState); break; } break; default: RT_TRACE(COMP_ERR, "SetRFPowerState8190(): Unknown RF type\n"); break; } if(bResult) { // Update current RF state variable. priv->ieee80211->eRFPowerState = eRFPowerState; switch(priv->rf_chip ) { case RF_8256: switch(priv->ieee80211->eRFPowerState) { case eRfOff: // //If Rf off reason is from IPS, Led should blink with no link, by Maddest 071015 // if(priv->ieee80211->RfOffReason==RF_CHANGE_BY_IPS ) { #ifdef TO_DO Adapter->HalFunc.LedControlHandler(Adapter,LED_CTL_NO_LINK); #endif } else { // Turn off LED if RF is not ON. #ifdef TO_DO Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_POWER_OFF); #endif } break; case eRfOn: // Turn on RF we are still linked, which might happen when // we quickly turn off and on HW RF. 2006.05.12, by rcnjko. if( priv->ieee80211->state == IEEE80211_LINKED) { #ifdef TO_DO Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_LINK); #endif } else { // Turn off LED if RF is not ON. #ifdef TO_DO Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_NO_LINK); #endif } break; default: // do nothing. break; }// Switch RF state break; default: RT_TRACE(COMP_ERR, "SetRFPowerState8190(): Unknown RF type\n"); break; }// Switch RFChipID } priv->SetRFPowerStateInProgress = false; RT_TRACE(COMP_POWER, "<=========== SetRFPowerState8190() bResult = %d!\n", bResult); return bResult; }
bool phy_RF8256_Config_ParaFile(struct net_device *dev) { u32 u4RegValue = 0; u8 eRFPath; bool rtStatus = true; struct bb_reg_definition *pPhyReg; struct r8192_priv *priv = rtllib_priv(dev); u32 RegOffSetToBeCheck = 0x3; u32 RegValueToBeCheck = 0x7f1; u32 RF3_Final_Value = 0; u8 ConstRetryTimes = 5, RetryTimes = 5; u8 ret = 0; for (eRFPath = (enum rf90_radio_path)RF90_PATH_A; eRFPath < priv->NumTotalRFPath; eRFPath++) { if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) continue; pPhyReg = &priv->PHYRegDef[eRFPath]; switch (eRFPath) { case RF90_PATH_A: case RF90_PATH_C: u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV); break; case RF90_PATH_B: case RF90_PATH_D: u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16); break; } rtl8192_setBBreg(dev, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1); rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0x1); rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path) eRFPath, 0x0, bMask12Bits, 0xbf); rtStatus = rtl8192_phy_checkBBAndRF(dev, HW90_BLOCK_RF, (enum rf90_radio_path)eRFPath); if (rtStatus != true) { RT_TRACE(COMP_ERR, "PHY_RF8256_Config():Check " "Radio[%d] Fail!!\n", eRFPath); goto phy_RF8256_Config_ParaFile_Fail; } RetryTimes = ConstRetryTimes; RF3_Final_Value = 0; switch (eRFPath) { case RF90_PATH_A: while (RF3_Final_Value != RegValueToBeCheck && RetryTimes != 0) { ret = rtl8192_phy_ConfigRFWithHeaderFile(dev, (enum rf90_radio_path)eRFPath); RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (enum rf90_radio_path)eRFPath, RegOffSetToBeCheck, bMask12Bits); RT_TRACE(COMP_RF, "RF %d %d register final " "value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value); RetryTimes--; } break; case RF90_PATH_B: while (RF3_Final_Value != RegValueToBeCheck && RetryTimes != 0) { ret = rtl8192_phy_ConfigRFWithHeaderFile(dev, (enum rf90_radio_path)eRFPath); RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (enum rf90_radio_path)eRFPath, RegOffSetToBeCheck, bMask12Bits); RT_TRACE(COMP_RF, "RF %d %d register final " "value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value); RetryTimes--; } break; case RF90_PATH_C: while (RF3_Final_Value != RegValueToBeCheck && RetryTimes != 0) { ret = rtl8192_phy_ConfigRFWithHeaderFile(dev, (enum rf90_radio_path)eRFPath); RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (enum rf90_radio_path)eRFPath, RegOffSetToBeCheck, bMask12Bits); RT_TRACE(COMP_RF, "RF %d %d register final " "value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value); RetryTimes--; } break; case RF90_PATH_D: while (RF3_Final_Value != RegValueToBeCheck && RetryTimes != 0) { ret = rtl8192_phy_ConfigRFWithHeaderFile(dev, (enum rf90_radio_path)eRFPath); RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (enum rf90_radio_path)eRFPath, RegOffSetToBeCheck, bMask12Bits); RT_TRACE(COMP_RF, "RF %d %d register final " "value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value); RetryTimes--; } break; } switch (eRFPath) { case RF90_PATH_A: case RF90_PATH_C: rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue); break; case RF90_PATH_B: case RF90_PATH_D: rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue); break; } if (ret) { RT_TRACE(COMP_ERR, "phy_RF8256_Config_ParaFile():" "Radio[%d] Fail!!", eRFPath); goto phy_RF8256_Config_ParaFile_Fail; } } RT_TRACE(COMP_PHY, "PHY Initialization Success\n") ; return true; phy_RF8256_Config_ParaFile_Fail: RT_TRACE(COMP_ERR, "PHY Initialization failed\n") ; return false; }
/*-------------------------------------------------------------------------- * Overview: Interface to config 8256 * Input: struct net_device* dev * Output: NONE * Return: NONE *---------------------------------------------------------------------------*/ void phy_RF8256_Config_ParaFile(struct net_device* dev) { u32 u4RegValue = 0; //static s1Byte szRadioAFile[] = RTL819X_PHY_RADIO_A; //static s1Byte szRadioBFile[] = RTL819X_PHY_RADIO_B; //static s1Byte szRadioCFile[] = RTL819X_PHY_RADIO_C; //static s1Byte szRadioDFile[] = RTL819X_PHY_RADIO_D; u8 eRFPath; BB_REGISTER_DEFINITION_T *pPhyReg; struct r8192_priv *priv = ieee80211_priv(dev); u32 RegOffSetToBeCheck = 0x3; u32 RegValueToBeCheck = 0x7f1; u32 RF3_Final_Value = 0; u8 ConstRetryTimes = 5, RetryTimes = 5; u8 ret = 0; //3//----------------------------------------------------------------- //3// <2> Initialize RF //3//----------------------------------------------------------------- for(eRFPath = (RF90_RADIO_PATH_E)RF90_PATH_A; eRFPath <priv->NumTotalRFPath; eRFPath++) { if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) continue; pPhyReg = &priv->PHYRegDef[eRFPath]; // Joseph test for shorten RF config // pHalData->RfReg0Value[eRFPath] = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, rGlobalCtrl, bMaskDWord); /*----Store original RFENV control type----*/ switch(eRFPath) { case RF90_PATH_A: case RF90_PATH_C: u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV); break; case RF90_PATH_B : case RF90_PATH_D: u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16); break; } /*----Set RF_ENV enable----*/ rtl8192_setBBreg(dev, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1); /*----Set RF_ENV output high----*/ rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0x1); /* Set bit number of Address and Data for RF register */ rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); // Set 0 to 4 bits for Z-serial and set 1 to 6 bits for 8258 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); // Set 0 to 12 bits for Z-serial and 8258, and set 1 to 14 bits for ??? rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E) eRFPath, 0x0, bMask12Bits, 0xbf); /*----Check RF block (for FPGA platform only)----*/ // TODO: this function should be removed on ASIC , Emily 2007.2.2 if (rtl8192_phy_checkBBAndRF(dev, HW90_BLOCK_RF, (RF90_RADIO_PATH_E)eRFPath)) { RT_TRACE(COMP_ERR, "PHY_RF8256_Config():Check Radio[%d] Fail!!\n", eRFPath); goto phy_RF8256_Config_ParaFile_Fail; } RetryTimes = ConstRetryTimes; RF3_Final_Value = 0; /*----Initialize RF fom connfiguration file----*/ switch(eRFPath) { case RF90_PATH_A: while(RF3_Final_Value!=RegValueToBeCheck && RetryTimes!=0) { ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath); RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits); RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value); RetryTimes--; } break; case RF90_PATH_B: while(RF3_Final_Value!=RegValueToBeCheck && RetryTimes!=0) { ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath); RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits); RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value); RetryTimes--; } break; case RF90_PATH_C: while(RF3_Final_Value!=RegValueToBeCheck && RetryTimes!=0) { ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath); RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits); RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value); RetryTimes--; } break; case RF90_PATH_D: while(RF3_Final_Value!=RegValueToBeCheck && RetryTimes!=0) { ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath); RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits); RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value); RetryTimes--; } break; } /*----Restore RFENV control type----*/; switch(eRFPath) { case RF90_PATH_A: case RF90_PATH_C: rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue); break; case RF90_PATH_B : case RF90_PATH_D: rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue); break; } if(ret){ RT_TRACE(COMP_ERR, "phy_RF8256_Config_ParaFile():Radio[%d] Fail!!", eRFPath); goto phy_RF8256_Config_ParaFile_Fail; } } RT_TRACE(COMP_PHY, "PHY Initialization Success\n") ; return ; phy_RF8256_Config_ParaFile_Fail: RT_TRACE(COMP_ERR, "PHY Initialization failed\n") ; return ; }
void writeOFDMPowerReg( struct net_device* dev, u8 index, u32 Value ) { struct r8192_priv *priv = rtllib_priv(dev); u16 RegOffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c}; u8 i, rfa_pwr[4]; u8 rfa_lower_bound = 0, rfa_upper_bound = 0, rf_pwr_diff = 0; u32 writeVal=Value; // // If path A and Path B coexist, we must limit Path A tx power. // Protect Path B pwr over or under flow. We need to calculate upper and // lower bound of path A tx power. // if (priv->rf_type == RF_2T2R) { rf_pwr_diff = priv->AntennaTxPwDiff[0]; //RTPRINT(FPHY, PHY_TXPWR, ("2T2R RF-B to RF-A PWR DIFF=%d\n", rf_pwr_diff)); if (rf_pwr_diff >= 8) // Diff=-8~-1 { // Prevent underflow!! rfa_lower_bound = 0x10-rf_pwr_diff; //printk("rfa_lower_bound= %d\n", rfa_lower_bound); } else if (rf_pwr_diff >= 0) // Diff = 0-7 { rfa_upper_bound = RF6052_MAX_TX_PWR-rf_pwr_diff; //printk("rfa_upper_bound= %d\n", rfa_upper_bound); } } for (i=0; i<4; i++) { rfa_pwr[i] = (u8)((writeVal & (0x7f<<(i*8)))>>(i*8)); if (rfa_pwr[i] > RF6052_MAX_TX_PWR) rfa_pwr[i] = RF6052_MAX_TX_PWR; // // If path A and Path B coexist, we must limit Path A tx power. // Protect Path B pwr over or under flow. We need to calculate upper and // lower bound of path A tx power. // if (priv->rf_type== RF_2T2R) { if (rf_pwr_diff >= 8) // Diff=-8~-1 { // Prevent underflow!! if (rfa_pwr[i] <rfa_lower_bound) { //printk("Underflow"); rfa_pwr[i] = rfa_lower_bound; } } else if (rf_pwr_diff >= 1) // Diff = 0-7 { // Prevent overflow if (rfa_pwr[i] > rfa_upper_bound) { //printk("Overflow"); rfa_pwr[i] = rfa_upper_bound; } } //printk("rfa_pwr[%d]=%x\n", i, rfa_pwr[i]); } } writeVal = (rfa_pwr[3]<<24) | (rfa_pwr[2]<<16) |(rfa_pwr[1]<<8) |rfa_pwr[0]; rtl8192_setBBreg(dev, RegOffset[index], 0x7f7f7f7f, writeVal); //printk("Set 0x%x = %08x\n",RegOffset[index], writeVal); }
static bool SetRFPowerState8190(struct r8192_priv *priv, RT_RF_POWER_STATE eRFPowerState) { PRT_POWER_SAVE_CONTROL pPSC = &priv->PowerSaveControl; bool bResult = true; if (eRFPowerState == priv->eRFPowerState && priv->bHwRfOffAction == 0) { bResult = false; goto out; } switch( eRFPowerState ) { case eRfOn: // turn on RF if ((priv->eRFPowerState == eRfOff) && RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC)) { /* * The current RF state is OFF and the RF OFF level * is halting the NIC, re-initialize the NIC. */ if (!NicIFEnableNIC(priv)) { RT_TRACE(COMP_ERR, "%s(): NicIFEnableNIC failed\n",__FUNCTION__); bResult = false; goto out; } RT_CLEAR_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC); } else { write_nic_byte(priv, ANAPAR, 0x37);//160MHz mdelay(1); //enable clock 80/88 MHz rtl8192_setBBreg(priv, rFPGA0_AnalogParameter1, 0x4, 0x1); // 0x880[2] priv->bHwRfOffAction = 0; //RF-A, RF-B //enable RF-Chip A/B rtl8192_setBBreg(priv, rFPGA0_XA_RFInterfaceOE, BIT4, 0x1); // 0x860[4] //analog to digital on rtl8192_setBBreg(priv, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8] //digital to analog on rtl8192_setBBreg(priv, rFPGA0_AnalogParameter1, 0x18, 0x3); // 0x880[4:3] //rx antenna on rtl8192_setBBreg(priv, rOFDM0_TRxPathEnable, 0x3, 0x3);// 0xc04[1:0] //rx antenna on rtl8192_setBBreg(priv, rOFDM1_TRxPathEnable, 0x3, 0x3);// 0xd04[1:0] //analog to digital part2 on rtl8192_setBBreg(priv, rFPGA0_AnalogParameter1, 0x60, 0x3); // 0x880[6:5] } break; // // In current solution, RFSleep=RFOff in order to save power under 802.11 power save. // By Bruce, 2008-01-16. // case eRfSleep: // HW setting had been configured with deeper mode. if(priv->eRFPowerState == eRfOff) break; r8192e_drain_tx_queues(priv); PHY_SetRtl8192eRfOff(priv); break; case eRfOff: // // Disconnect with Any AP or STA. // r8192e_drain_tx_queues(priv); if (pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC && !RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC)) { /* Disable all components. */ NicIFDisableNIC(priv); RT_SET_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC); } else if (!(pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC)) { /* Normal case - IPS should go to this. */ PHY_SetRtl8192eRfOff(priv); } break; default: bResult = false; RT_TRACE(COMP_ERR, "SetRFPowerState8190(): unknow state to set: 0x%X!!!\n", eRFPowerState); break; } if(bResult) { // Update current RF state variable. priv->eRFPowerState = eRFPowerState; } out: return bResult; }
static bool SetRFPowerState8190( struct net_device* dev, RT_RF_POWER_STATE eRFPowerState ) { struct r8192_priv *priv = ieee80211_priv(dev); PRT_POWER_SAVE_CONTROL pPSC = (PRT_POWER_SAVE_CONTROL)(&(priv->ieee80211->PowerSaveControl)); bool bResult = true; //u8 eRFPath; u8 i = 0, QueueID = 0; //ptx_ring head=NULL,tail=NULL; struct rtl8192_tx_ring *ring = NULL; if(priv->SetRFPowerStateInProgress == true) return false; //RT_TRACE(COMP_PS, "===========> SetRFPowerState8190()!\n"); priv->SetRFPowerStateInProgress = true; switch(priv->rf_chip) { case RF_8256: switch( eRFPowerState ) { case eRfOn: //RT_TRACE(COMP_PS, "SetRFPowerState8190() eRfOn !\n"); //RXTX enable control: On //for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++) // PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x4, 0xC00, 0x2); #ifdef RTL8190P if(priv->rf_type == RF_2T4R) { //enable RF-Chip A/B rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x1); // 0x860[4] //enable RF-Chip C/D rtl8192_setBBreg(dev, rFPGA0_XC_RFInterfaceOE, BIT4, 0x1); // 0x868[4] //analog to digital on rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0xf);// 0x88c[11:8] //digital to analog on rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x1e0, 0xf); // 0x880[8:5] //rx antenna on rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0xf);// 0xc04[3:0] //rx antenna on rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0xf);// 0xd04[3:0] //analog to digital part2 on rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x1e00, 0xf); // 0x880[12:9] } else if(priv->rf_type == RF_1T2R) //RF-C, RF-D { //enable RF-Chip C/D rtl8192_setBBreg(dev, rFPGA0_XC_RFInterfaceOE, BIT4, 0x1); // 0x868[4] //analog to digital on rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xc00, 0x3);// 0x88c[11:10] //digital to analog on rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x180, 0x3); // 0x880[8:7] //rx antenna on rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xc, 0x3);// 0xc04[3:2] //rx antenna on rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xc, 0x3);// 0xd04[3:2] //analog to digital part2 on rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x1800, 0x3); // 0x880[12:11] } else if(priv->rf_type == RF_1T1R) //RF-C { //enable RF-Chip C/D rtl8192_setBBreg(dev, rFPGA0_XC_RFInterfaceOE, BIT4, 0x1); // 0x868[4] //analog to digital on rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x400, 0x1);// 0x88c[10] //digital to analog on rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x80, 0x1); // 0x880[7] //rx antenna on rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x4, 0x1);// 0xc04[2] //rx antenna on rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x4, 0x1);// 0xd04[2] //analog to digital part2 on rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x800, 0x1); // 0x880[11] } #elif defined RTL8192E // turn on RF if((priv->ieee80211->eRFPowerState == eRfOff) && RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC)) { // The current RF state is OFF and the RF OFF level is halting the NIC, re-initialize the NIC. bool rtstatus = true; u32 InitializeCount = 3; do { InitializeCount--; priv->RegRfOff = false; rtstatus = NicIFEnableNIC(dev); }while( (rtstatus != true) &&(InitializeCount >0) ); if(rtstatus != true) { RT_TRACE(COMP_ERR,"%s():Initialize Adapter fail,return\n",__FUNCTION__); priv->SetRFPowerStateInProgress = false; return false; } RT_CLEAR_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC); } else { write_nic_byte(dev, ANAPAR, 0x37);//160MHz //write_nic_byte(dev, MacBlkCtrl, 0x17); // 0x403 mdelay(1); //enable clock 80/88 MHz rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x4, 0x1); // 0x880[2] priv->bHwRfOffAction = 0; //} //RF-A, RF-B //enable RF-Chip A/B rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x1); // 0x860[4] //analog to digital on rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8] //digital to analog on rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x3); // 0x880[4:3] //rx antenna on rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3, 0x3);// 0xc04[1:0] //rx antenna on rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x3, 0x3);// 0xd04[1:0] //analog to digital part2 on rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x3); // 0x880[6:5] // Baseband reset 2008.09.30 add //write_nic_byte(dev, BB_RESET, (read_nic_byte(dev, BB_RESET)|BIT0)); //2 AFE // 2008.09.30 add //rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0x20000000, 0x1); // 0x884 //analog to digital part2 on //rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x3); // 0x880[6:5] //digital to analog on //rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x98, 0x13); // 0x880[4:3] //analog to digital on //rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf03, 0xf03);// 0x88c[9:8] //rx antenna on //PHY_SetBBReg(dev, rOFDM0_TRxPathEnable, 0x3, 0x3);// 0xc04[1:0] //rx antenna on 2008.09.30 mark //PHY_SetBBReg(dev, rOFDM1_TRxPathEnable, 0x3, 0x3);// 0xd04[1:0] //2 RF //enable RF-Chip A/B //rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x1); // 0x860[4] //rtl8192_setBBreg(dev, rFPGA0_XB_RFInterfaceOE, BIT4, 0x1); // 0x864[4] } #endif break; // // In current solution, RFSleep=RFOff in order to save power under 802.11 power save. // By Bruce, 2008-01-16. // case eRfSleep: { // HW setting had been configured with deeper mode. if(priv->ieee80211->eRFPowerState == eRfOff) break; // Update current RF state variable. //priv->ieee80211->eRFPowerState = eRFPowerState; //if (pPSC->bLeisurePs) { for(QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) { ring = &priv->tx_ring[QueueID]; if(skb_queue_len(&ring->queue) == 0) { QueueID++; continue; } else { RT_TRACE((COMP_POWER|COMP_RF), "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 before doze!\n", (i+1), QueueID); udelay(10); i++; } if(i >= MAX_DOZE_WAITING_TIMES_9x) { RT_TRACE(COMP_POWER, "\n\n\n TimeOut!! SetRFPowerState8190(): eRfOff: %d times TcbBusyQueue[%d] != 0 !!!\n\n\n", MAX_DOZE_WAITING_TIMES_9x, QueueID); break; } } } //if(Adapter->HardwareType == HARDWARE_TYPE_RTL8190P) #ifdef RTL8190P { PHY_SetRtl8190pRfOff(dev); } //else if(Adapter->HardwareType == HARDWARE_TYPE_RTL8192E) #elif defined RTL8192E { PHY_SetRtl8192eRfOff(dev); } #endif } break; case eRfOff: //RT_TRACE(COMP_PS, "SetRFPowerState8190() eRfOff/Sleep !\n"); // Update current RF state variable. //priv->ieee80211->eRFPowerState = eRFPowerState; // // Disconnect with Any AP or STA. // for(QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) { ring = &priv->tx_ring[QueueID]; if(skb_queue_len(&ring->queue) == 0) { QueueID++; continue; } else { RT_TRACE(COMP_POWER, "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 before doze!\n", (i+1), QueueID); udelay(10); i++; } if(i >= MAX_DOZE_WAITING_TIMES_9x) { RT_TRACE(COMP_POWER, "\n\n\n SetZebraRFPowerState8185B(): eRfOff: %d times TcbBusyQueue[%d] != 0 !!!\n\n\n", MAX_DOZE_WAITING_TIMES_9x, QueueID); break; } } //if(Adapter->HardwareType == HARDWARE_TYPE_RTL8190P) #if defined RTL8190P { PHY_SetRtl8190pRfOff(dev); } //else if(Adapter->HardwareType == HARDWARE_TYPE_RTL8192E) #elif defined RTL8192E { //if(pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC && !RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC) && priv->ieee80211->RfOffReason > RF_CHANGE_BY_PS) if (pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC && !RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC)) { // Disable all components. // // Note: // NicIFSetLinkStatus is a big problem when we indicate the status to OS, // the OS(XP) will reset. But now, we cnnot find why the NIC is hard to receive // packets after RF ON. Just keep this function here and still work to find out the root couse. // By Bruce, 2009-05-01. // //NicIFSetLinkStatus( Adapter, RT_MEDIA_DISCONNECT ); //if HW radio of , need to indicate scan complete first for not be reset. //if(MgntScanInProgress(pMgntInfo)) // MgntResetScanProcess( Adapter ); // <1> Disable Interrupt //rtl8192_irq_disable(dev); // <2> Stop all timer //MgntCancelAllTimer(Adapter); // <3> Disable Adapter //NicIFHaltAdapter(Adapter, false); NicIFDisableNIC(dev); RT_SET_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC); } else if (!(pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC)) { // Normal case. // IPS should go to this. PHY_SetRtl8192eRfOff(dev); } } #else else { RT_TRACE(COMP_DBG,DBG_TRACE,("It is not 8190Pci and 8192PciE \n")); } #endif break; default: bResult = false; RT_TRACE(COMP_ERR, "SetRFPowerState8190(): unknow state to set: 0x%X!!!\n", eRFPowerState); break; } break; default: RT_TRACE(COMP_ERR, "SetRFPowerState8190(): Unknown RF type\n"); break; }
bool phy_RF8225_Config_ParaFile(struct net_device* dev) { u32 u4RegValue = 0; u8 eRFPath; bool rtStatus = true; struct r8192_priv *priv = ieee80211_priv(dev); BB_REGISTER_DEFINITION_T *pPhyReg; #if 1 for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++) { pPhyReg = &priv->PHYRegDef[eRFPath]; switch(eRFPath) { case RF90_PATH_A: case RF90_PATH_C: u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV); break; case RF90_PATH_B : case RF90_PATH_D: u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16); break; } rtl8192_setBBreg(dev, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1); rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0x1); rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); switch(eRFPath) { case RF90_PATH_A: rtStatus = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath); break; case RF90_PATH_B: rtStatus = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath); break; case RF90_PATH_C: break; case RF90_PATH_D: break; } ; switch(eRFPath) { case RF90_PATH_A: case RF90_PATH_C: rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue); break; case RF90_PATH_B : case RF90_PATH_D: rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue); break; } if(rtStatus == false){ goto phy_RF8225_Config_ParaFile_Fail; } } return rtStatus; phy_RF8225_Config_ParaFile_Fail: #endif return rtStatus; }
extern void PHY_RF6052SetOFDMTxPower(struct net_device* dev, u8 powerlevel, u8 Channel) { struct r8192_priv *priv = rtllib_priv(dev); u32 writeVal, powerBase0, powerBase1; u8 index = 0; u16 RegOffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c}; u8 rfa_pwr[4]; u8 rfa_lower_bound = 0, rfa_upper_bound = 0; u8 i; u8 rf_pwr_diff = 0, chnlGroup = 0; u8 Legacy_pwrdiff=0, HT20_pwrdiff=0; if (priv->eeprom_version < 2) powerBase0 = powerlevel + (priv->LegacyHTTxPowerDiff & 0xf); else if (priv->eeprom_version >= 2) { Legacy_pwrdiff = priv->TxPwrLegacyHtDiff[RF90_PATH_A][Channel-1]; powerBase0 = powerlevel + Legacy_pwrdiff; RT_TRACE(COMP_POWER, " [LagacyToHT40 pwr diff = %d]\n", Legacy_pwrdiff); RT_TRACE(COMP_POWER, " [OFDM power base index = 0x%x]\n", powerBase0); } powerBase0 = (powerBase0<<24) | (powerBase0<<16) |(powerBase0<<8) |powerBase0; if(priv->eeprom_version >= 2) { if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20) { HT20_pwrdiff = priv->TxPwrHt20Diff[RF90_PATH_A][Channel-1]; if (HT20_pwrdiff < 8) powerlevel += HT20_pwrdiff; else powerlevel -= (16-HT20_pwrdiff); RT_TRACE(COMP_POWER, " [HT20 to HT40 pwrdiff = %d]\n", HT20_pwrdiff); RT_TRACE(COMP_POWER, " [MCS power base index = 0x%x]\n", powerlevel); } } powerBase1 = powerlevel; powerBase1 = (powerBase1<<24) | (powerBase1<<16) |(powerBase1<<8) |powerBase1; RT_TRACE(COMP_POWER, " [Legacy/HT power index= %x/%x]\n", powerBase0, powerBase1); for(index=0; index<6; index++) { if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40) { writeVal = ((index<2)?powerBase0:powerBase1); } else { if(priv->pwrGroupCnt == 0) chnlGroup = 0; if(priv->pwrGroupCnt >= 3) { if(Channel <= 3) chnlGroup = 0; else if(Channel >= 4 && Channel <= 9) chnlGroup = 1; else if(Channel >= 10) chnlGroup = 2; if(priv->pwrGroupCnt == 4) chnlGroup ++; } else chnlGroup = 0; writeVal = priv->MCSTxPowerLevelOriginalOffset[chnlGroup][index] + ((index<2)?powerBase0:powerBase1); } RT_TRACE(COMP_POWER, "Reg 0x%x, chnlGroup = %d, Original=%x writeVal=%x\n", RegOffset[index], chnlGroup, priv->MCSTxPowerLevelOriginalOffset[chnlGroup][index], writeVal); if (priv->rf_type == RF_2T2R) { rf_pwr_diff = priv->AntennaTxPwDiff[0]; RT_TRACE(COMP_POWER, "2T2R RF-B to RF-A PWR DIFF=%d\n", rf_pwr_diff); if (rf_pwr_diff >= 8) { rfa_lower_bound = 0x10-rf_pwr_diff; RT_TRACE(COMP_POWER, "rfa_lower_bound= %d\n", rfa_lower_bound); } else if (rf_pwr_diff >= 0) { rfa_upper_bound = RF6052_MAX_TX_PWR-rf_pwr_diff; RT_TRACE(COMP_POWER, "rfa_upper_bound= %d\n", rfa_upper_bound); } } for (i= 0; i <4; i++) { rfa_pwr[i] = (u8)((writeVal & (0x7f<<(i*8)))>>(i*8)); if (rfa_pwr[i] > RF6052_MAX_TX_PWR) rfa_pwr[i] = RF6052_MAX_TX_PWR; if (priv->rf_type == RF_2T2R) { if (rf_pwr_diff >= 8) { if (rfa_pwr[i] <rfa_lower_bound) { RT_TRACE(COMP_POWER, "Underflow"); rfa_pwr[i] = rfa_lower_bound; } } else if (rf_pwr_diff >= 1) { if (rfa_pwr[i] > rfa_upper_bound) { RT_TRACE(COMP_POWER, "Overflow"); rfa_pwr[i] = rfa_upper_bound; } } RT_TRACE(COMP_POWER, "rfa_pwr[%d]=%x\n", i, rfa_pwr[i]); } } #if 1 writeVal = (rfa_pwr[3]<<24) | (rfa_pwr[2]<<16) |(rfa_pwr[1]<<8) |rfa_pwr[0]; RT_TRACE(COMP_POWER, "WritePower=%08x\n", writeVal); #else if(priv->bDynamicTxHighPower == true) { if(index > 1) { writeVal = 0x03030303; } else { writeVal = (rfa_pwr[3]<<24) | (rfa_pwr[2]<<16) |(rfa_pwr[1]<<8) |rfa_pwr[0]; } RT_TRACE(COMP_POWER, "HighPower=%08x\n", writeVal); } else { writeVal = (rfa_pwr[3]<<24) | (rfa_pwr[2]<<16) |(rfa_pwr[1]<<8) |rfa_pwr[0]; RT_TRACE(COMP_POWER, "NormalPower=%08x\n", writeVal); } #endif rtl8192_setBBreg(dev, RegOffset[index], 0x7f7f7f7f, writeVal); } } /* PHY_RF6052SetOFDMTxPower */
void PHY_SetRF8256OFDMTxPower(struct net_device* dev, u8 powerlevel) { struct r8192_priv *priv = ieee80211_priv(dev); //Joseph TxPower for 8192 testing #ifdef RTL8190P u32 TxAGC1=0, TxAGC2=0, TxAGC2_tmp = 0; u8 i, byteVal1[4], byteVal2[4], byteVal3[4]; if(priv->bDynamicTxHighPower == true) //Add by Jacken 2008/03/06 { TxAGC1 |= ((powerlevel<<24)|(powerlevel<<16)|(powerlevel<<8)|powerlevel); //for tx power track TxAGC2_tmp = TxAGC1; TxAGC1 += priv->MCSTxPowerLevelOriginalOffset[0]; TxAGC2 =0x03030303; //for tx power track TxAGC2_tmp += priv->MCSTxPowerLevelOriginalOffset[1]; } else { TxAGC1 |= ((powerlevel<<24)|(powerlevel<<16)|(powerlevel<<8)|powerlevel); TxAGC2 = TxAGC1; TxAGC1 += priv->MCSTxPowerLevelOriginalOffset[0]; TxAGC2 += priv->MCSTxPowerLevelOriginalOffset[1]; TxAGC2_tmp = TxAGC2; } for(i=0; i<4; i++) { byteVal1[i] = (u8)( (TxAGC1 & (0xff<<(i*8))) >>(i*8) ); if(byteVal1[i] > 0x24) byteVal1[i] = 0x24; byteVal2[i] = (u8)( (TxAGC2 & (0xff<<(i*8))) >>(i*8) ); if(byteVal2[i] > 0x24) byteVal2[i] = 0x24; //for tx power track byteVal3[i] = (u8)( (TxAGC2_tmp & (0xff<<(i*8))) >>(i*8) ); if(byteVal3[i] > 0x24) byteVal3[i] = 0x24; } if(priv->rf_type == RF_2T4R) //Only 2T4R you have to care the Antenna Tx Power offset { // check antenna C over the max index 0x24 if(priv->RF_C_TxPwDiff > 0) { for(i=0; i<4; i++) { if( (byteVal1[i] + (u8)priv->RF_C_TxPwDiff) > 0x24) byteVal1[i] = 0x24 - priv->RF_C_TxPwDiff; if( (byteVal2[i] + (u8)priv->RF_C_TxPwDiff) > 0x24) byteVal2[i] = 0x24 - priv->RF_C_TxPwDiff; if( (byteVal3[i] + (u8)priv->RF_C_TxPwDiff) > 0x24) byteVal3[i] = 0x24 - priv->RF_C_TxPwDiff; } } } TxAGC1 = (byteVal1[3]<<24) | (byteVal1[2]<<16) |(byteVal1[1]<<8) |byteVal1[0]; TxAGC2 = (byteVal2[3]<<24) | (byteVal2[2]<<16) |(byteVal2[1]<<8) |byteVal2[0]; //for tx power track TxAGC2_tmp = (byteVal3[3]<<24) | (byteVal3[2]<<16) |(byteVal3[1]<<8) |byteVal3[0]; priv->Pwr_Track = TxAGC2_tmp; //DbgPrint("TxAGC2_tmp = 0x%x\n", TxAGC2_tmp); //DbgPrint("TxAGC1/TxAGC2 = 0x%x/0x%x\n", TxAGC1, TxAGC2); write_nic_dword(dev, MCS_TXAGC, TxAGC1); write_nic_dword(dev, MCS_TXAGC+4, TxAGC2); #else #ifdef RTL8192E u32 writeVal, powerBase0, powerBase1, writeVal_tmp; u8 index = 0; u16 RegOffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c}; u8 byte0, byte1, byte2, byte3; powerBase0 = powerlevel + priv->LegacyHTTxPowerDiff; //OFDM rates powerBase0 = (powerBase0<<24) | (powerBase0<<16) |(powerBase0<<8) |powerBase0; powerBase1 = powerlevel; //MCS rates powerBase1 = (powerBase1<<24) | (powerBase1<<16) |(powerBase1<<8) |powerBase1; for(index=0; index<6; index++) { writeVal = priv->MCSTxPowerLevelOriginalOffset[index] + ((index<2)?powerBase0:powerBase1); byte0 = (u8)(writeVal & 0x7f); byte1 = (u8)((writeVal & 0x7f00)>>8); byte2 = (u8)((writeVal & 0x7f0000)>>16); byte3 = (u8)((writeVal & 0x7f000000)>>24); if(byte0 > 0x24) // Max power index = 0x24 byte0 = 0x24; if(byte1 > 0x24) byte1 = 0x24; if(byte2 > 0x24) byte2 = 0x24; if(byte3 > 0x24) byte3 = 0x24; if(index == 3) { writeVal_tmp = (byte3<<24) | (byte2<<16) |(byte1<<8) |byte0; priv->Pwr_Track = writeVal_tmp; } if(priv->bDynamicTxHighPower == true) //Add by Jacken 2008/03/06 //when DM implement, add this { writeVal = 0x03030303; } else { writeVal = (byte3<<24) | (byte2<<16) |(byte1<<8) |byte0; } rtl8192_setBBreg(dev, RegOffset[index], 0x7f7f7f7f, writeVal); } #endif #endif }
bool phy_RF6052_Config_ParaFile(struct net_device* dev) { u32 u4RegValue = 0; //static s1Byte szRadioAFile[] = RTL819X_PHY_RADIO_A; //static s1Byte szRadioBFile[] = RTL819X_PHY_RADIO_B; u8 eRFPath; bool rtStatus = true; struct r8192_priv *priv = ieee80211_priv(dev); BB_REGISTER_DEFINITION_T *pPhyReg; //u8 eCheckItem; //3//----------------------------------------------------------------- //3// <2> Initialize RF //3//----------------------------------------------------------------- //for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++) for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++) { pPhyReg = &priv->PHYRegDef[eRFPath]; /*----Store original RFENV control type----*/ switch(eRFPath) { case RF90_PATH_A: case RF90_PATH_C: u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV); break; case RF90_PATH_B : case RF90_PATH_D: u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16); break; } /*----Set RF_ENV enable----*/ rtl8192_setBBreg(dev, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1); /*----Set RF_ENV output high----*/ rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0x1); /* Set bit number of Address and Data for RF register */ rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); // Set 1 to 4 bits for 8255 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); // Set 0 to 12 bits for 8255 /*----Initialize RF fom connfiguration file----*/ switch(eRFPath) { case RF90_PATH_A: #if RTL8190_Download_Firmware_From_Header rtStatus= rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath); #else rtStatus = PHY_ConfigRFWithParaFile(dev, (char* )&szRadioAFile, (RF90_RADIO_PATH_E)eRFPath); #endif break; case RF90_PATH_B: #if RTL8190_Download_Firmware_From_Header rtStatus= rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath); #else if(priv->rf_type == RF_2T2R_GREEN) rtStatus = PHY_ConfigRFWithParaFile(dev, (char *)&szRadioBGMFile, (RF90_RADIO_PATH_E)eRFPath); else rtStatus = PHY_ConfigRFWithParaFile(dev, (char* )&szRadioBFile, (RF90_RADIO_PATH_E)eRFPath); #endif break; case RF90_PATH_C: break; case RF90_PATH_D: break; } /*----Restore RFENV control type----*/; switch(eRFPath) { case RF90_PATH_A: case RF90_PATH_C: rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue); break; case RF90_PATH_B : case RF90_PATH_D: rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue); break; } if(rtStatus != true){ printk("phy_RF6052_Config_ParaFile():Radio[%d] Fail!!", eRFPath); goto phy_RF6052_Config_ParaFile_Fail; } } RT_TRACE(COMP_INIT, "<---phy_RF6052_Config_ParaFile()\n"); return rtStatus; phy_RF6052_Config_ParaFile_Fail: return rtStatus; }
/*----------------------------------------------------------------------------- * Function: PHY_RF6052SetOFDMTxPower * * Overview: For legacy and HY OFDM, we must read EEPROM TX power index for * different channel and read original value in TX power register area from * 0xe00. We increase offset and original value to be correct tx pwr. * * Input: NONE * * Output: NONE * * Return: NONE * * Revised History: * When Who Remark * 11/05/2008 MHC Simulate 8192 series method. * *---------------------------------------------------------------------------*/ extern void PHY_RF6052SetOFDMTxPower(struct net_device* dev, u8 powerlevel, u8 Channel) { struct r8192_priv *priv = ieee80211_priv(dev); u32 writeVal, powerBase0, powerBase1; u8 index = 0; u16 RegOffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c}; u8 rfa_pwr[4]; u8 rfa_lower_bound = 0, rfa_upper_bound = 0; u8 i; u8 rf_pwr_diff = 0, chnlGroup = 0; u8 Legacy_pwrdiff=0, HT20_pwrdiff=0;// BandEdge_Pwrdiff=0; //cosa pHalData->bIgnoreDiffRateTxPowerOffset = FALSE; // We only care about the path A for legacy. if (priv->eeprom_version < 2) powerBase0 = powerlevel + (priv->LegacyHTTxPowerDiff & 0xf); else if (priv->eeprom_version >= 2) // Defined by SD1 Jong { // // 2009/01/21 MH Support new EEPROM format from SD3 requirement // Legacy_pwrdiff = priv->TxPwrLegacyHtDiff[RF90_PATH_A][Channel-1]; // For legacy OFDM, tx pwr always > HT OFDM pwr. We do not care Path B // legacy OFDM pwr diff. NO BB register to notify HW. powerBase0 = powerlevel + Legacy_pwrdiff; RT_TRACE(COMP_POWER, " [LagacyToHT40 pwr diff = %d]\n", Legacy_pwrdiff); RT_TRACE(COMP_POWER, " [OFDM power base index = 0x%x]\n", powerBase0); } powerBase0 = (powerBase0<<24) | (powerBase0<<16) |(powerBase0<<8) |powerBase0; //MCS rates if(priv->eeprom_version >= 2) { //Cosa add for new EEPROM content. 02102009 //Check HT20 to HT40 diff if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20) { // HT 20<->40 pwr diff HT20_pwrdiff = priv->TxPwrHt20Diff[RF90_PATH_A][Channel-1]; // Calculate Antenna pwr diff if (HT20_pwrdiff < 8) // 0~+7 powerlevel += HT20_pwrdiff; else // index8-15=-8~-1 powerlevel -= (16-HT20_pwrdiff); RT_TRACE(COMP_POWER, " [HT20 to HT40 pwrdiff = %d]\n", HT20_pwrdiff); RT_TRACE(COMP_POWER, " [MCS power base index = 0x%x]\n", powerlevel); } } powerBase1 = powerlevel; powerBase1 = (powerBase1<<24) | (powerBase1<<16) |(powerBase1<<8) |powerBase1; RT_TRACE(COMP_POWER, " [Legacy/HT power index= %x/%x]\n", powerBase0, powerBase1); for(index=0; index<6; index++) { // // Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate // //cosa add for lenovo, to pass the safety spec, don't increase power index for different rates. if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40) { writeVal = ((index<2)?powerBase0:powerBase1); //printk("40MHz, writeVal = 0x%x\n", writeVal); } else { if(priv->pwrGroupCnt > 1) { if(Channel <= 3) chnlGroup = 0; else if(Channel >= 4 && Channel <= 9) chnlGroup = 1; else if(Channel >= 10) chnlGroup = 2; } else chnlGroup = 0; writeVal = priv->MCSTxPowerLevelOriginalOffset[chnlGroup][index] + ((index<2)?powerBase0:powerBase1); //printk("20MHz, writeVal = 0x%x\n", writeVal); } RT_TRACE(COMP_POWER, "Reg 0x%x, chnlGroup = %d, Original=%x writeVal=%x\n", RegOffset[index], chnlGroup, priv->MCSTxPowerLevelOriginalOffset[chnlGroup][index], writeVal); // // If path A and Path B coexist, we must limit Path A tx power. // Protect Path B pwr over or under flow. We need to calculate upper and // lower bound of path A tx power. // if (priv->rf_type == RF_2T2R) { rf_pwr_diff = priv->AntennaTxPwDiff[0]; RT_TRACE(COMP_POWER, "2T2R RF-B to RF-A PWR DIFF=%d\n", rf_pwr_diff); if (rf_pwr_diff >= 8) // Diff=-8~-1 { // Prevent underflow!! rfa_lower_bound = 0x10-rf_pwr_diff; RT_TRACE(COMP_POWER, "rfa_lower_bound= %d\n", rfa_lower_bound); } else if (rf_pwr_diff >= 0) // Diff = 0-7 { rfa_upper_bound = RF6052_MAX_TX_PWR-rf_pwr_diff; RT_TRACE(COMP_POWER, "rfa_upper_bound= %d\n", rfa_upper_bound); } } for (i= 0; i <4; i++) { rfa_pwr[i] = (u8)((writeVal & (0x7f<<(i*8)))>>(i*8)); if (rfa_pwr[i] > RF6052_MAX_TX_PWR) rfa_pwr[i] = RF6052_MAX_TX_PWR; // // If path A and Path B coexist, we must limit Path A tx power. // Protect Path B pwr over or under flow. We need to calculate upper and // lower bound of path A tx power. // if (priv->rf_type == RF_2T2R) { if (rf_pwr_diff >= 8) // Diff=-8~-1 { // Prevent underflow!! if (rfa_pwr[i] <rfa_lower_bound) { RT_TRACE(COMP_POWER, "Underflow"); rfa_pwr[i] = rfa_lower_bound; } } else if (rf_pwr_diff >= 1) // Diff = 0-7 { // Prevent overflow if (rfa_pwr[i] > rfa_upper_bound) { RT_TRACE(COMP_POWER, "Overflow"); rfa_pwr[i] = rfa_upper_bound; } } RT_TRACE(COMP_POWER, "rfa_pwr[%d]=%x\n", i, rfa_pwr[i]); } } // // Add description: PWDB > threshold!!!High power issue!! // We must decrease tx power !! Why is the value ??? // if(priv->bDynamicTxHighPower == TRUE) { // For MCS rate if(index > 1) { writeVal = 0x03030303; } // For Legacy rate else { writeVal = (rfa_pwr[3]<<24) | (rfa_pwr[2]<<16) |(rfa_pwr[1]<<8) |rfa_pwr[0]; } RT_TRACE(COMP_POWER, "HighPower=%08x\n", writeVal); } else { writeVal = (rfa_pwr[3]<<24) | (rfa_pwr[2]<<16) |(rfa_pwr[1]<<8) |rfa_pwr[0]; RT_TRACE(COMP_POWER, "NormalPower=%08x\n", writeVal); } // // Write different rate set tx power index. // //if (DCMD_Test_Flag == 0) rtl8192_setBBreg(dev, RegOffset[index], 0x7f7f7f7f, writeVal); } } /* PHY_RF6052SetOFDMTxPower */
void writeOFDMPowerReg( struct net_device* dev, u8 index, u32 Value ) { struct r8192_priv *priv = rtllib_priv(dev); u16 RegOffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c}; u8 i, rfa_pwr[4]; u8 rfa_lower_bound = 0, rfa_upper_bound = 0, rf_pwr_diff = 0; u32 writeVal=Value; if (priv->rf_type == RF_2T2R) { rf_pwr_diff = priv->AntennaTxPwDiff[0]; if (rf_pwr_diff >= 8) { rfa_lower_bound = 0x10-rf_pwr_diff; RT_TRACE(COMP_POWER,"rfa_lower_bound= %d\n", rfa_lower_bound); } else { rfa_upper_bound = RF6052_MAX_TX_PWR-rf_pwr_diff; RT_TRACE(COMP_POWER,"rfa_upper_bound= %d\n", rfa_upper_bound); } } for (i=0; i<4; i++) { rfa_pwr[i] = (u8)((writeVal & (0x7f<<(i*8)))>>(i*8)); if (rfa_pwr[i] > RF6052_MAX_TX_PWR) rfa_pwr[i] = RF6052_MAX_TX_PWR; if (priv->rf_type == RF_2T2R) { if (rf_pwr_diff >= 8) { if (rfa_pwr[i] <rfa_lower_bound) { RT_TRACE(COMP_POWER,"Underflow"); rfa_pwr[i] = rfa_lower_bound; } } else if (rf_pwr_diff >= 1) { if (rfa_pwr[i] > rfa_upper_bound) { RT_TRACE(COMP_POWER,"Overflow"); rfa_pwr[i] = rfa_upper_bound; } } RT_TRACE(COMP_POWER,"rfa_pwr[%d]=%x\n", i, rfa_pwr[i]); } } writeVal = (rfa_pwr[3]<<24) | (rfa_pwr[2]<<16) |(rfa_pwr[1]<<8) |rfa_pwr[0]; rtl8192_setBBreg(dev, RegOffset[index], 0x7f7f7f7f, writeVal); RT_TRACE(COMP_POWER,"Set 0x%x = %08x\n",RegOffset[index], writeVal); }
extern void PHY_RF6052SetOFDMTxPower(struct net_device* dev, u8 powerlevel) { struct r8192_priv *priv = ieee80211_priv(dev); u32 writeVal, powerBase0, powerBase1; u8 index = 0; u16 RegOffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c}; //u8 byte0, byte1, byte2, byte3; u8 Channel = priv->ieee80211->current_network.channel; u8 rfa_pwr[4]; u8 rfa_lower_bound = 0, rfa_upper_bound = 0 /*, rfa_htpwr, rfa_legacypwr*/; u8 i; u8 rf_pwr_diff = 0; u8 Legacy_pwrdiff=0, HT20_pwrdiff=0, BandEdge_Pwrdiff=0; u8 ofdm_bandedge_chnl_low=0, ofdm_bandedge_chnl_high=0; // We only care about the path A for legacy. if (priv->EEPROMVersion != 2) powerBase0 = powerlevel + (priv->LegacyHTTxPowerDiff & 0xf); else if (priv->EEPROMVersion == 2) // Defined by SD1 Jong { // // 2009/01/21 MH Support new EEPROM format from SD3 requirement // Legacy_pwrdiff = priv->TxPwrLegacyHtDiff[RF90_PATH_A][Channel-1]; // For legacy OFDM, tx pwr always > HT OFDM pwr. We do not care Path B // legacy OFDM pwr diff. NO BB register to notify HW. powerBase0 = powerlevel + Legacy_pwrdiff; //RTPRINT(FPHY, PHY_TXPWR, (" [LagacyToHT40 pwr diff = %d]\n", Legacy_pwrdiff)); // Band Edge scheme is enabled for FCC mode if (priv->TxPwrbandEdgeFlag == 1/* && pHalData->ChannelPlan == 0*/) { ofdm_bandedge_chnl_low = 1; ofdm_bandedge_chnl_high = 11; BandEdge_Pwrdiff = 0; if (Channel <= ofdm_bandedge_chnl_low) BandEdge_Pwrdiff = priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_A][0]; else if (Channel >= ofdm_bandedge_chnl_high) { BandEdge_Pwrdiff = priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_A][1]; } powerBase0 -= BandEdge_Pwrdiff; if (Channel <= ofdm_bandedge_chnl_low || Channel >= ofdm_bandedge_chnl_high) { //RTPRINT(FPHY, PHY_TXPWR, (" [OFDM band-edge channel = %d, pwr diff = %d]\n", //Channel, BandEdge_Pwrdiff)); } } //RTPRINT(FPHY, PHY_TXPWR, (" [OFDM power base index = 0x%x]\n", powerBase0)); } powerBase0 = (powerBase0<<24) | (powerBase0<<16) |(powerBase0<<8) |powerBase0; //MCS rates if(priv->EEPROMVersion == 2) { //Cosa add for new EEPROM content. 02102009 //Check HT20 to HT40 diff if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20) { // HT 20<->40 pwr diff HT20_pwrdiff = priv->TxPwrHt20Diff[RF90_PATH_A][Channel-1]; // Calculate Antenna pwr diff if (HT20_pwrdiff < 8) // 0~+7 powerlevel += HT20_pwrdiff; else // index8-15=-8~-1 powerlevel -= (16-HT20_pwrdiff); //RTPRINT(FPHY, PHY_TXPWR, (" [HT20 to HT40 pwrdiff = %d]\n", HT20_pwrdiff)); //RTPRINT(FPHY, PHY_TXPWR, (" [MCS power base index = 0x%x]\n", powerlevel)); } // Band Edge scheme is enabled for FCC mode if (priv->TxPwrbandEdgeFlag == 1/* && pHalData->ChannelPlan == 0*/) { BandEdge_Pwrdiff = 0; if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40) { if (Channel <= 3) BandEdge_Pwrdiff = priv->TxPwrbandEdgeHt40[RF90_PATH_A][0]; else if (Channel >= 9) BandEdge_Pwrdiff = priv->TxPwrbandEdgeHt40[RF90_PATH_A][1]; if (Channel <= 3 || Channel >= 9) { //RTPRINT(FPHY, PHY_TXPWR, (" [HT40 band-edge channel = %d, pwr diff = %d]\n", //Channel, BandEdge_Pwrdiff)); } } else if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20) { if (Channel <= 1) BandEdge_Pwrdiff = priv->TxPwrbandEdgeHt20[RF90_PATH_A][0]; else if (Channel >= 11) BandEdge_Pwrdiff = priv->TxPwrbandEdgeHt20[RF90_PATH_A][1]; if (Channel <= 1 || Channel >= 11) { //RTPRINT(FPHY, PHY_TXPWR, (" [HT20 band-edge channel = %d, pwr diff = %d]\n", //Channel, BandEdge_Pwrdiff)); } } powerlevel -= BandEdge_Pwrdiff; //RTPRINT(FPHY, PHY_TXPWR, (" [MCS power base index = 0x%x]\n", powerlevel)); } } powerBase1 = powerlevel; powerBase1 = (powerBase1<<24) | (powerBase1<<16) |(powerBase1<<8) |powerBase1; //RTPRINT(FPHY, PHY_TXPWR, (" [Legacy/HT power index= %x/%x]\n", powerBase0, powerBase1)); for(index=0; index<6; index++) { // // Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate // //cosa add for lenovo, to pass the safety spec, don't increase power index for different rates. if(priv->bIgnoreDiffRateTxPowerOffset) writeVal = ((index<2)?powerBase0:powerBase1); else writeVal = priv->MCSTxPowerLevelOriginalOffset[index] + ((index<2)?powerBase0:powerBase1); //RTPRINT(FPHY, PHY_TXPWR, ("Reg 0x%x, Original=%x writeVal=%x\n", //RegOffset[index], priv->MCSTxPowerLevelOriginalOffset[index], writeVal)); // // If path A and Path B coexist, we must limit Path A tx power. // Protect Path B pwr over or underflow. We need to calculate upper and // lower bound of path A tx power. // if (priv->rf_type == RF_2T2R) { rf_pwr_diff = priv->AntennaTxPwDiff[0]; //RTPRINT(FPHY, PHY_TXPWR, ("2T2R RF-B to RF-A PWR DIFF=%d\n", rf_pwr_diff)); if (rf_pwr_diff >= 8) // Diff=-8~-1 { // Prevent underflow!! rfa_lower_bound = 0x10-rf_pwr_diff; //RTPRINT(FPHY, PHY_TXPWR, ("rfa_lower_bound= %d\n", rfa_lower_bound)); } else if (rf_pwr_diff >= 0) // Diff = 0-7 { rfa_upper_bound = RF6052_MAX_TX_PWR-rf_pwr_diff; //RTPRINT(FPHY, PHY_TXPWR, ("rfa_upper_bound= %d\n", rfa_upper_bound)); } } for (i= 0; i <4; i++) { rfa_pwr[i] = (u8)((writeVal & (0x7f<<(i*8)))>>(i*8)); if (rfa_pwr[i] > RF6052_MAX_TX_PWR) rfa_pwr[i] = RF6052_MAX_TX_PWR; // // If path A and Path B coexist, we must limit Path A tx power. // Protect Path B pwr under/over flow. We need to calculate upper and // lower bound of path A tx power. // if (priv->rf_type == RF_2T2R) { if (rf_pwr_diff >= 8) // Diff=-8~-1 { // Prevent underflow!! if (rfa_pwr[i] <rfa_lower_bound) { //RTPRINT(FPHY, PHY_TXPWR, ("Underflow")); rfa_pwr[i] = rfa_lower_bound; } } else if (rf_pwr_diff >= 1) // Diff = 0-7 { // Prevent overflow if (rfa_pwr[i] > rfa_upper_bound) { //RTPRINT(FPHY, PHY_TXPWR, ("Overflow")); rfa_pwr[i] = rfa_upper_bound; } } //RTPRINT(FPHY, PHY_TXPWR, ("rfa_pwr[%d]=%x\n", i, rfa_pwr[i])); } } // // Add description: PWDB > threshold!!!High power issue!! // We must decrease tx power !! Why is the value ??? // if(priv->bDynamicTxHighPower == TRUE) { // For MCS rate if(index > 1) { writeVal = 0x03030303; } // For Legacy rate else { writeVal = (rfa_pwr[3]<<24) | (rfa_pwr[2]<<16) |(rfa_pwr[1]<<8) |rfa_pwr[0]; } //RTPRINT(FPHY, PHY_TXPWR, ("HighPower=%08x\n", writeVal)); } else { writeVal = (rfa_pwr[3]<<24) | (rfa_pwr[2]<<16) |(rfa_pwr[1]<<8) |rfa_pwr[0]; //RTPRINT(FPHY, PHY_TXPWR, ("NormalPower=%08x\n", writeVal)); } // // Write different rate set tx power index. // //if (DCMD_Test_Flag == 0) rtl8192_setBBreg(dev, RegOffset[index], 0x7f7f7f7f, writeVal); } } /* PHY_RF6052SetOFDMTxPower */
bool phy_RF6052_Config_ParaFile(struct net_device* dev) { u32 u4RegValue = 0; u8 eRFPath; bool rtStatus = true; struct r8192_priv *priv = rtllib_priv(dev); BB_REGISTER_DEFINITION_T *pPhyReg; for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++) { pPhyReg = &priv->PHYRegDef[eRFPath]; switch(eRFPath) { case RF90_PATH_A: case RF90_PATH_C: u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV); break; case RF90_PATH_B : case RF90_PATH_D: u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16); break; } rtl8192_setBBreg(dev, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1); rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0x1); rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); switch(eRFPath) { case RF90_PATH_A: #if RTL8190_Download_Firmware_From_Header rtStatus= rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath); #else rtStatus = PHY_ConfigRFWithParaFile(dev, (char* )&szRadioAFile, (RF90_RADIO_PATH_E)eRFPath); #endif break; case RF90_PATH_B: #if RTL8190_Download_Firmware_From_Header rtStatus= rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath); #else if(priv->rf_type == RF_2T2R_GREEN) rtStatus = PHY_ConfigRFWithParaFile(dev, (char *)&szRadioBGMFile, (RF90_RADIO_PATH_E)eRFPath); else rtStatus = PHY_ConfigRFWithParaFile(dev, (char* )&szRadioBFile, (RF90_RADIO_PATH_E)eRFPath); #endif break; case RF90_PATH_C: break; case RF90_PATH_D: break; } switch(eRFPath) { case RF90_PATH_A: case RF90_PATH_C: rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue); break; case RF90_PATH_B : case RF90_PATH_D: rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue); break; } if(rtStatus != true){ printk("phy_RF6052_Config_ParaFile():Radio[%d] Fail!!", eRFPath); goto phy_RF6052_Config_ParaFile_Fail; } } RT_TRACE(COMP_INIT, "<---phy_RF6052_Config_ParaFile()\n"); return rtStatus; phy_RF6052_Config_ParaFile_Fail: return rtStatus; }