static u32 _rtl92e_phy_rf_fw_read(struct net_device *dev,
enum rf90_radio_path eRFPath, u32 Offset)
{
u32 Data = 0;
u8 time = 0;
Data |= ((Offset & 0xFF) << 12);
Data |= ((eRFPath & 0x3) << 20);
Data |= 0x80000000;
while (rtl92e_readl(dev, QPNR) & 0x80000000) {
if (time++ < 100)
udelay(10);
else
break;
}
rtl92e_writel(dev, QPNR, Data);
while (rtl92e_readl(dev, QPNR) & 0x80000000) {
if (time++ < 100)
udelay(10);
else
return 0;
}
return rtl92e_readl(dev, RF_DATA);
}
static bool _rtl92e_bb_config_para_file(struct net_device *dev)
{
struct r8192_priv *priv = rtllib_priv(dev);
bool rtStatus = true;
u8 bRegValue = 0, eCheckItem = 0;
u32 dwRegValue = 0;
bRegValue = rtl92e_readb(dev, BB_GLOBAL_RESET);
rtl92e_writeb(dev, BB_GLOBAL_RESET, (bRegValue|BB_GLOBAL_RESET_BIT));
dwRegValue = rtl92e_readl(dev, CPU_GEN);
rtl92e_writel(dev, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST)));
for (eCheckItem = (enum hw90_block)HW90_BLOCK_PHY0;
eCheckItem <= HW90_BLOCK_PHY1; eCheckItem++) {
rtStatus = rtl92e_check_bb_and_rf(dev,
(enum hw90_block)eCheckItem,
(enum rf90_radio_path)0);
if (!rtStatus) {
RT_TRACE((COMP_ERR | COMP_PHY),
"rtl92e_config_rf():Check PHY%d Fail!!\n",
eCheckItem-1);
return rtStatus;
}
}
rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0);
_rtl92e_phy_config_bb(dev, BaseBand_Config_PHY_REG);
dwRegValue = rtl92e_readl(dev, CPU_GEN);
rtl92e_writel(dev, CPU_GEN, (dwRegValue|CPU_GEN_BB_RST));
_rtl92e_phy_config_bb(dev, BaseBand_Config_AGC_TAB);
if (priv->IC_Cut > VERSION_8190_BD) {
if (priv->rf_type == RF_2T4R)
dwRegValue = (priv->AntennaTxPwDiff[2]<<8 |
priv->AntennaTxPwDiff[1]<<4 |
priv->AntennaTxPwDiff[0]);
else
dwRegValue = 0x0;
rtl92e_set_bb_reg(dev, rFPGA0_TxGainStage,
(bXBTxAGC|bXCTxAGC|bXDTxAGC), dwRegValue);
dwRegValue = priv->CrystalCap;
rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, bXtalCap92x,
dwRegValue);
}
return rtStatus;
}
void rtl92e_get_tx_power(struct net_device *dev)
{
struct r8192_priv *priv = rtllib_priv(dev);
priv->MCSTxPowerLevelOriginalOffset[0] =
rtl92e_readl(dev, rTxAGC_Rate18_06);
priv->MCSTxPowerLevelOriginalOffset[1] =
rtl92e_readl(dev, rTxAGC_Rate54_24);
priv->MCSTxPowerLevelOriginalOffset[2] =
rtl92e_readl(dev, rTxAGC_Mcs03_Mcs00);
priv->MCSTxPowerLevelOriginalOffset[3] =
rtl92e_readl(dev, rTxAGC_Mcs07_Mcs04);
priv->MCSTxPowerLevelOriginalOffset[4] =
rtl92e_readl(dev, rTxAGC_Mcs11_Mcs08);
priv->MCSTxPowerLevelOriginalOffset[5] =
rtl92e_readl(dev, rTxAGC_Mcs15_Mcs12);
priv->DefaultInitialGain[0] = rtl92e_readb(dev, rOFDM0_XAAGCCore1);
priv->DefaultInitialGain[1] = rtl92e_readb(dev, rOFDM0_XBAGCCore1);
priv->DefaultInitialGain[2] = rtl92e_readb(dev, rOFDM0_XCAGCCore1);
priv->DefaultInitialGain[3] = rtl92e_readb(dev, rOFDM0_XDAGCCore1);
RT_TRACE(COMP_INIT,
"Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x)\n",
priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],
priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);
priv->framesync = rtl92e_readb(dev, rOFDM0_RxDetector3);
priv->framesyncC34 = rtl92e_readl(dev, rOFDM0_RxDetector2);
RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x\n",
rOFDM0_RxDetector3, priv->framesync);
priv->SifsTime = rtl92e_readw(dev, SIFS);
}
bool rtl92e_check_bb_and_rf(struct net_device *dev, enum hw90_block CheckBlock,
enum rf90_radio_path eRFPath)
{
bool ret = true;
u32 i, CheckTimes = 4, dwRegRead = 0;
u32 WriteAddr[4];
u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
WriteAddr[HW90_BLOCK_MAC] = 0x100;
WriteAddr[HW90_BLOCK_PHY0] = 0x900;
WriteAddr[HW90_BLOCK_PHY1] = 0x800;
WriteAddr[HW90_BLOCK_RF] = 0x3;
RT_TRACE(COMP_PHY, "=======>%s(), CheckBlock:%d\n", __func__,
CheckBlock);
if (CheckBlock == HW90_BLOCK_MAC) {
netdev_warn(dev, "%s(): No checks available for MAC block.\n",
__func__);
return ret;
}
for (i = 0; i < CheckTimes; i++) {
switch (CheckBlock) {
case HW90_BLOCK_PHY0:
case HW90_BLOCK_PHY1:
rtl92e_writel(dev, WriteAddr[CheckBlock],
WriteData[i]);
dwRegRead = rtl92e_readl(dev, WriteAddr[CheckBlock]);
break;
case HW90_BLOCK_RF:
WriteData[i] &= 0xfff;
rtl92e_set_rf_reg(dev, eRFPath,
WriteAddr[HW90_BLOCK_RF],
bMask12Bits, WriteData[i]);
mdelay(10);
dwRegRead = rtl92e_get_rf_reg(dev, eRFPath,
WriteAddr[HW90_BLOCK_RF],
bMaskDWord);
mdelay(10);
break;
default:
ret = false;
break;
}
if (dwRegRead != WriteData[i]) {
netdev_warn(dev, "%s(): Check failed.\n", __func__);
ret = false;
break;
}
}
return ret;
}
u32 rtl92e_get_bb_reg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask)
{
u32 OriginalValue, BitShift;
OriginalValue = rtl92e_readl(dev, dwRegAddr);
BitShift = _rtl92e_calculate_bit_shift(dwBitMask);
return (OriginalValue & dwBitMask) >> BitShift;
}
static bool _rtl92e_wait_for_fw(struct net_device *dev, u32 mask, u32 timeout)
{
unsigned long deadline = jiffies + msecs_to_jiffies(timeout);
while (time_before(jiffies, deadline)) {
if (rtl92e_readl(dev, CPU_GEN) & mask)
return true;
mdelay(2);
}
return false;
}
void rtl92e_set_bb_reg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask,
u32 dwData)
{
u32 OriginalValue, BitShift, NewValue;
if (dwBitMask != bMaskDWord) {
OriginalValue = rtl92e_readl(dev, dwRegAddr);
BitShift = _rtl92e_calculate_bit_shift(dwBitMask);
NewValue = (((OriginalValue) & (~dwBitMask)) |
(dwData << BitShift));
rtl92e_writel(dev, dwRegAddr, NewValue);
} else
rtl92e_writel(dev, dwRegAddr, dwData);
}
static void _rtl92e_phy_rf_fw_write(struct net_device *dev,
enum rf90_radio_path eRFPath, u32 Offset,
u32 Data)
{
u8 time = 0;
Data |= ((Offset & 0xFF) << 12);
Data |= ((eRFPath & 0x3) << 20);
Data |= 0x400000;
Data |= 0x80000000;
while (rtl92e_readl(dev, QPNR) & 0x80000000) {
if (time++ < 100)
udelay(10);
else
break;
}
rtl92e_writel(dev, QPNR, Data);
}
static bool _rtl92e_fw_boot_cpu(struct net_device *dev)
{
u32 CPU_status = 0;
if (!_rtl92e_wait_for_fw(dev, CPU_GEN_PUT_CODE_OK, 200)) {
netdev_err(dev, "Firmware download failed.\n");
return false;
}
netdev_dbg(dev, "Download Firmware: Put code ok!\n");
CPU_status = rtl92e_readl(dev, CPU_GEN);
rtl92e_writeb(dev, CPU_GEN,
(u8)((CPU_status|CPU_GEN_PWR_STB_CPU)&0xff));
mdelay(1);
if (!_rtl92e_wait_for_fw(dev, CPU_GEN_BOOT_RDY, 200)) {
netdev_err(dev, "Firmware boot failed.\n");
return false;
}
netdev_dbg(dev, "Download Firmware: Boot ready!\n");
return true;
}
