static int rts525a_optimize_phy(struct rtsx_pcr *pcr) { int err; err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, D3_DELINK_MODE_EN, 0x00); if (err < 0) return err; rtsx_pci_write_phy_register(pcr, _PHY_FLD0, _PHY_FLD0_CLK_REQ_20C | _PHY_FLD0_RX_IDLE_EN | _PHY_FLD0_BIT_ERR_RSTN | _PHY_FLD0_BER_COUNT | _PHY_FLD0_BER_TIMER | _PHY_FLD0_CHECK_EN); rtsx_pci_write_phy_register(pcr, _PHY_ANA03, _PHY_ANA03_TIMER_MAX | _PHY_ANA03_OOBS_DEB_EN | _PHY_CMU_DEBUG_EN); if (is_version(pcr, 0x525A, IC_VER_A)) rtsx_pci_write_phy_register(pcr, _PHY_REV0, _PHY_REV0_FILTER_OUT | _PHY_REV0_CDR_BYPASS_PFD | _PHY_REV0_CDR_RX_IDLE_BYPASS); return 0; }
static int rts5229_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage) { int err; if (voltage == OUTPUT_3V3) { err = rtsx_pci_write_register(pcr, SD30_DRIVE_SEL, 0x07, pcr->sd30_drive_sel_3v3); if (err < 0) return err; err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4FC0 | 0x24); if (err < 0) return err; } else if (voltage == OUTPUT_1V8) { err = rtsx_pci_write_register(pcr, SD30_DRIVE_SEL, 0x07, pcr->sd30_drive_sel_1v8); if (err < 0) return err; err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4C40 | 0x24); if (err < 0) return err; } else { return -EINVAL; } return 0; }
static int rts5249_optimize_phy(struct rtsx_pcr *pcr) { int err; err = rtsx_pci_write_phy_register(pcr, PHY_REG_REV, 0xFE46); if (err < 0) return err; msleep(1); return rtsx_pci_write_phy_register(pcr, PHY_BPCR, 0x05C0); }
static int rts5249_optimize_phy(struct rtsx_pcr *pcr) { int err; err = rtsx_pci_write_phy_register(pcr, PHY_REG_REV, PHY_REG_REV_RESV | PHY_REG_REV_RXIDLE_LATCHED | PHY_REG_REV_P1_EN | PHY_REG_REV_RXIDLE_EN | PHY_REG_REV_RX_PWST | PHY_REG_REV_CLKREQ_DLY_TIMER_1_0 | PHY_REG_REV_STOP_CLKRD | PHY_REG_REV_STOP_CLKWR); if (err < 0) return err; msleep(1); err = rtsx_pci_write_phy_register(pcr, PHY_BPCR, PHY_BPCR_IBRXSEL | PHY_BPCR_IBTXSEL | PHY_BPCR_IB_FILTER | PHY_BPCR_CMIRROR_EN); if (err < 0) return err; err = rtsx_pci_write_phy_register(pcr, PHY_PCR, PHY_PCR_FORCE_CODE | PHY_PCR_OOBS_CALI_50 | PHY_PCR_OOBS_VCM_08 | PHY_PCR_OOBS_SEN_90 | PHY_PCR_RSSI_EN); if (err < 0) return err; err = rtsx_pci_write_phy_register(pcr, PHY_RCR2, PHY_RCR2_EMPHASE_EN | PHY_RCR2_NADJR | PHY_RCR2_CDR_CP_10 | PHY_RCR2_CDR_SR_2 | PHY_RCR2_FREQSEL_12 | PHY_RCR2_CPADJEN | PHY_RCR2_CDR_SC_8 | PHY_RCR2_CALIB_LATE); if (err < 0) return err; err = rtsx_pci_write_phy_register(pcr, PHY_FLD4, PHY_FLD4_FLDEN_SEL | PHY_FLD4_REQ_REF | PHY_FLD4_RXAMP_OFF | PHY_FLD4_REQ_ADDA | PHY_FLD4_BER_COUNT | PHY_FLD4_BER_TIMER | PHY_FLD4_BER_CHK_EN); if (err < 0) return err; err = rtsx_pci_write_phy_register(pcr, PHY_RDR, PHY_RDR_RXDSEL_1_9); if (err < 0) return err; err = rtsx_pci_write_phy_register(pcr, PHY_RCR1, PHY_RCR1_ADP_TIME | PHY_RCR1_VCO_COARSE); if (err < 0) return err; err = rtsx_pci_write_phy_register(pcr, PHY_FLD3, PHY_FLD3_TIMER_4 | PHY_FLD3_TIMER_6 | PHY_FLD3_RXDELINK); if (err < 0) return err; return rtsx_pci_write_phy_register(pcr, PHY_TUNE, PHY_TUNE_TUNEREF_1_0 | PHY_TUNE_VBGSEL_1252 | PHY_TUNE_SDBUS_33 | PHY_TUNE_TUNED18 | PHY_TUNE_TUNED12); }
static int rts5209_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage) { int err; if (voltage == OUTPUT_3V3) { err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4FC0 | 0x24); if (err < 0) return err; } else if (voltage == OUTPUT_1V8) { err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4C40 | 0x24); if (err < 0) return err; } else { return -EINVAL; } return 0; }
static int rts5249_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage) { int err; u8 clk_drive, cmd_drive, dat_drive; if (voltage == OUTPUT_3V3) { err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, 0x4FC0 | 0x24); if (err < 0) return err; clk_drive = 0x99; cmd_drive = 0x99; dat_drive = 0x92; } else if (voltage == OUTPUT_1V8) { err = rtsx_pci_write_phy_register(pcr, PHY_BACR, 0x3C02); if (err < 0) return err; err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, 0x4C40 | 0x24); if (err < 0) return err; clk_drive = 0xb3; cmd_drive = 0xb3; dat_drive = 0xb3; } else { return -EINVAL; } /* set pad drive */ rtsx_pci_init_cmd(pcr); rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL, 0xFF, clk_drive); rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL, 0xFF, cmd_drive); rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL, 0xFF, dat_drive); return rtsx_pci_send_cmd(pcr, 100); }
static int rts5249_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage) { int err; if (voltage == OUTPUT_3V3) { err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, 0x4FC0 | 0x24); if (err < 0) return err; } else if (voltage == OUTPUT_1V8) { err = rtsx_pci_write_phy_register(pcr, PHY_BACR, 0x3C02); if (err < 0) return err; err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, 0x4C40 | 0x24); if (err < 0) return err; } else { return -EINVAL; } /* set pad drive */ rtsx_pci_init_cmd(pcr); rts5249_fill_driving(pcr, voltage); return rtsx_pci_send_cmd(pcr, 100); }
static int rts524a_optimize_phy(struct rtsx_pcr *pcr) { int err; err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, D3_DELINK_MODE_EN, 0x00); if (err < 0) return err; rtsx_pci_write_phy_register(pcr, PHY_PCR, PHY_PCR_FORCE_CODE | PHY_PCR_OOBS_CALI_50 | PHY_PCR_OOBS_VCM_08 | PHY_PCR_OOBS_SEN_90 | PHY_PCR_RSSI_EN); rtsx_pci_write_phy_register(pcr, PHY_SSCCR3, PHY_SSCCR3_STEP_IN | PHY_SSCCR3_CHECK_DELAY); if (is_version(pcr, 0x524A, IC_VER_A)) { rtsx_pci_write_phy_register(pcr, PHY_SSCCR3, PHY_SSCCR3_STEP_IN | PHY_SSCCR3_CHECK_DELAY); rtsx_pci_write_phy_register(pcr, PHY_SSCCR2, PHY_SSCCR2_PLL_NCODE | PHY_SSCCR2_TIME0 | PHY_SSCCR2_TIME2_WIDTH); rtsx_pci_write_phy_register(pcr, PHY_ANA1A, PHY_ANA1A_TXR_LOOPBACK | PHY_ANA1A_RXT_BIST | PHY_ANA1A_TXR_BIST | PHY_ANA1A_REV); rtsx_pci_write_phy_register(pcr, PHY_ANA1D, PHY_ANA1D_DEBUG_ADDR); rtsx_pci_write_phy_register(pcr, PHY_DIG1E, PHY_DIG1E_REV | PHY_DIG1E_D0_X_D1 | PHY_DIG1E_RX_ON_HOST | PHY_DIG1E_RCLK_REF_HOST | PHY_DIG1E_RCLK_TX_EN_KEEP | PHY_DIG1E_RCLK_TX_TERM_KEEP | PHY_DIG1E_RCLK_RX_EIDLE_ON | PHY_DIG1E_TX_TERM_KEEP | PHY_DIG1E_RX_TERM_KEEP | PHY_DIG1E_TX_EN_KEEP | PHY_DIG1E_RX_EN_KEEP); } rtsx_pci_write_phy_register(pcr, PHY_ANA08, PHY_ANA08_RX_EQ_DCGAIN | PHY_ANA08_SEL_RX_EN | PHY_ANA08_RX_EQ_VAL | PHY_ANA08_SCP | PHY_ANA08_SEL_IPI); return 0; }
static int rts5227_optimize_phy(struct rtsx_pcr *pcr) { /* Optimize RX sensitivity */ return rtsx_pci_write_phy_register(pcr, 0x00, 0xBA42); }
static int rts5209_optimize_phy(struct rtsx_pcr *pcr) { return rtsx_pci_write_phy_register(pcr, 0x00, 0xB966); }