int rtw_IOL_exec_cmd_array_sync(PADAPTER adapter, u8 *IOL_cmds, u32 cmd_num, u32 max_wating_ms) { struct xmit_frame *xmit_frame; if((xmit_frame=rtw_IOL_accquire_xmit_frame(adapter)) == NULL) return _FAIL; if(rtw_IOL_append_cmds(xmit_frame, IOL_cmds, cmd_num<<3) == _FAIL) return _FAIL; return rtw_IOL_exec_cmds_sync(adapter, xmit_frame, max_wating_ms); }
enum HAL_STATUS ODM_ReadAndConfig_MAC_REG_8188E(struct odm_dm_struct *dm_odm) { #define READ_NEXT_PAIR(v1, v2, i) do { i += 2; v1 = array[i]; v2 = array[i+1]; } while (0) u32 hex = 0; u32 i; u8 platform = dm_odm->SupportPlatform; u8 interface_val = dm_odm->SupportInterface; u8 board = dm_odm->BoardType; u32 array_len = sizeof(array_MAC_REG_8188E)/sizeof(u32); u32 *array = array_MAC_REG_8188E; bool biol = false; struct adapter *adapt = dm_odm->Adapter; struct xmit_frame *pxmit_frame = NULL; u8 bndy_cnt = 1; enum HAL_STATUS rst = HAL_STATUS_SUCCESS; hex += board; hex += interface_val << 8; hex += platform << 16; hex += 0xFF000000; biol = rtw_IOL_applied(adapt); if (biol) { pxmit_frame = rtw_IOL_accquire_xmit_frame(adapt); if (pxmit_frame == NULL) { pr_info("rtw_IOL_accquire_xmit_frame failed\n"); return HAL_STATUS_FAILURE; } } for (i = 0; i < array_len; i += 2) { u32 v1 = array[i]; u32 v2 = array[i+1]; /* This (offset, data) pair meets the condition. */ if (v1 < 0xCDCDCDCD) { if (biol) { if (rtw_IOL_cmd_boundary_handle(pxmit_frame)) bndy_cnt++; rtw_IOL_append_WB_cmd(pxmit_frame, (u16)v1, (u8)v2, 0xFF); } else { odm_ConfigMAC_8188E(dm_odm, v1, (u8)v2); } continue; } else { /* This line is the start line of branch. */ if (!Checkcondition(array[i], hex)) { /* Discard the following (offset, data) pairs. */ READ_NEXT_PAIR(v1, v2, i); while (v2 != 0xDEAD && v2 != 0xCDEF && v2 != 0xCDCD && i < array_len - 2) { READ_NEXT_PAIR(v1, v2, i); } i -= 2; /* prevent from for-loop += 2 */ } else { /* Configure matched pairs and skip to end of if-else. */ READ_NEXT_PAIR(v1, v2, i); while (v2 != 0xDEAD && v2 != 0xCDEF && v2 != 0xCDCD && i < array_len - 2) { if (biol) { if (rtw_IOL_cmd_boundary_handle(pxmit_frame)) bndy_cnt++; rtw_IOL_append_WB_cmd(pxmit_frame, (u16)v1, (u8)v2, 0xFF); } else { odm_ConfigMAC_8188E(dm_odm, v1, (u8)v2); } READ_NEXT_PAIR(v1, v2, i); } while (v2 != 0xDEAD && i < array_len - 2) READ_NEXT_PAIR(v1, v2, i); } } } if (biol) { if (!rtw_IOL_exec_cmds_sync(dm_odm->Adapter, pxmit_frame, 1000, bndy_cnt)) { pr_info("~~~ MAC IOL_exec_cmds Failed !!!\n"); rst = HAL_STATUS_FAILURE; } } return rst; }
HAL_STATUS ODM_ReadAndConfig_MP_8188E_PHY_REG_1T( IN PDM_ODM_T pDM_Odm ) { #define READ_NEXT_PAIR(v1, v2, i) do { i += 2; v1 = Array[i]; v2 = Array[i+1]; } while(0) u4Byte hex = 0; u4Byte i = 0; u2Byte count = 0; pu4Byte ptr_array = NULL; u1Byte platform = pDM_Odm->SupportPlatform; u1Byte _interface = pDM_Odm->SupportInterface; u1Byte board = pDM_Odm->BoardType; u4Byte ArrayLen = sizeof(Array_MP_8188E_PHY_REG_1T)/sizeof(u4Byte); pu4Byte Array = Array_MP_8188E_PHY_REG_1T; BOOLEAN biol = FALSE; #ifdef CONFIG_IOL_IOREG_CFG PADAPTER Adapter = pDM_Odm->Adapter; struct xmit_frame *pxmit_frame; u8 bndy_cnt=1; #ifdef CONFIG_IOL_IOREG_CFG_DBG struct cmd_cmp cmpdata[ArrayLen]; u4Byte cmpdata_idx=0; #endif #endif//#ifdef CONFIG_IOL_IOREG_CFG HAL_STATUS rst =HAL_STATUS_SUCCESS; hex += board; hex += _interface << 8; hex += platform << 16; hex += 0xFF000000; ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ReadAndConfig_MP_8188E_PHY_REG_1T, hex = 0x%X\n", hex)); #ifdef CONFIG_IOL_IOREG_CFG biol = rtw_IOL_applied(Adapter); if(biol){ if((pxmit_frame=rtw_IOL_accquire_xmit_frame(Adapter)) == NULL) { printk("rtw_IOL_accquire_xmit_frame failed\n"); return HAL_STATUS_FAILURE; } } #endif//#ifdef CONFIG_IOL_IOREG_CFG for (i = 0; i < ArrayLen; i += 2 ) { u4Byte v1 = Array[i]; u4Byte v2 = Array[i+1]; // This (offset, data) pair meets the condition. if ( v1 < 0xCDCDCDCD ) { #ifdef CONFIG_IOL_IOREG_CFG if(biol){ if(rtw_IOL_cmd_boundary_handle(pxmit_frame)) bndy_cnt++; if (v1 == 0xfe){ rtw_IOL_append_DELAY_MS_cmd(pxmit_frame,50); } else if (v1 == 0xfd){ rtw_IOL_append_DELAY_MS_cmd(pxmit_frame,5); } else if (v1 == 0xfc){ rtw_IOL_append_DELAY_MS_cmd(pxmit_frame,1); } else if (v1 == 0xfb){ rtw_IOL_append_DELAY_US_cmd(pxmit_frame,50); } else if (v1 == 0xfa){ rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 5); } else if (v1 == 0xf9){ rtw_IOL_append_DELAY_US_cmd(pxmit_frame,1); } else{ if (v1 == 0xa24) pDM_Odm->RFCalibrateInfo.RegA24 = v2; rtw_IOL_append_WD_cmd(pxmit_frame,(u2Byte)v1, v2,bMaskDWord); #ifdef CONFIG_IOL_IOREG_CFG_DBG cmpdata[cmpdata_idx].addr = v1; cmpdata[cmpdata_idx].value= v2; cmpdata_idx++; #endif } } else #endif //#ifdef CONFIG_IOL_IOREG_CFG { odm_ConfigBB_PHY_8188E(pDM_Odm, v1, bMaskDWord, v2); } continue; } else { // This line is the start line of branch. if ( !CheckCondition(Array[i], hex) ) { // Discard the following (offset, data) pairs. READ_NEXT_PAIR(v1, v2, i); while (v2 != 0xDEAD && v2 != 0xCDEF && v2 != 0xCDCD && i < ArrayLen -2) { READ_NEXT_PAIR(v1, v2, i); } i -= 2; // prevent from for-loop += 2 } else // Configure matched pairs and skip to end of if-else. { READ_NEXT_PAIR(v1, v2, i); while (v2 != 0xDEAD && v2 != 0xCDEF && v2 != 0xCDCD && i < ArrayLen -2) { #ifdef CONFIG_IOL_IOREG_CFG if(biol){ if(rtw_IOL_cmd_boundary_handle(pxmit_frame)) bndy_cnt++; if (v1 == 0xfe){ rtw_IOL_append_DELAY_MS_cmd(pxmit_frame,50); } else if (v1 == 0xfd){ rtw_IOL_append_DELAY_MS_cmd(pxmit_frame,5); } else if (v1 == 0xfc){ rtw_IOL_append_DELAY_MS_cmd(pxmit_frame,1); } else if (v1 == 0xfb){ rtw_IOL_append_DELAY_US_cmd(pxmit_frame,50); } else if (v1 == 0xfa){ rtw_IOL_append_DELAY_US_cmd(pxmit_frame,5); } else if (v1 == 0xf9){ rtw_IOL_append_DELAY_US_cmd(pxmit_frame,1); } else{ if (v1 == 0xa24) pDM_Odm->RFCalibrateInfo.RegA24 = v2; rtw_IOL_append_WD_cmd(pxmit_frame,(u2Byte)v1, v2,bMaskDWord); #ifdef CONFIG_IOL_IOREG_CFG_DBG cmpdata[cmpdata_idx].addr = v1; cmpdata[cmpdata_idx].value= v2; cmpdata_idx++; #endif } } else #endif //#ifdef CONFIG_IOL_IOREG_CFG { odm_ConfigBB_PHY_8188E(pDM_Odm, v1, bMaskDWord, v2); } READ_NEXT_PAIR(v1, v2, i); } while (v2 != 0xDEAD && i < ArrayLen -2) { READ_NEXT_PAIR(v1, v2, i); } } } } #ifdef CONFIG_IOL_IOREG_CFG if(biol){ //printk("==> %s, pktlen = %d,bndy_cnt = %d\n",__FUNCTION__,pxmit_frame->attrib.pktlen+4+32,bndy_cnt); if(rtw_IOL_exec_cmds_sync(pDM_Odm->Adapter, pxmit_frame, 1000, bndy_cnt)) { #ifdef CONFIG_IOL_IOREG_CFG_DBG printk("~~~ %s IOL_exec_cmds Success !!! \n",__FUNCTION__); { u4Byte idx; u4Byte cdata; printk(" %s data compare => array_len:%d \n",__FUNCTION__,cmpdata_idx); printk("### %s data compared !!###\n",__FUNCTION__); for(idx=0;idx< cmpdata_idx;idx++) { cdata = ODM_Read4Byte(pDM_Odm, cmpdata[idx].addr); if(cdata != cmpdata[idx].value){ printk(" addr:0x%04x, data:(0x%02x : 0x%02x) \n", cmpdata[idx].addr,cmpdata[idx].value,cdata); rst = HAL_STATUS_FAILURE; } } printk("### %s data compared !!###\n",__FUNCTION__); //if(rst == HAL_STATUS_FAILURE) {//dump data from TX packet buffer rtw_IOL_cmd_tx_pkt_buf_dump(pDM_Odm->Adapter,pxmit_frame->attrib.pktlen+32); } } #endif //CONFIG_IOL_IOREG_CFG_DBG } else{ rst = HAL_STATUS_FAILURE; printk("~~~ IOL Config %s Failed !!! \n",__FUNCTION__); #ifdef CONFIG_IOL_IOREG_CFG_DBG { //dump data from TX packet buffer rtw_IOL_cmd_tx_pkt_buf_dump(pDM_Odm->Adapter,pxmit_frame->attrib.pktlen+32); } #endif //CONFIG_IOL_IOREG_CFG_DBG } } #endif //#ifdef CONFIG_IOL_IOREG_CFG return rst; }
HAL_STATUS ODM_ReadAndConfig_MP_8188E_AGC_TAB_1T_ICUT( IN PDM_ODM_T pDM_Odm ) { #define READ_NEXT_PAIR(v1, v2, i) do { i += 2; v1 = Array[i]; v2 = Array[i+1]; } while(0) u4Byte hex = 0; u4Byte i = 0; u2Byte count = 0; pu4Byte ptr_array = NULL; u1Byte platform = pDM_Odm->SupportPlatform; u1Byte _interface = pDM_Odm->SupportInterface; u1Byte board = pDM_Odm->BoardType; u4Byte ArrayLen = sizeof(Array_MP_8188E_AGC_TAB_1T_ICUT)/sizeof(u4Byte); pu4Byte Array = Array_MP_8188E_AGC_TAB_1T_ICUT; BOOLEAN biol = FALSE; #ifdef CONFIG_IOL_IOREG_CFG PADAPTER Adapter = pDM_Odm->Adapter; struct xmit_frame *pxmit_frame; u8 bndy_cnt=1; #endif//#ifdef CONFIG_IOL_IOREG_CFG HAL_STATUS rst =HAL_STATUS_SUCCESS; hex += board; hex += _interface << 8; hex += platform << 16; hex += 0xFF000000; ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ReadAndConfig_MP_8188E_AGC_TAB_1T_ICUT, hex = 0x%X\n", hex)); #ifdef CONFIG_IOL_IOREG_CFG biol = rtw_IOL_applied(Adapter); if(biol){ if((pxmit_frame= rtw_IOL_accquire_xmit_frame(Adapter)) == NULL){ printk("rtw_IOL_accquire_xmit_frame failed\n"); return HAL_STATUS_FAILURE; } } #endif//#ifdef CONFIG_IOL_IOREG_CFG for (i = 0; i < ArrayLen; i += 2 ) { u4Byte v1 = Array[i]; u4Byte v2 = Array[i+1]; // This (offset, data) pair meets the condition. if ( v1 < 0xCDCDCDCD ) { #ifdef CONFIG_IOL_IOREG_CFG if(biol){ if(rtw_IOL_cmd_boundary_handle(pxmit_frame)) bndy_cnt++; rtw_IOL_append_WD_cmd(pxmit_frame,(u2Byte)v1, v2,bMaskDWord); } else #endif //#ifdef CONFIG_IOL_IOREG_CFG { odm_ConfigBB_AGC_8188E(pDM_Odm, v1, bMaskDWord, v2); } continue; } else { // This line is the start line of branch. if ( !CheckCondition(Array[i], hex) ) { // Discard the following (offset, data) pairs. READ_NEXT_PAIR(v1, v2, i); while (v2 != 0xDEAD && v2 != 0xCDEF && v2 != 0xCDCD && i < ArrayLen -2) { READ_NEXT_PAIR(v1, v2, i); } i -= 2; // prevent from for-loop += 2 } else // Configure matched pairs and skip to end of if-else. { READ_NEXT_PAIR(v1, v2, i); while (v2 != 0xDEAD && v2 != 0xCDEF && v2 != 0xCDCD && i < ArrayLen -2) { #ifdef CONFIG_IOL_IOREG_CFG if(biol){ if(rtw_IOL_cmd_boundary_handle(pxmit_frame)) bndy_cnt++; rtw_IOL_append_WD_cmd(pxmit_frame,(u2Byte)v1, v2,bMaskDWord); } else #endif //#ifdef CONFIG_IOL_IOREG_CFG { odm_ConfigBB_AGC_8188E(pDM_Odm, v1, bMaskDWord, v2); } READ_NEXT_PAIR(v1, v2, i); } while (v2 != 0xDEAD && i < ArrayLen -2) { READ_NEXT_PAIR(v1, v2, i); } } } } #ifdef CONFIG_IOL_IOREG_CFG if(biol){ //printk("==> %s, pktlen = %d,bndy_cnt = %d\n",__FUNCTION__,pxmit_frame->attrib.pktlen+4+32,bndy_cnt); if(rtw_IOL_exec_cmds_sync(pDM_Odm->Adapter, pxmit_frame, 1000, bndy_cnt)) { #ifdef CONFIG_IOL_IOREG_CFG_DBG printk("~~~ %s Success !!! \n",__FUNCTION__); { //dump data from TX packet buffer rtw_IOL_cmd_tx_pkt_buf_dump(pDM_Odm->Adapter,pxmit_frame->attrib.pktlen+32); } #endif //CONFIG_IOL_IOREG_CFG_DBG } else{ printk("~~~ %s IOL_exec_cmds Failed !!! \n",__FUNCTION__); #ifdef CONFIG_IOL_IOREG_CFG_DBG { //dump data from TX packet buffer rtw_IOL_cmd_tx_pkt_buf_dump(pDM_Odm->Adapter,pxmit_frame->attrib.pktlen+32); } #endif //CONFIG_IOL_IOREG_CFG_DBG rst = HAL_STATUS_FAILURE; } } #endif //#ifdef CONFIG_IOL_IOREG_CFG return rst; }
enum HAL_STATUS ODM_ReadAndConfig_RadioA_1T_8188E(struct odm_dm_struct *pDM_Odm) { #define READ_NEXT_PAIR(v1, v2, i) do \ { i += 2; v1 = Array[i]; \ v2 = Array[i+1]; } while (0) u32 hex = 0; u32 i = 0; u8 platform = pDM_Odm->SupportPlatform; u8 interfaceValue = pDM_Odm->SupportInterface; u8 board = pDM_Odm->BoardType; u32 ArrayLen = sizeof(Array_RadioA_1T_8188E)/sizeof(u32); u32 *Array = Array_RadioA_1T_8188E; bool biol = false; struct adapter *Adapter = pDM_Odm->Adapter; struct xmit_frame *pxmit_frame = NULL; u8 bndy_cnt = 1; enum HAL_STATUS rst = HAL_STATUS_SUCCESS; hex += board; hex += interfaceValue << 8; hex += platform << 16; hex += 0xFF000000; biol = rtw_IOL_applied(Adapter); if (biol) { pxmit_frame = rtw_IOL_accquire_xmit_frame(Adapter); if (pxmit_frame == NULL) { pr_info("rtw_IOL_accquire_xmit_frame failed\n"); return HAL_STATUS_FAILURE; } } for (i = 0; i < ArrayLen; i += 2) { u32 v1 = Array[i]; u32 v2 = Array[i+1]; /* This (offset, data) pair meets the condition. */ if (v1 < 0xCDCDCDCD) { if (biol) { if (rtw_IOL_cmd_boundary_handle(pxmit_frame)) bndy_cnt++; if (v1 == 0xffe) rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 50); else if (v1 == 0xfd) rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 5); else if (v1 == 0xfc) rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 1); else if (v1 == 0xfb) rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 50); else if (v1 == 0xfa) rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 5); else if (v1 == 0xf9) rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 1); else rtw_IOL_append_WRF_cmd(pxmit_frame, ODM_RF_PATH_A, (u16)v1, v2, bRFRegOffsetMask); } else { odm_ConfigRF_RadioA_8188E(pDM_Odm, v1, v2); } continue; } else { /* This line is the start line of branch. */ if (!CheckCondition(Array[i], hex)) { /* Discard the following (offset, data) pairs. */ READ_NEXT_PAIR(v1, v2, i); while (v2 != 0xDEAD && v2 != 0xCDEF && v2 != 0xCDCD && i < ArrayLen - 2) READ_NEXT_PAIR(v1, v2, i); i -= 2; /* prevent from for-loop += 2 */ } else { /* Configure matched pairs and skip to end of if-else. */ READ_NEXT_PAIR(v1, v2, i); while (v2 != 0xDEAD && v2 != 0xCDEF && v2 != 0xCDCD && i < ArrayLen - 2) { if (biol) { if (rtw_IOL_cmd_boundary_handle(pxmit_frame)) bndy_cnt++; if (v1 == 0xffe) rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 50); else if (v1 == 0xfd) rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 5); else if (v1 == 0xfc) rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 1); else if (v1 == 0xfb) rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 50); else if (v1 == 0xfa) rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 5); else if (v1 == 0xf9) rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 1); else rtw_IOL_append_WRF_cmd(pxmit_frame, ODM_RF_PATH_A, (u16)v1, v2, bRFRegOffsetMask); } else { odm_ConfigRF_RadioA_8188E(pDM_Odm, v1, v2); } READ_NEXT_PAIR(v1, v2, i); } while (v2 != 0xDEAD && i < ArrayLen - 2) READ_NEXT_PAIR(v1, v2, i); } } } if (biol) { if (!rtw_IOL_exec_cmds_sync(pDM_Odm->Adapter, pxmit_frame, 1000, bndy_cnt)) { rst = HAL_STATUS_FAILURE; pr_info("~~~ IOL Config %s Failed !!!\n", __func__); } } return rst; }
enum HAL_STATUS ODM_ReadAndConfig_PHY_REG_1T_8188E(struct odm_dm_struct *dm_odm) { u32 hex = 0; u32 i = 0; u8 platform = dm_odm->SupportPlatform; u8 interfaceValue = dm_odm->SupportInterface; u8 board = dm_odm->BoardType; u32 arraylen = sizeof(array_phy_reg_1t_8188e)/sizeof(u32); u32 *array = array_phy_reg_1t_8188e; bool biol = false; struct adapter *adapter = dm_odm->Adapter; struct xmit_frame *pxmit_frame = NULL; u8 bndy_cnt = 1; enum HAL_STATUS rst = HAL_STATUS_SUCCESS; hex += board; hex += interfaceValue << 8; hex += platform << 16; hex += 0xFF000000; biol = rtw_IOL_applied(adapter); if (biol) { pxmit_frame = rtw_IOL_accquire_xmit_frame(adapter); if (pxmit_frame == NULL) { pr_info("rtw_IOL_accquire_xmit_frame failed\n"); return HAL_STATUS_FAILURE; } } for (i = 0; i < arraylen; i += 2) { u32 v1 = array[i]; u32 v2 = array[i+1]; /* This (offset, data) pair meets the condition. */ if (v1 < 0xCDCDCDCD) { if (biol) { if (rtw_IOL_cmd_boundary_handle(pxmit_frame)) bndy_cnt++; if (v1 == 0xfe) { rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 50); } else if (v1 == 0xfd) { rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 5); } else if (v1 == 0xfc) { rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 1); } else if (v1 == 0xfb) { rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 50); } else if (v1 == 0xfa) { rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 5); } else if (v1 == 0xf9) { rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 1); } else { if (v1 == 0xa24) dm_odm->RFCalibrateInfo.RegA24 = v2; rtw_IOL_append_WD_cmd(pxmit_frame, (u16)v1, v2, bMaskDWord); } } else { odm_ConfigBB_PHY_8188E(dm_odm, v1, bMaskDWord, v2); } continue; } else { /* This line is the start line of branch. */ if (!CheckCondition(array[i], hex)) { /* Discard the following (offset, data) pairs. */ read_next_pair(array, v1, v2, i); while (v2 != 0xDEAD && v2 != 0xCDEF && v2 != 0xCDCD && i < arraylen - 2) read_next_pair(array, v1, v2, i); i -= 2; /* prevent from for-loop += 2 */ } else { /* Configure matched pairs and skip to end of if-else. */ read_next_pair(array, v1, v2, i); while (v2 != 0xDEAD && v2 != 0xCDEF && v2 != 0xCDCD && i < arraylen - 2) { if (biol) { if (rtw_IOL_cmd_boundary_handle(pxmit_frame)) bndy_cnt++; if (v1 == 0xfe) { rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 50); } else if (v1 == 0xfd) { rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 5); } else if (v1 == 0xfc) { rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 1); } else if (v1 == 0xfb) { rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 50); } else if (v1 == 0xfa) { rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 5); } else if (v1 == 0xf9) { rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 1); } else{ if (v1 == 0xa24) dm_odm->RFCalibrateInfo.RegA24 = v2; rtw_IOL_append_WD_cmd(pxmit_frame, (u16)v1, v2, bMaskDWord); } } else { odm_ConfigBB_PHY_8188E(dm_odm, v1, bMaskDWord, v2); } read_next_pair(array, v1, v2, i); } while (v2 != 0xDEAD && i < arraylen - 2) read_next_pair(array, v1, v2, i); } } } if (biol) { if (!rtw_IOL_exec_cmds_sync(dm_odm->Adapter, pxmit_frame, 1000, bndy_cnt)) { rst = HAL_STATUS_FAILURE; pr_info("~~~ IOL Config %s Failed !!!\n", __func__); } } return rst; }