/** * @brief The basic entry point for board initialization. * * This is called as part of machine init (after arch init). * This is again called with stack in SRAM, so not too many * constructs possible here. * * @return void */ void board_init(void) { int in_sdram = running_in_sdram(); mux_config(); /* Dont reconfigure SDRAM while running in SDRAM! */ if (!in_sdram) sdrc_init(); }
/** * @brief The basic entry point for board initialization. * * This is called as part of machine init (after arch init). * This is again called with stack in SRAM, so not too many * constructs possible here. * * @return void */ static int omap3_evm_board_init(void) { int in_sdram = running_in_sdram(); omap3_core_init(); mux_config(); /* Dont reconfigure SDRAM while running in SDRAM! */ if (!in_sdram) sdrc_init(); return 0; }
/********************************************************** * Routine: s_init * Description: Does early system init of muxing and clocks. * - Called path is with sram stack. **********************************************************/ void s_init(void) { int in_sdram = running_in_sdram(); watchdog_init(); set_muxconf_regs(); delay(100); try_unlock_sram(); if(!in_sdram) prcm_init(); peripheral_enable(); icache_enable(); if (!in_sdram) sdrc_init(); }
/********************************************************** * Routine: s_init * Description: Does early system init of muxing and clocks. * - Called path is with SRAM stack. **********************************************************/ void s_init(void) { int i; int external_boot = 0; int in_sdram = running_in_sdram(); watchdog_init(); external_boot = (get_boot_type() == 0x1F) ? 1 : 0; /* Right now flushing at low MPU speed. Need to move after clock init */ v7_flush_dcache_all(get_device_type(), external_boot); try_unlock_memory(); if (cpu_is_3410()) { /* Lock down 6-ways in L2 cache so that effective size of L2 is 64K */ __asm__ __volatile__("mov %0, #0xFC":"=r" (i)); __asm__ __volatile__("mcr p15, 1, %0, c9, c0, 0":"=r" (i)); } #ifndef CONFIG_ICACHE_OFF icache_enable(); #endif #ifdef CONFIG_L2_OFF l2cache_disable(); #else l2cache_enable(); #endif set_muxconf_regs(); delay(100); /* Writing to AuxCR in U-boot using SMI for GP/EMU DEV */ /* Currently SMI in Kernel on ES2 devices seems to have an isse * Once that is resolved, we can postpone this config to kernel */ setup_auxcr(get_device_type(), external_boot); prcm_init(); per_clocks_enable(); }
/** * @brief The basic entry point for board initialization. * * This is called as part of machine init (after arch init). * This is again called with stack in SRAM, so not too many * constructs possible here. * * @return void */ static int beaglebone_board_init(void) { int in_sdram = running_in_sdram(); /* WDT1 is already running when the bootloader gets control * Disable it to avoid "random" resets */ __raw_writel(WDT_DISABLE_CODE1, AM33XX_WDT_REG(WSPR)); while(__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0); __raw_writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR)); while(__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0); /* Dont reconfigure SDRAM while running in SDRAM! */ if (!in_sdram) beaglebone_sram_init(); /* Enable pin mux */ am33xx_enable_uart0_pin_mux(); return 0; }
/********************************************************** * Routine: s_init * Description: Does early system init of muxing and clocks. * - Called path is with sram stack. **********************************************************/ void s_init(void) { int in_sdram = running_in_sdram(); /* u32 rev = get_cpu_rev(); unused as of now.. */ watchdog_init(); try_unlock_sram(); /* Do SRAM availability first - take care of permissions too */ set_muxconf_regs(); delay(100); if (!in_sdram){ prcm_init(); } peripheral_enable(); icache_enable(); if (!in_sdram) sdrc_init(); }
/****************************************************************************** * Routine: s_init * Description: Does early system init of muxing and clocks. * - Called path is with SRAM stack. *****************************************************************************/ void s_init(void) { int in_sdram = running_in_sdram(); watchdog_init(); try_unlock_memory(); /* Right now flushing at low MPU speed. Need to move after clock init */ v7_flush_dcache_all(get_device_type()); #ifndef CONFIG_ICACHE_OFF icache_enable(); #endif #ifdef CONFIG_L2_OFF l2cache_disable(); #else l2cache_enable(); #endif /* Writing to AuxCR in U-boot using SMI for GP DEV */ /* Currently SMI in Kernel on ES2 devices seems to have an isse * Once that is resolved, we can postpone this config to kernel */ if (get_device_type() == GP_DEVICE) setup_auxcr(); set_muxconf_regs(); delay(100); prcm_init(); per_clocks_enable(); if (!in_sdram) sdrc_init(); }
/****************************************************************************** * Routine: try_unlock_sram() * Description: If chip is GP/EMU(special) type, unlock the SRAM for * general use. *****************************************************************************/ void try_unlock_memory() { int mode; int in_sdram = running_in_sdram(); /* if GP device unlock device SRAM for general use */ /* secure code breaks for Secure/Emulation device - HS/E/T */ mode = get_device_type(); if (mode == GP_DEVICE) secure_unlock_mem(); /* If device is EMU and boot is XIP external booting * Unlock firewalls and disable L2 and put chip * out of secure world */ /* Assuming memories are unlocked by the demon who put us in SDRAM */ if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F) && (!in_sdram)) { secure_unlock_mem(); secureworld_exit(); } return; }