int usb_cpu_stop(void)
{
struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
/* may not want to do this */
writel(readl(&clk_power->CLKCON) & ~(1 << 4), &clk_power->CLKCON);
return 0;
}
static void s3c24x0_configure_device (struct usb_device_instance *device)
{
struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
struct s3c24x0_clock_power * const cpower = s3c24x0_get_base_clock_power();
/* disable EP0-4 SUBD interrupts ? */
outl(0x00, S3C24X0_UDC_USB_INT_EN_REG);
/* UPLL already configured by board-level init code */
/* configure USB pads to device mode */
gpio->MISCCR &= ~(S3C24X0_MISCCR_USBHOST|S3C24X0_MISCCR_USBSUSPND1);
/* don't disable USB clock */
cpower->CLKSLOW &= ~S3C24X0_CLKSLOW_UCLK_OFF;
/* clear interrupt registers */
inl(S3C24X0_UDC_EP_INT_REG);
inl(S3C24X0_UDC_USB_INT_REG);
outl(0xff, S3C24X0_UDC_EP_INT_REG);
outl(0xff, S3C24X0_UDC_USB_INT_REG);
/* enable USB interrupts for RESET and SUSPEND/RESUME */
outl(S3C24X0_UDC_USBINT_RESET|S3C24X0_UDC_USBINT_SUSPEND,
S3C24X0_UDC_USB_INT_EN_REG);
}
/* Start to initialize h/w stuff */
int udc_init (void)
{
struct s3c24x0_clock_power * const clk_power = s3c24x0_get_base_clock_power();
struct s3c24x0_interrupt * irq = s3c24x0_get_base_interrupt();
udc_device = NULL;
/* Set and check clock control.
* We might ought to be using the clock control API to do
* this instead of fiddling with the clock registers directly
* here.
*/
clk_power->CLKCON |= (1 << 7);
/* Print banner with device revision */
printf("USB: S3C2440 USB Deviced\n");
/*
* At this point, device is ready for configuration...
*/
outl(0x00, S3C24X0_UDC_EP_INT_EN_REG);
outl(0x00, S3C24X0_UDC_USB_INT_EN_REG);
irq->INTMSK &= ~BIT_DMA2;
irq->SRCPND &= ~BIT_DMA2;
irq_install_handler(IRQ_USBD, do_usbd_irq, (void *) IRQ_USBD);
irq_install_handler(IRQ_DMA2, do_dma2, (void *) IRQ_DMA2);
return 0;
}
static int s3cmmc_init(struct mmc *mmc)
{
struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
struct s3c24x0_sdi *sdi_regs = s3c24x0_get_base_sdi();
/* Start the clock. */
setbits_le32(&clk_power->clkcon, 1 << 9);
#if defined(CONFIG_S3C2440)
writel(S3C2440_SDICON_SDRESET, &sdi_regs->sdicon);
mdelay(10);
writel(0x7fffff, &sdi_regs->sdidtimer);
#else
writel(0xffff, &sdi_regs->sdidtimer);
#endif
writel(MMC_MAX_BLOCK_LEN, &sdi_regs->sdibsize);
writel(0x0, &sdi_regs->sdiimsk);
writel(S3C2410_SDICON_FIFORESET | S3C2410_SDICON_CLOCKTYPE,
&sdi_regs->sdicon);
mdelay(125);
return 0;
}
int usb_cpu_stop(void)
{
struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
/* may not want to do this */
writel(readl(&clk_power->clkcon) & ~USB_CEN_MASK, &clk_power->clkcon);
return 0;
}
int board_init (void)
{
struct s3c24x0_clock_power * const clk_power =
s3c24x0_get_base_clock_power();
struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
/* to reduce PLL lock time, adjust the LOCKTIME register */
clk_power->LOCKTIME = 0xFFFFFF;
/* configure MPLL */
clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
/* some delay between MPLL and UPLL */
delay (4000);
/* configure UPLL */
clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
/* some delay between MPLL and UPLL */
delay (8000);
/* set up the I/O ports */
gpio->GPACON = 0x007FFFFF;
gpio->GPBCON = 0x00044555;
gpio->GPBUP = 0x000007FF;
gpio->GPCCON = 0xAAAAAAAA;
gpio->GPCUP = 0x0000FFFF;
gpio->GPDCON = 0xAAAAAAAA;
gpio->GPDUP = 0x0000FFFF;
gpio->GPECON = 0xAAAAAAAA;
gpio->GPEUP = 0x0000FFFF;
gpio->GPFCON = 0x000055AA;
gpio->GPFUP = 0x000000FF;
gpio->GPGCON = 0xFD95FFBA;
gpio->GPGUP = 0x0000EFFF;
gpio->GPGDAT &= ~(1<<12);
gpio->GPHCON = 0x002AFAAA;
gpio->GPHUP = 0x000007FF;
/* arch number of S3C2440-Board */
gd->bd->bi_arch_number = MACH_TYPE_SMDK2440A;
/* adress of boot parameters */
gd->bd->bi_boot_params = 0x30000100;
icache_enable();
dcache_enable();
return 0;
}
int board_early_init_f(void)
{
struct s3c24x0_clock_power * const clk_power =
s3c24x0_get_base_clock_power();
struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
/* to reduce PLL lock time, adjust the LOCKTIME register */
writel(0xFFFFFF, &clk_power->locktime);
/* configure MPLL */
writel((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV,
&clk_power->mpllcon);
/* some delay between MPLL and UPLL */
pll_delay(4000);
/* configure UPLL */
writel((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV,
&clk_power->upllcon);
/* some delay between MPLL and UPLL */
pll_delay(8000);
/* set up the I/O ports */
writel(0x007FFFFF, &gpio->gpacon);
writel(0x00295551, &gpio->gpbcon);
writel(0x000007FE, &gpio->gpbup);
// writel(readl(&gpio->gpbdat)&0x1,&gpio->gpbdat);
writel(0xAAAAA6AA, &gpio->gpccon);
writel(readl(&gpio->gpcdat)&(~(1<<5)),&gpio->gpcdat);
writel(0x0000FFFF, &gpio->gpcup);
writel(0xAAAAAAAA, &gpio->gpdcon);
writel(0x0000FFFF, &gpio->gpdup);
writel(0xAAAAAAAA, &gpio->gpecon);
writel(0x0000FFFF, &gpio->gpeup);
writel(0x000055AA, &gpio->gpfcon);
writel(0x000000FF, &gpio->gpfup);
writel(0xFF95FFBA, &gpio->gpgcon);
writel(0x0000FFFF, &gpio->gpgup);
writel(0x002AFAAA, &gpio->gphcon);
writel(0x000007FF, &gpio->gphup);
return 0;
}
int usb_cpu_init(void)
{
struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
/*
* Set the 48 MHz UPLL clocking. Values are taken from
* "PLL value selection guide", 6-23, s3c2400_UM.pdf.
*/
writel((40 << 12) + (1 << 4) + 2, &clk_power->UPLLCON);
/* 1 = use pads related USB for USB host */
writel(readl(&gpio->MISCCR) | 0x8, &gpio->MISCCR);
/*
* Enable USB host clock.
*/
writel(readl(&clk_power->CLKCON) | (1 << 4), &clk_power->CLKCON);
return 0;
}
int usb_cpu_init_fail(void)
{
struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
writel(readl(&clk_power->CLKCON) & ~(1 << 4), &clk_power->CLKCON);
return 0;
}
int board_nand_init(struct nand_chip *nand)
{
u_int32_t cfg;
u_int8_t tacls, twrph0, twrph1;
struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
struct s3c24x0_nand *nand_reg = s3c24x0_get_base_nand();
debug("board_nand_init()\n");
writel(readl(&clk_power->clkcon) | (1 << 4), &clk_power->clkcon);
/* initialize hardware */
#if defined(CONFIG_S3C24XX_CUSTOM_NAND_TIMING)
tacls = CONFIG_S3C24XX_TACLS;
twrph0 = CONFIG_S3C24XX_TWRPH0;
twrph1 = CONFIG_S3C24XX_TWRPH1;
#else
tacls = 4;
twrph0 = 8;
twrph1 = 8;
#endif
cfg = S3C2410_NFCONF_EN;
cfg |= S3C2410_NFCONF_TACLS(tacls - 1);
cfg |= S3C2410_NFCONF_TWRPH0(twrph0 - 1);
cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1);
writel(cfg, &nand_reg->nfconf);
/* initialize nand_chip data structure */
nand->IO_ADDR_R = (void *)&nand_reg->nfdata;
nand->IO_ADDR_W = (void *)&nand_reg->nfdata;
nand->select_chip = NULL;
/* read_buf and write_buf are default */
/* read_byte and write_byte are default */
#ifdef CONFIG_NAND_SPL
nand->read_buf = nand_read_buf;
#endif
/* hwcontrol always must be implemented */
nand->cmd_ctrl = s3c24x0_hwcontrol;
nand->dev_ready = s3c24x0_dev_ready;
#ifdef CONFIG_S3C2410_NAND_HWECC
nand->ecc.hwctl = s3c24x0_nand_enable_hwecc;
nand->ecc.calculate = s3c24x0_nand_calculate_ecc;
nand->ecc.correct = s3c24x0_nand_correct_data;
nand->ecc.mode = NAND_ECC_HW;
nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
nand->ecc.strength = 1;
#else
nand->ecc.mode = NAND_ECC_SOFT;
#endif
#ifdef CONFIG_S3C2410_NAND_BBT
nand->bbt_options |= NAND_BBT_USE_FLASH;
#endif
debug("end of nand_init\n");
return 0;
}
int board_nand_init(struct nand_chip *nand)
{
#if 0
u_int32_t cfg;
u_int8_t tacls, twrph0, twrph1;
struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
struct s3c2410_nand *nand_reg = s3c2410_get_base_nand();
debug("board_nand_init()\n");
writel(readl(&clk_power->clkcon) | (1 << 4), &clk_power->clkcon);
/* initialize hardware */
#if defined(CONFIG_S3C24XX_CUSTOM_NAND_TIMING)
tacls = CONFIG_S3C24XX_TACLS;
twrph0 = CONFIG_S3C24XX_TWRPH0;
twrph1 = CONFIG_S3C24XX_TWRPH1;
#else
tacls = 4;
twrph0 = 8;
twrph1 = 8;
#endif
cfg = S3C2410_NFCONF_EN;
cfg |= S3C2410_NFCONF_TACLS(tacls - 1);
cfg |= S3C2410_NFCONF_TWRPH0(twrph0 - 1);
cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1);
writel(cfg, &nand_reg->nfconf);
#endif
#define MP0_1CON (*(volatile unsigned int *)0xE02002E0)
#define MP0_3CON (*(volatile unsigned int *)0xE0200320)
#define NFCONF (*(volatile unsigned int *)0xB0E00000)
#define NFCONT (*(volatile unsigned int *)0xB0E00004)
#define NFCMMD (*(volatile unsigned char *)0xB0E00008)
#define NFADDR (*(volatile unsigned char *)0xB0E0000C)
#define NFDATA (*(volatile unsigned char *)0xB0E00010)
#define NFSTAT (*(volatile unsigned int *)0xB0E00028)
#define NFCONF_VAL ((7<<12)|(7<<8)|(7<<4)|(0<<3)|(0<<2)|(1<<1))
#define NFCONT_VAL ((1<<23)|(1<<22)|(1<<2)|(0<<1)|(1<<0))
unsigned int tmp;
//tmp = MP0_1CON;
//tmp &= ~((0xf<<8)|(0xf<<12));
//tmp |= (0x3<<8) | (0x3<<12);
//MP0_1CON = tmp;
tmp = MP0_1CON;
tmp &= ~(0xf<<16);
tmp |= (0x3<<16);
MP0_1CON = tmp;
tmp = MP0_3CON;
//tmp &= ~((0xf<<0)|(0xf<<4)|(0xf<<8)|(0xf<<12)|(0xf<<16)|(0xf<<20));
//tmp |= (0x2<<0)|(0x2<<4)|(0x2<<8)|(0x2<<12)|(0x2<<16)|(0x2<<20);
tmp &= ~((0xf<<0)|(0xf<<4)|(0xf<<8)|(0xf<<12)|(0xf<<16));
tmp |= (0x2<<0)|(0x2<<4)|(0x2<<8)|(0x2<<12)|(0x2<<16);
MP0_3CON = tmp;
NFCONF = NFCONF_VAL;
NFCONT = NFCONT_VAL;
/* initialize nand_chip data structure */
nand->IO_ADDR_R = (volatile unsigned char *)0xB0E00010;
nand->IO_ADDR_W = (volatile unsigned char *)0xB0E00010;
nand->select_chip = s5pv210_select_chip;
/* read_buf and write_buf are default */
/* read_byte and write_byte are default */
#ifdef CONFIG_NAND_SPL
nand->read_buf = nand_read_buf;
#endif
/* hwcontrol always must be implemented */
nand->cmd_ctrl = s3c2410_hwcontrol;
nand->dev_ready = s3c2410_dev_ready;
#ifdef CONFIG_S3C2410_NAND_HWECC
nand->ecc.hwctl = s3c2410_nand_enable_hwecc;
nand->ecc.calculate = s3c2410_nand_calculate_ecc;
nand->ecc.correct = s3c2410_nand_correct_data;
nand->ecc.mode = NAND_ECC_HW;
nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
nand->ecc.strength = 1;
#else
nand->ecc.mode = NAND_ECC_SOFT;
#endif
#ifdef CONFIG_S3C2410_NAND_BBT
nand->bbt_options |= NAND_BBT_USE_FLASH;
#endif
debug("end of nand_init\n");
return 0;
}
int usb_cpu_init_fail(void)
{
struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
writel(readl(&clk_power->clkcon) & ~USB_CEN_MASK, &clk_power->clkcon);
return 0;
}
int board_init (void)
{
struct s3c24x0_clock_power * const clk_power =
s3c24x0_get_base_clock_power();
struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
/* to reduce PLL lock time, adjust the LOCKTIME register */
clk_power->LOCKTIME = 0xFFFFFF;
/* configure MPLL */
clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
/* some delay between MPLL and UPLL */
delay (4000);
/* configure UPLL */
clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
/* some delay between MPLL and UPLL */
delay (8000);
/* set up the I/O ports */
gpio->GPACON = 0x007FFFFF;
/*^@@-1,+1@@<2>: GPIO设置需要参考原理图*/
// gpio->GPBCON = 0x00044555;
gpio->GPBCON = 0x00295551;
/*$*/
gpio->GPBUP = 0x000007FF;
gpio->GPCCON = 0xAAAAAAAA;
gpio->GPCUP = 0x0000FFFF;
gpio->GPDCON = 0xAAAAAAAA;
gpio->GPDUP = 0x0000FFFF;
gpio->GPECON = 0xAAAAAAAA;
gpio->GPEUP = 0x0000FFFF;
/*
* ^@@-1,+1@@<5>: GPF7接DM9000的INT端口，因此我们将其配置
* 为EINT7，虽然u-boot的DM9000并未采用中断方式。
*/
// gpio->GPFCON = 0x000055AA;
gpio->GPFCON = 0x0000AAAA;
/*$*/
gpio->GPFUP = 0x000000FF;
gpio->GPGCON = 0xFF95FFBA;
gpio->GPGUP = 0x0000FFFF;
gpio->GPHCON = 0x002AFAAA;
gpio->GPHUP = 0x000007FF;
/*
* ^@@-2,+2@@<6>: 修改机器类型号，MACH_TYPE_SMDK2440
* 宏需要在include/asm-arm/mach-types.h中添加*/
// /* arch number of SMDK2410-Board */
// gd->bd->bi_arch_number = MACH_TYPE_SMDK2410;
/* arch number of SMDK2440-Board */
gd->bd->bi_arch_number = MACH_TYPE_SMDK2440;
/*$*/
/* adress of boot parameters */
gd->bd->bi_boot_params = 0x30000100;
icache_enable();
dcache_enable();
return 0;
}
