void __init exynos5_manta_camera_init(void)
{
	manta_camera_sysmmu_init();
	platform_add_devices(camera_devices, ARRAY_SIZE(camera_devices));

	/* SPI */
	exynos_spi_clock_setup(&s3c64xx_device_spi1.dev, 1);

	if (!exynos_spi_cfg_cs(spi1_csi[0].line, 1)) {
		s3c64xx_spi1_pdata.gpio_pull_up = manta_gpio_pull_up;
		s3c64xx_spi1_set_platdata(&s3c64xx_spi1_pdata,
			EXYNOS_SPI_SRCCLK_SCLK, ARRAY_SIZE(spi1_csi));

		spi_register_board_info(spi1_board_info,
			ARRAY_SIZE(spi1_board_info));
	} else {
		pr_err("%s: Error requesting gpio for SPI-CH1 CS\n", __func__);
	}

	/* FIMC-IS-MC */
	dev_set_name(&exynos5_device_fimc_is.dev, "s5p-mipi-csis.0");
	clk_add_alias("gscl_wrap0", FIMC_IS_MODULE_NAME, "gscl_wrap0",
			&exynos5_device_fimc_is.dev);
	clk_add_alias("sclk_gscl_wrap0", FIMC_IS_MODULE_NAME, "sclk_gscl_wrap0",
			&exynos5_device_fimc_is.dev);

	dev_set_name(&exynos5_device_fimc_is.dev, "s5p-mipi-csis.1");
	clk_add_alias("gscl_wrap1", FIMC_IS_MODULE_NAME, "gscl_wrap1",
			&exynos5_device_fimc_is.dev);
	clk_add_alias("sclk_gscl_wrap1", FIMC_IS_MODULE_NAME, "sclk_gscl_wrap1",
			&exynos5_device_fimc_is.dev);

	dev_set_name(&exynos5_device_fimc_is.dev, "exynos-gsc.0");
	clk_add_alias("gscl", FIMC_IS_MODULE_NAME, "gscl",
			&exynos5_device_fimc_is.dev);
	dev_set_name(&exynos5_device_fimc_is.dev, FIMC_IS_MODULE_NAME);

#if defined CONFIG_VIDEO_S5K6A3
	exynos5_fimc_is_data.sensor_info[s5k6a3.sensor_position] = &s5k6a3;
#endif
#if defined CONFIG_VIDEO_S5K4E5
	exynos5_fimc_is_data.sensor_info[s5k4e5.sensor_position] = &s5k4e5;
#endif

	exynos5_fimc_is_set_platdata(&exynos5_fimc_is_data);
}
void __init tmm_dev_init(void)
{
	int ret;
	
#if defined(CONFIG_TMM_ANT_DET)
	s5p_register_gpio_interrupt(GPIO_TDMB_ANT_DET);
	s3c_gpio_cfgpin(GPIO_TDMB_ANT_DET, S3C_GPIO_SFN(0xf));
	s3c_gpio_setpull(GPIO_TDMB_ANT_DET, S3C_GPIO_PULL_UP);
#endif
	
	ret = platform_device_register(&tmm_i2c_device);
	
	if (ret < 0) {
		pr_err("%s: i2c platform_device_register returned error ret = %d\n", __func__, ret);
		return;
	}
	
	ret = platform_device_register(&tmm_spi_device);
	
	if (ret < 0) {
		pr_err("%s: spi platform_device_register returned error ret = %d\n", __func__, ret);
		return;
	}
	
	i2c_register_board_info(25, i2c_smtej113_tmm,
							ARRAY_SIZE(i2c_smtej113_tmm));
	
	if (!exynos_spi_cfg_cs(spi1_csi[0].line, 1)) {
		s3c64xx_spi1_set_platdata(&s3c64xx_spi1_pdata,
								EXYNOS_SPI_SRCCLK_SCLK, ARRAY_SIZE(spi1_csi));
		ret = spi_register_board_info(spi1_board_info,
								ARRAY_SIZE(spi1_board_info));
		if (ret) {
			pr_err("%s: spi_register_board_info returned error ret = %d\n", __func__, ret);
		}
	}
	else {
		pr_err("%s:exynos_spi_cfg_cs returned error ret = %d\n", __func__, ret);
	}
	return;
}
void __init exynos5_universal5420_sensor_init(void)
{
	int ret = 0;

	pr_info("%s, is called\n", __func__);

#ifdef CONFIG_SENSORS_SSP
	ret = initialize_ssp_gpio();
	if (ret < 0)
		pr_err("%s, initialize_ssp_gpio fail(err=%d)\n", __func__, ret);
#endif

#if defined(CONFIG_V1A) || defined(CONFIG_N1A)
	s3c_i2c3_set_platdata(NULL);
	ret = i2c_register_board_info(3, i2c_devs3, ARRAY_SIZE(i2c_devs3));
	if (ret < 0) {
		pr_err("%s, i2c3 adding i2c fail(err=%d)\n", __func__, ret);
	}

	ret = platform_device_register(&s3c_device_i2c3);
	if (ret < 0)
		pr_err("%s, sensor platform device register failed (err=%d)\n",
			__func__, ret);

#endif

#if defined(CONFIG_V1A_3G) || defined(CONFIG_N1A_3G)
	exynos5_hs_i2c0_set_platdata(&hs_i2c0_data);
	ret = i2c_register_board_info(4, i2c_devs4, ARRAY_SIZE(i2c_devs4));
	if (ret < 0) {
		pr_err("%s, i2c4 adding i2c fail(err=%d)\n", __func__, ret);
	}

	ret = platform_device_register(&exynos5_device_hs_i2c0);
	if (ret < 0)
		pr_err("%s, grip platform device register failed (err=%d)\n",
			__func__, ret);
#endif


#ifdef CONFIG_SENSORS_SSP_STM
	pr_info("%s, SSP_SPI_SETUP\n", __func__);
	if (!exynos_spi_cfg_cs(spi0_csi[0].line, 0)) {
		pr_info("%s, spi0_set_platdata ...\n", __func__);
		ssp_spi0_set_platdata(&s3c64xx_spi0_pdata,
			EXYNOS_SPI_SRCCLK_SCLK, ARRAY_SIZE(spi0_csi));

		spi_register_board_info(spi0_board_info,
			ARRAY_SIZE(spi0_board_info));
	} else {
		pr_err("%s, Error requesting gpio for SPI-CH%d CS",
			__func__, spi0_board_info->bus_num);
	}

	ret = platform_device_register(&s3c64xx_device_spi0);
	if (ret < 0)
		pr_err("%s, Failed to register spi0 plaform devices(err=%d)\n",
			__func__, ret);
#endif

#ifdef CONFIG_SENSORS_VFS61XX
	pr_info("%s: SENSORS_VFS61XX init\n", __func__);
	vfs61xx_setup_gpio();
	s3c64xx_spi1_pdata.dma_mode = PIO_MODE;
	if (system_rev > 4)
		vfs61xx_pdata.ldocontrol = 1;

	if (!exynos_spi_cfg_cs(spi1_csi[0].line, 1)) {
		pr_info("%s: spi1_set_platdata ...\n", __func__);
		s3c64xx_spi1_set_platdata(&s3c64xx_spi1_pdata,
			EXYNOS_SPI_SRCCLK_SCLK, ARRAY_SIZE(spi1_csi));

		spi_register_board_info(spi1_board_info,
			ARRAY_SIZE(spi1_board_info));
	} else {
		pr_err("%s : Error requesting gpio for SPI-CH%d CS",
			__func__, spi1_board_info->bus_num);
	}
	platform_device_register(&s3c64xx_device_spi1);
#endif
}
void __init exynos5_universal5410_media_init(void)
{
#if defined (CONFIG_CSI_D) || defined (CONFIG_S5K6B2_CSI_D)
	s3c_i2c1_set_platdata(NULL);
#endif
#if defined (CONFIG_CSI_E) || defined (CONFIG_S5K6B2_CSI_E)
	s3c_i2c1_set_platdata(NULL);
#endif
#ifdef CONFIG_VIDEO_EXYNOS_MFC
	s5p_mfc_set_platdata(&universal5410_mfc_pd);

	dev_set_name(&s5p_device_mfc.dev, "s3c-mfc");
	clk_add_alias("mfc", "s5p-mfc-v6", "mfc", &s5p_device_mfc.dev);
	s5p_mfc_setname(&s5p_device_mfc, "s5p-mfc-v6");
#endif

	platform_add_devices(universal5410_media_devices,
			ARRAY_SIZE(universal5410_media_devices));

#ifdef CONFIG_VIDEO_S5K6B2
#if defined(CONFIG_S5K6B2_CSI_C)
	__set_mipi_csi_config(&s5p_mipi_csis0_default_data, s5k6b2.csi_data_align);
#elif defined(CONFIG_S5K6B2_CSI_D)
	__set_mipi_csi_config(&s5p_mipi_csis1_default_data, s5k6b2.csi_data_align);
#elif defined(CONFIG_S5K6B2_CSI_E)
	__set_mipi_csi_config(&s5p_mipi_csis2_default_data, s5k6b2.csi_data_align);
#endif
#endif

#ifdef CONFIG_VIDEO_EXYNOS_MIPI_CSIS
	s3c_set_platdata(&s5p_mipi_csis0_default_data,
			sizeof(s5p_mipi_csis0_default_data), &s5p_device_mipi_csis0);
	s3c_set_platdata(&s5p_mipi_csis1_default_data,
			sizeof(s5p_mipi_csis1_default_data), &s5p_device_mipi_csis1);
	s3c_set_platdata(&s5p_mipi_csis2_default_data,
			sizeof(s5p_mipi_csis2_default_data), &s5p_device_mipi_csis2);
#endif
#ifdef CONFIG_VIDEO_EXYNOS_FIMC_LITE
	universal5410_camera_gpio_cfg();
	universal5410_set_camera_platdata();
	s3c_set_platdata(&exynos_flite0_default_data,
			sizeof(exynos_flite0_default_data), &exynos_device_flite0);
	s3c_set_platdata(&exynos_flite1_default_data,
			sizeof(exynos_flite1_default_data), &exynos_device_flite1);
	s3c_set_platdata(&exynos_flite2_default_data,
			sizeof(exynos_flite2_default_data), &exynos_device_flite2);
#endif

#if defined(CONFIG_VIDEO_EXYNOS_TV)
	dev_set_name(&s5p_device_hdmi.dev, "exynos5-hdmi");
	mxr_platdata.ip_ver = IP_VER_TV_5A_1;
	hdmi_platdata.ip_ver = IP_VER_TV_5A_1;

	s5p_tv_setup();
/* Below should be enabled after power domain is available */
#if 0
	s5p_device_hdmi.dev.parent = &exynos5_device_pd[PD_DISP1].dev;
	s5p_device_mixer.dev.parent = &exynos5_device_pd[PD_DISP1].dev;
#endif
#ifdef CONFIG_VIDEO_EXYNOS_HDMI_CEC
	s5p_hdmi_cec_set_platdata(&hdmi_cec_data);
#endif
	s3c_set_platdata(&mxr_platdata, sizeof(mxr_platdata), &s5p_device_mixer);
	s5p_hdmi_set_platdata(&hdmi_platdata);
	/*
	 * exynos5_hs_i2c2_set_platdata(NULL);
	 * i2c_register_board_info(6, hs_i2c_devs2, ARRAY_SIZE(hs_i2c_devs2));
	 */

#endif
#ifdef CONFIG_VIDEO_EXYNOS_GSCALER
	exynos5_gsc_set_ip_ver(IP_VER_GSC_5A);

	s3c_set_platdata(&exynos_gsc0_default_data, sizeof(exynos_gsc0_default_data),
			&exynos5_device_gsc0);
	s3c_set_platdata(&exynos_gsc1_default_data, sizeof(exynos_gsc1_default_data),
			&exynos5_device_gsc1);
	s3c_set_platdata(&exynos_gsc2_default_data, sizeof(exynos_gsc2_default_data),
			&exynos5_device_gsc2);
	s3c_set_platdata(&exynos_gsc3_default_data, sizeof(exynos_gsc3_default_data),
			&exynos5_device_gsc3);
#endif
#ifdef CONFIG_VIDEO_EXYNOS5_FIMC_IS
	dev_set_name(&exynos5_device_fimc_is.dev, "s5p-mipi-csis.0");
	clk_add_alias("gscl_wrap0", FIMC_IS_MODULE_NAME, "gscl_wrap0", &exynos5_device_fimc_is.dev);
	dev_set_name(&exynos5_device_fimc_is.dev, "s5p-mipi-csis.1");
	clk_add_alias("gscl_wrap1", FIMC_IS_MODULE_NAME, "gscl_wrap1", &exynos5_device_fimc_is.dev);
	dev_set_name(&exynos5_device_fimc_is.dev, "s5p-mipi-csis.2");
	clk_add_alias("gscl_wrap2", FIMC_IS_MODULE_NAME, "gscl_wrap2", &exynos5_device_fimc_is.dev);

	dev_set_name(&exynos5_device_fimc_is.dev, FIMC_IS_MODULE_NAME);

	exynos5_fimc_is_data.gpio_info = &gpio_universal5410;

	exynos5_fimc_is_set_platdata(&exynos5_fimc_is_data);

	if (!exynos_spi_cfg_cs(spi3_csi[0].line, 3)) {
		s3c64xx_spi3_set_platdata(&s3c64xx_spi3_pdata,
			EXYNOS_SPI_SRCCLK_SCLK, ARRAY_SIZE(spi3_csi));

		spi_register_board_info(spi3_board_info,
			ARRAY_SIZE(spi3_board_info));
	} else {
		pr_err("%s: Error requesting gpio for SPI-CH1 CS\n", __func__);
	}
#endif
#ifdef CONFIG_VIDEO_EXYNOS_FIMG2D
	s5p_fimg2d_set_platdata(&fimg2d_data);
#endif
#ifdef CONFIG_VIDEO_EXYNOS_JPEG
	exynos5_jpeg_fimp_setup_clock(&s5p_device_jpeg.dev, 166500000);
#endif
#ifdef CONFIG_VIDEO_EXYNOS_JPEG_HX
	exynos5_jpeg_hx_setup_clock(&exynos5_device_jpeg_hx.dev, 300000000);
#endif
#if defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE)
#if defined(CONFIG_TDMB_SPI)
	if (!exynos_spi_cfg_cs(spi1_csi[0].line, 1)) {
		s3c64xx_spi1_set_platdata(&s3c64xx_spi1_pdata,
			EXYNOS_SPI_SRCCLK_SCLK, ARRAY_SIZE(spi1_csi));
	spi_register_board_info(spi1_board_info,
		ARRAY_SIZE(spi1_board_info));
	} else {
		pr_err("%s: Error requesting gpio for TDMB_SPI CS\n", __func__);
	}
#endif
	tdmb_dev_init();
#endif
}