int mdnie_set_size(unsigned int hsize, unsigned int vsize)
{
unsigned int reg;
/* Bank0 Select : DO NOT REMOVE THIS LINE */
s3c_mdnie_write(MDNIE_REG_BANK_SEL, 0);
#if defined(CONFIG_CPU_EXYNOS4212) || defined(CONFIG_CPU_EXYNOS4412)
/* Input Data Unmask */
reg = s3c_mdnie_read(S3C_MDNIE_rR1);
reg &= ~S3C_MDNIE_INPUT_DATA_ENABLE;
s3c_mdnie_write(S3C_MDNIE_rR1, reg);
#endif
/* LCD width */
reg = s3c_mdnie_read(MDNIE_REG_WIDTH);
reg &= ~S3C_MDNIE_SIZE_MASK;
reg |= S3C_MDNIE_HSIZE(hsize);
s3c_mdnie_write(MDNIE_REG_WIDTH, reg);
/* LCD height */
reg = s3c_mdnie_read(MDNIE_REG_HEIGHT);
reg &= ~S3C_MDNIE_SIZE_MASK;
reg |= S3C_MDNIE_VSIZE(vsize);
s3c_mdnie_write(MDNIE_REG_HEIGHT, reg);
mdnie_unmask();
return 0;
}
static void mdnie_pwm_control(struct mdnie_info *mdnie, int value)
{
mutex_lock(&mdnie->lock);
s3c_mdnie_write(0x00, 0x0000);
s3c_mdnie_write(0xB4, 0xC000 | value);
s3c_mdnie_write(0x28, 0x0000);
mutex_unlock(&mdnie->lock);
}
static void mdnie_pwm_control_cabc(struct mdnie_info *mdnie, int value)
{
int reg;
const unsigned char *p_plut;
u16 min_duty;
unsigned idx;
mutex_lock(&mdnie->lock);
idx = tunning_table[mdnie->cabc][mdnie->mode][mdnie->scenario].idx_lut;
p_plut = power_lut[idx];
min_duty = p_plut[7] * value / 100;
s3c_mdnie_write(0x00, 0x0000);
if (min_duty < 4)
reg = 0xC000 | (max(1, (value * p_plut[3] / 100)));
else {
/*PowerLUT*/
s3c_mdnie_write(0x76, (p_plut[0] * value / 100) << 8 | (p_plut[1] * value / 100));
s3c_mdnie_write(0x77, (p_plut[2] * value / 100) << 8 | (p_plut[3] * value / 100));
s3c_mdnie_write(0x78, (p_plut[4] * value / 100) << 8 | (p_plut[5] * value / 100));
s3c_mdnie_write(0x79, (p_plut[6] * value / 100) << 8 | (p_plut[7] * value / 100));
s3c_mdnie_write(0x7a, (p_plut[8] * value / 100) << 8);
reg = 0x5000 | (value << 4);
}
s3c_mdnie_write(0xB4, reg);
s3c_mdnie_write(0x28, 0x0000);
mutex_unlock(&mdnie->lock);
}
int mdnie_send_sequence(struct mdnie_info *mdnie, const unsigned short *seq)
{
int ret = 0, i = 0;
const unsigned short *wbuf;
if (!mdnie->enable) {
dev_err(mdnie->dev, "do not configure mDNIe after LCD/mDNIe power off\n");
return -EPERM;
}
mutex_lock(&mdnie->lock);
wbuf = seq;
s3c_mdnie_writel(S3C_MDNIE_rR40, 0x7FFF);
while (wbuf[i] != END_SEQ) {
s3c_mdnie_write(wbuf[i], wbuf[i+1]);
i += 2;
}
mutex_unlock(&mdnie->lock);
return ret;
}
int mdnie_unmask(void)
{
return s3c_mdnie_write(MDNIE_REG_MASK, 0);
}
int mdnie_mask(void)
{
return s3c_mdnie_write(MDNIE_REG_MASK, 0x9FFF);
}
int mdnie_write(unsigned int addr, unsigned int val)
{
return s3c_mdnie_write(addr, val);
}