static __init int exynos4_gpiolib_init(void) { struct s3c_gpio_chip *chip; int i; int nr_chips; /* GPIO common part */ chip = exynos4_gpio_common_4bit; nr_chips = ARRAY_SIZE(exynos4_gpio_common_4bit); for (i = 0; i < nr_chips; i++, chip++) { if (chip->config == NULL) chip->config = &gpio_cfg; if (chip->base == NULL) pr_err("No allocation of base address for [common gpio]"); } samsung_gpiolib_add_4bit_chips(exynos4_gpio_common_4bit, nr_chips); /* Only 4210 GPIO part */ if (soc_is_exynos4210()) { chip = exynos4210_gpio_4bit; nr_chips = ARRAY_SIZE(exynos4210_gpio_4bit); for (i = 0; i < nr_chips; i++, chip++) { if (chip->config == NULL) chip->config = &gpio_cfg; if (chip->base == NULL) pr_err("No allocation of base address [4210 gpio]"); } samsung_gpiolib_add_4bit_chips(exynos4210_gpio_4bit, nr_chips); } else { /* Only 4212/4412 GPIO part */ chip = exynos4212_gpio_4bit; nr_chips = ARRAY_SIZE(exynos4212_gpio_4bit); for (i = 0; i < nr_chips; i++, chip++) { if (chip->config == NULL) chip->config = &gpio_cfg; if (chip->base == NULL) pr_err("No allocation of base address [4212 gpio]"); } samsung_gpiolib_add_4bit_chips(exynos4212_gpio_4bit, nr_chips); } s5p_register_gpioint_bank(IRQ_GPIO_XA, 0, IRQ_GPIO1_NR_GROUPS); s5p_register_gpioint_bank(IRQ_GPIO_XB, IRQ_GPIO1_NR_GROUPS, IRQ_GPIO2_NR_GROUPS); return 0; }
/* TODO: cleanup soc_is_* */ static __init int samsung_gpiolib_init(void) { struct samsung_gpio_chip *chip; int i, nr_chips; int group = 0; /* * Currently there are two drivers that can provide GPIO support for * Samsung SoCs. For device tree enabled platforms, the new * pinctrl-samsung driver is used, providing both GPIO and pin control * interfaces. For legacy (non-DT) platforms this driver is used. */ if (of_have_populated_dt()) return -ENODEV; samsung_gpiolib_set_cfg(samsung_gpio_cfgs, ARRAY_SIZE(samsung_gpio_cfgs)); if (soc_is_s3c24xx()) { s3c24xx_gpiolib_add_chips(s3c24xx_gpios, ARRAY_SIZE(s3c24xx_gpios), S3C24XX_VA_GPIO); } else if (soc_is_s3c64xx()) { samsung_gpiolib_add_2bit_chips(s3c64xx_gpios_2bit, ARRAY_SIZE(s3c64xx_gpios_2bit), S3C64XX_VA_GPIO + 0xE0, 0x20); samsung_gpiolib_add_4bit_chips(s3c64xx_gpios_4bit, ARRAY_SIZE(s3c64xx_gpios_4bit), S3C64XX_VA_GPIO); samsung_gpiolib_add_4bit2_chips(s3c64xx_gpios_4bit2, ARRAY_SIZE(s3c64xx_gpios_4bit2)); } else if (soc_is_s5pv210()) { group = 0; chip = s5pv210_gpios_4bit; nr_chips = ARRAY_SIZE(s5pv210_gpios_4bit); for (i = 0; i < nr_chips; i++, chip++) { if (!chip->config) { chip->config = &samsung_gpio_cfgs[3]; chip->group = group++; } } samsung_gpiolib_add_4bit_chips(s5pv210_gpios_4bit, nr_chips, S5P_VA_GPIO); #if defined(CONFIG_CPU_S5PV210) && defined(CONFIG_S5P_GPIO_INT) s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR); #endif } else { WARN(1, "Unknown SoC in gpio-samsung, no GPIOs added\n"); return -ENODEV; } return 0; }
__init int s5pv210_gpiolib_init(void) { struct s3c_gpio_chip *chip = s5pv210_gpio_4bit; int nr_chips = ARRAY_SIZE(s5pv210_gpio_4bit); int gpioint_group = 0; int i = 0; for (i = 0; i < nr_chips; i++, chip++) { if (chip->config == NULL) { chip->config = &gpio_cfg; chip->group = gpioint_group++; } if (chip->base == NULL) chip->base = S5PV210_BANK_BASE(i); } samsung_gpiolib_add_4bit_chips(s5pv210_gpio_4bit, nr_chips); s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR); return 0; }
static __init int exynos4_gpiolib_init(void) { struct s3c_gpio_chip *chip; int i; int group = 0; int nr_chips; /* GPIO part 1 */ chip = exynos4_gpio_part1_4bit; nr_chips = ARRAY_SIZE(exynos4_gpio_part1_4bit); for (i = 0; i < nr_chips; i++, chip++) { if (chip->config == NULL) { chip->config = &gpio_cfg; /* Assign the GPIO interrupt group */ chip->group = group++; } if (chip->base == NULL) chip->base = S5P_VA_GPIO1 + (i) * 0x20; } samsung_gpiolib_add_4bit_chips(exynos4_gpio_part1_4bit, nr_chips); /* GPIO part 2 */ chip = exynos4_gpio_part2_4bit; nr_chips = ARRAY_SIZE(exynos4_gpio_part2_4bit); for (i = 0; i < nr_chips; i++, chip++) { if (chip->config == NULL) { chip->config = &gpio_cfg; /* Assign the GPIO interrupt group */ chip->group = group++; } if (chip->base == NULL) chip->base = S5P_VA_GPIO2 + (i) * 0x20; } samsung_gpiolib_add_4bit_chips(exynos4_gpio_part2_4bit, nr_chips); /* GPIO part 3 */ chip = exynos4_gpio_part3_4bit; nr_chips = ARRAY_SIZE(exynos4_gpio_part3_4bit); for (i = 0; i < nr_chips; i++, chip++) { if (chip->config == NULL) { chip->config = &gpio_cfg; /* Assign the GPIO interrupt group */ chip->group = group++; } if (chip->base == NULL) chip->base = S5P_VA_GPIO3 + (i) * 0x20; } samsung_gpiolib_add_4bit_chips(exynos4_gpio_part3_4bit, nr_chips); s5p_register_gpioint_bank(IRQ_GPIO_XA, 0, IRQ_GPIO1_NR_GROUPS); s5p_register_gpioint_bank(IRQ_GPIO_XB, IRQ_GPIO1_NR_GROUPS, IRQ_GPIO2_NR_GROUPS); return 0; }