static void __init cerf_init(void)
{
sa11x0_ppc_configure_mcp();
platform_add_devices(cerf_devices, ARRAY_SIZE(cerf_devices));
sa11x0_register_mtd(&cerf_flash_data, &cerf_flash_resource, 1);
sa11x0_register_mcp(&cerf_mcp_data);
}
static int __init simpad_init(void)
{
int ret;
spin_lock_init(&cs3_lock);
cs3_gpio.label = "simpad_cs3";
cs3_gpio.base = SIMPAD_CS3_GPIO_BASE;
cs3_gpio.ngpio = 24;
cs3_gpio.set = cs3_gpio_set;
cs3_gpio.get = cs3_gpio_get;
cs3_gpio.direction_input = cs3_gpio_direction_input;
cs3_gpio.direction_output = cs3_gpio_direction_output;
ret = gpiochip_add(&cs3_gpio);
if (ret)
printk(KERN_WARNING "simpad: Unable to register cs3 GPIO device");
pm_power_off = simpad_power_off;
sa11x0_ppc_configure_mcp();
sa11x0_register_mtd(&simpad_flash_data, simpad_flash_resources,
ARRAY_SIZE(simpad_flash_resources));
sa11x0_register_mcp(&simpad_mcp_data);
ret = platform_add_devices(devices, ARRAY_SIZE(devices));
if(ret)
printk(KERN_WARNING "simpad: Unable to register mq200 framebuffer device");
return 0;
}
static void __init simpad_map_io(void)
{
sa1100_map_io();
iotable_init(simpad_io_desc, ARRAY_SIZE(simpad_io_desc));
set_cs3_bit (EN1 | EN0 | LED2_ON | DISPLAY_ON | RS232_ON |
ENABLE_5V | RESET_SIMCARD | DECT_POWER_ON);
sa1100_register_uart_fns(&simpad_port_fns);
sa1100_register_uart(0, 3); /* serial interface */
sa1100_register_uart(1, 1); /* DECT */
// Reassign UART 1 pins
GAFR |= GPIO_UART_TXD | GPIO_UART_RXD;
GPDR |= GPIO_UART_TXD | GPIO_LDD13 | GPIO_LDD15;
GPDR &= ~GPIO_UART_RXD;
PPAR |= PPAR_UPR;
/*
* Set up registers for sleep mode.
*/
PWER = PWER_GPIO0| PWER_RTC;
PGSR = 0x818;
PCFR = 0;
PSDR = 0;
sa11x0_register_mtd(&simpad_flash_data, simpad_flash_resources,
ARRAY_SIZE(simpad_flash_resources));
sa11x0_register_mcp(&simpad_mcp_data);
}
static void __init pleb_init(void)
{
sa11x0_register_mtd(&pleb_flash_data, pleb_flash_resources,
ARRAY_SIZE(pleb_flash_resources));
platform_add_devices(devices, ARRAY_SIZE(devices));
}
static void __init assabet_init(void)
{
/*
* Ensure that the power supply is in "high power" mode.
*/
GPDR |= GPIO_GPIO16;
GPSR = GPIO_GPIO16;
/*
* Ensure that these pins are set as outputs and are driving
* logic 0. This ensures that we won't inadvertently toggle
* the WS latch in the CPLD, and we don't float causing
* excessive power drain. --rmk
*/
GPDR |= GPIO_SSP_TXD | GPIO_SSP_SCLK | GPIO_SSP_SFRM;
GPCR = GPIO_SSP_TXD | GPIO_SSP_SCLK | GPIO_SSP_SFRM;
/*
* Set up registers for sleep mode.
*/
PWER = PWER_GPIO0;
PGSR = 0;
PCFR = 0;
PSDR = 0;
PPDR |= PPC_TXD3 | PPC_TXD1;
PPSR |= PPC_TXD3 | PPC_TXD1;
sa1100fb_lcd_power = assabet_lcd_power;
sa1100fb_backlight_power = assabet_backlight_power;
if (machine_has_neponset()) {
/*
* Angel sets this, but other bootloaders may not.
*
* This must precede any driver calls to BCR_set()
* or BCR_clear().
*/
ASSABET_BCR = BCR_value = ASSABET_BCR_DB1111;
#ifndef CONFIG_ASSABET_NEPONSET
printk( "Warning: Neponset detected but full support "
"hasn't been configured in the kernel\n" );
#endif
}
sa11x0_register_mtd(&assabet_flash_data, assabet_flash_resources,
ARRAY_SIZE(assabet_flash_resources));
sa11x0_register_irda(&assabet_irda_data);
sa11x0_register_mcp(&assabet_mcp_data);
}
static void __init collie_init(void)
{
int ret = 0;
/* cpu initialize */
GAFR = GPIO_SSP_TXD | GPIO_SSP_SCLK | GPIO_SSP_SFRM | GPIO_SSP_CLK |
GPIO_MCP_CLK | GPIO_32_768kHz;
GPDR = GPIO_LDD8 | GPIO_LDD9 | GPIO_LDD10 | GPIO_LDD11 | GPIO_LDD12 |
GPIO_LDD13 | GPIO_LDD14 | GPIO_LDD15 | GPIO_SSP_TXD |
GPIO_SSP_SCLK | GPIO_SSP_SFRM | GPIO_SDLC_SCLK |
_COLLIE_GPIO_UCB1x00_RESET | _COLLIE_GPIO_nMIC_ON |
_COLLIE_GPIO_nREMOCON_ON | GPIO_32_768kHz;
PPDR = PPC_LDD0 | PPC_LDD1 | PPC_LDD2 | PPC_LDD3 | PPC_LDD4 | PPC_LDD5 |
PPC_LDD6 | PPC_LDD7 | PPC_L_PCLK | PPC_L_LCLK | PPC_L_FCLK | PPC_L_BIAS |
PPC_TXD1 | PPC_TXD2 | PPC_TXD3 | PPC_TXD4 | PPC_SCLK | PPC_SFRM;
PWER = _COLLIE_GPIO_AC_IN | _COLLIE_GPIO_CO | _COLLIE_GPIO_ON_KEY |
_COLLIE_GPIO_WAKEUP | _COLLIE_GPIO_nREMOCON_INT | PWER_RTC;
PGSR = _COLLIE_GPIO_nREMOCON_ON;
PSDR = PPC_RXD1 | PPC_RXD2 | PPC_RXD3 | PPC_RXD4;
PCFR = PCFR_OPDE;
GPSR |= _COLLIE_GPIO_UCB1x00_RESET;
collie_power_resource[0].start = gpio_to_irq(COLLIE_GPIO_AC_IN);
collie_power_resource[0].end = gpio_to_irq(COLLIE_GPIO_AC_IN);
sa11x0_ppc_configure_mcp();
platform_scoop_config = &collie_pcmcia_config;
ret = platform_add_devices(devices, ARRAY_SIZE(devices));
if (ret) {
printk(KERN_WARNING "collie: Unable to register LoCoMo device\n");
}
sa11x0_register_lcd(&collie_lcd_info);
sa11x0_register_mtd(&collie_flash_data, collie_flash_resources,
ARRAY_SIZE(collie_flash_resources));
sa11x0_register_mcp(&collie_mcp_data);
sharpsl_save_param();
}
static void __init shannon_init(void)
{
sa11x0_register_mtd(&shannon_flash_data, &shannon_flash_resource, 1);
/*
* Setup the PPC unit correctly.
*/
PPDR &= ~PPC_RXD4;
PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM;
PSDR |= PPC_RXD4;
PSDR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
sa11x0_register_mcp(&shannon_mcp_data);
}
static int __init badge4_init(void)
{
int ret;
if (!machine_is_badge4())
return -ENODEV;
/* LCD */
GPCR = (BADGE4_GPIO_LGP2 | BADGE4_GPIO_LGP3 |
BADGE4_GPIO_LGP4 | BADGE4_GPIO_LGP5 |
BADGE4_GPIO_LGP6 | BADGE4_GPIO_LGP7 |
BADGE4_GPIO_LGP8 | BADGE4_GPIO_LGP9 |
BADGE4_GPIO_GPA_VID | BADGE4_GPIO_GPB_VID |
BADGE4_GPIO_GPC_VID);
GPDR &= ~BADGE4_GPIO_INT_VID;
GPDR |= (BADGE4_GPIO_LGP2 | BADGE4_GPIO_LGP3 |
BADGE4_GPIO_LGP4 | BADGE4_GPIO_LGP5 |
BADGE4_GPIO_LGP6 | BADGE4_GPIO_LGP7 |
BADGE4_GPIO_LGP8 | BADGE4_GPIO_LGP9 |
BADGE4_GPIO_GPA_VID | BADGE4_GPIO_GPB_VID |
BADGE4_GPIO_GPC_VID);
/* SDRAM SPD i2c */
GPCR = (BADGE4_GPIO_SDSDA | BADGE4_GPIO_SDSCL);
GPDR |= (BADGE4_GPIO_SDSDA | BADGE4_GPIO_SDSCL);
/* uart */
GPCR = (BADGE4_GPIO_UART_HS1 | BADGE4_GPIO_UART_HS2);
GPDR |= (BADGE4_GPIO_UART_HS1 | BADGE4_GPIO_UART_HS2);
/* CPLD muxsel0 input for mux/adc chip select */
GPCR = BADGE4_GPIO_MUXSEL0;
GPDR |= BADGE4_GPIO_MUXSEL0;
/* test points: J5, J6 as inputs, J7 outputs */
GPDR &= ~(BADGE4_GPIO_TESTPT_J5 | BADGE4_GPIO_TESTPT_J6);
GPCR = BADGE4_GPIO_TESTPT_J7;
GPDR |= BADGE4_GPIO_TESTPT_J7;
/* 5V supply rail. */
GPCR = BADGE4_GPIO_PCMEN5V; /* initially off */
GPDR |= BADGE4_GPIO_PCMEN5V;
/* CPLD sdram type inputs; set up by blob */
//GPDR |= (BADGE4_GPIO_SDTYP1 | BADGE4_GPIO_SDTYP0);
printk(KERN_DEBUG __FILE__ ": SDRAM CPLD typ1=%d typ0=%d\n",
!!(GPLR & BADGE4_GPIO_SDTYP1),
!!(GPLR & BADGE4_GPIO_SDTYP0));
/* SA1111 reset pin; set up by blob */
//GPSR = BADGE4_GPIO_SA1111_NRST;
//GPDR |= BADGE4_GPIO_SA1111_NRST;
/* power management cruft */
PGSR = 0;
PWER = 0;
PCFR = 0;
PSDR = 0;
PWER |= PWER_GPIO26; /* wake up on an edge from TESTPT_J5 */
PWER |= PWER_RTC; /* wake up if rtc fires */
/* drive sa1111_nrst during sleep */
PGSR |= BADGE4_GPIO_SA1111_NRST;
/* drive CPLD as is during sleep */
PGSR |= (GPLR & (BADGE4_GPIO_SDTYP0|BADGE4_GPIO_SDTYP1));
/* Now bring up the SA-1111. */
ret = badge4_sa1111_init();
if (ret < 0)
printk(KERN_ERR
"%s: SA-1111 initialization failed (%d)\n",
__func__, ret);
/* maybe turn on 5v0 from the start */
badge4_set_5V(BADGE4_5V_INITIALLY, five_v_on);
sa11x0_register_mtd(&badge4_flash_data, &badge4_flash_resource, 1);
return 0;
}
static void __init shannon_init(void)
{
sa11x0_register_mtd(&shannon_flash_data, &shannon_flash_resource, 1);
sa11x0_register_mcp(&shannon_mcp_data);
}
static void __init nanoengine_init(void)
{
sa11x0_register_mtd(&nanoengine_flash_data, nanoengine_flash_resources,
ARRAY_SIZE(nanoengine_flash_resources));
}
static void __init jornada720_mach_init(void)
{
sa11x0_register_mtd(&jornada720_flash_data, &jornada720_flash_resource, 1);
}
void __init h3xxx_mach_init(void)
{
sa1100_register_uart_fns(&h3xxx_port_fns);
sa11x0_register_mtd(&h3xxx_flash_data, &h3xxx_flash_resource, 1);
platform_add_devices(h3xxx_devices, ARRAY_SIZE(h3xxx_devices));
}
static void __init hackkit_init(void)
{
sa11x0_register_mtd(&hackkit_flash_data, &hackkit_flash_resource, 1);
}
static void __init assabet_init(void)
{
/*
* Ensure that the power supply is in "high power" mode.
*/
GPSR = GPIO_GPIO16;
GPDR |= GPIO_GPIO16;
/*
* Ensure that these pins are set as outputs and are driving
* logic 0. This ensures that we won't inadvertently toggle
* the WS latch in the CPLD, and we don't float causing
* excessive power drain. --rmk
*/
GPCR = GPIO_SSP_TXD | GPIO_SSP_SCLK | GPIO_SSP_SFRM;
GPDR |= GPIO_SSP_TXD | GPIO_SSP_SCLK | GPIO_SSP_SFRM;
/*
* Also set GPIO27 as an output; this is used to clock UART3
* via the FPGA and as otherwise has no pullups or pulldowns,
* so stop it floating.
*/
GPCR = GPIO_GPIO27;
GPDR |= GPIO_GPIO27;
/*
* Set up registers for sleep mode.
*/
PWER = PWER_GPIO0;
PGSR = 0;
PCFR = 0;
PSDR = 0;
PPDR |= PPC_TXD3 | PPC_TXD1;
PPSR |= PPC_TXD3 | PPC_TXD1;
sa11x0_ppc_configure_mcp();
if (machine_has_neponset()) {
/*
* Angel sets this, but other bootloaders may not.
*
* This must precede any driver calls to BCR_set()
* or BCR_clear().
*/
ASSABET_BCR = BCR_value = ASSABET_BCR_DB1111;
#ifndef CONFIG_ASSABET_NEPONSET
printk( "Warning: Neponset detected but full support "
"hasn't been configured in the kernel\n" );
#else
platform_device_register_simple("neponset", 0,
neponset_resources, ARRAY_SIZE(neponset_resources));
#endif
}
#ifndef ASSABET_PAL_VIDEO
sa11x0_register_lcd(&lq039q2ds54_info);
#else
sa11x0_register_lcd(&pal_video);
#endif
sa11x0_register_mtd(&assabet_flash_data, assabet_flash_resources,
ARRAY_SIZE(assabet_flash_resources));
sa11x0_register_irda(&assabet_irda_data);
sa11x0_register_mcp(&assabet_mcp_data);
}
