void tx_packet(volatile packet_t *p) {
safe_irq_disable(MACA);
BOUND_CHECK(p);
if(!p) { PRINTF("tx_packet passed packet 0\n\r"); return; }
if(tx_head == 0) {
/* start a new queue if empty */
tx_end = p;
tx_end->left = 0; tx_end->right = 0;
tx_head = tx_end;
} else {
/* add p to the end of the queue */
tx_end->left = p;
p->right = tx_end;
/* move the queue */
tx_end = p; tx_end->left = 0;
}
// print_packets("tx packet");
irq_restore();
if(bit_is_set(*NIPEND, INT_NUM_MACA)) { *INTFRC = (1 << INT_NUM_MACA); }
if(last_post == NO_POST) { *INTFRC = (1<<INT_NUM_MACA); }
/* if we are in a reception cycle, advance the softclock timeout to now */
if(last_post == RX_POST) { *MACA_SFTCLK = *MACA_CLK + CLK_PER_BYTE; }
return;
}
void insert_at_rx_head(volatile packet_t *p) {
safe_irq_disable(MACA);
BOUND_CHECK(p);
if(!p) { PRINTF("insert_at_rx_head passed packet 0\n\r"); return; }
p->offset = 1; /* first byte is the length */
if(rx_head == 0) {
/* start a new queue if empty */
rx_end = p;
rx_end->left = 0; rx_end->right = 0;
rx_head = rx_end;
} else {
rx_head->right = p;
p->left = rx_head;
p->right = 0;
rx_head = p;
}
// print_packets("insert at rx head");
irq_restore();
if(bit_is_set(*NIPEND, INT_NUM_MACA)) { *INTFRC = (1 << INT_NUM_MACA); }
return;
}
volatile packet_t* get_free_packet(void) {
volatile packet_t *p;
safe_irq_disable(MACA);
BOUND_CHECK(free_head);
p = free_head;
if( p != 0 ) {
free_head = p->left;
free_head->right = 0;
}
BOUND_CHECK(free_head);
#if PACKET_STATS
p->get_free++;
#endif
// print_packets("get_free_packet");
irq_restore();
if(bit_is_set(*NIPEND, INT_NUM_MACA)) { *INTFRC = (1 << INT_NUM_MACA); }
return p;
}
/* ends are to the left */
void free_packet(volatile packet_t *p) {
safe_irq_disable(MACA);
BOUND_CHECK(p);
if(!p) { PRINTF("free_packet passed packet 0\n\r"); return; }
if(p == &dummy_ack) { return; }
BOUND_CHECK(free_head);
p->length = 0; p->offset = 0;
p->left = free_head; p->right = 0;
#if PACKET_STATS
p->seen = 0;
p->post_tx = 0;
p->get_free = 0;
p->rxd = 0;
#endif
free_head = p;
BOUND_CHECK(free_head);
irq_restore();
if(bit_is_set(*NIPEND, INT_NUM_MACA)) { *INTFRC = (1 << INT_NUM_MACA); }
return;
}
void set_channel(uint8_t chan) {
volatile uint32_t tmp;
safe_irq_disable(MACA);
tmp = reg(ADDR_CHAN1);
tmp = tmp & 0xbfffffff;
reg(ADDR_CHAN1) = tmp;
reg(ADDR_CHAN2) = VCODivI[chan];
reg(ADDR_CHAN3) = VCODivF[chan];
tmp = reg(ADDR_CHAN4);
tmp = tmp | 2;
reg(ADDR_CHAN4) = tmp;
tmp = reg(ADDR_CHAN4);
tmp = tmp | 4;
reg(ADDR_CHAN4) = tmp;
tmp = tmp & 0xffffe0ff;
tmp = tmp | (((ctov[chan])<<8)&0x1F00);
reg(ADDR_CHAN4) = tmp;
/* duh! */
irq_restore();
if(bit_is_set(*NIPEND, INT_NUM_MACA)) { *INTFRC = (1 << INT_NUM_MACA); }
}
void check_maca(void) {
safe_irq_disable(MACA);
static volatile uint32_t last_time;
static volatile uint32_t last_entry;
volatile uint32_t i;
#if DEBUG_MACA
volatile uint32_t count;
#endif
/* if *MACA_CLK == last_time */
/* try waiting for one clock period */
/* since maybe check_maca is getting called quickly */
for(i=0; (i < 1024) && (*MACA_CLK == last_time); i++) {
continue;
}
if(*MACA_CLK == last_time) {
PRINTF("check maca: maca_clk stopped, restarting\n");
/* clock isn't running */
ResumeMACASync();
*INTFRC = (1<<INT_NUM_MACA);
} else {
if((last_time > (*MACA_SFTCLK + RECV_SOFTIMEOUT)) &&
(last_time > (*MACA_CPLCLK + CPL_TIMEOUT))) {
PRINTF("check maca: complete clocks expired\n");
/* all complete clocks have expired */
/* check that maca entry is changing */
/* if not, do call the isr to restart the cycle */
if(last_entry == maca_entry) {
PRINTF("check maca: forcing isr\n");
*INTFRC = (1<<INT_NUM_MACA);
}
}
}
last_entry = maca_entry;
last_time = *MACA_CLK;
#if DEBUG_MACA
if((count = count_packets()) != NUM_PACKETS) {
PRINTF("check maca: count_packets %d\n", count);
Print_Packets("check_maca");
#if PACKET_STATS
for(i=0; i<NUM_PACKETS; i++) {
printf("packet 0x%lx seen %d post_tx %d get_free %d rxd %d\n",
(uint32_t) &packet_pool[i],
packet_pool[i].seen,
packet_pool[i].post_tx,
packet_pool[i].get_free,
packet_pool[i].rxd);
}
#endif
if(bit_is_set(*NIPEND, INT_NUM_MACA)) {
*INTFRC = (1 << INT_NUM_MACA);
}
}
#endif /* DEBUG_MACA */
irq_restore();
}
void free_all_packets(void) {
volatile int i;
safe_irq_disable(MACA);
free_head = 0;
for(i=0; i<NUM_PACKETS; i++) {
free_packet((volatile packet_t *)&(packet_pool[i]));
}
rx_head = 0; rx_end = 0;
tx_head = 0; tx_end = 0;
irq_restore();
if(bit_is_set(*NIPEND, INT_NUM_MACA)) { *INTFRC = (1 << INT_NUM_MACA); }
return;
}
void free_tx_head(void) {
volatile packet_t *p;
safe_irq_disable(MACA);
BOUND_CHECK(tx_head);
p = tx_head;
tx_head = tx_head->left;
if(tx_head == 0) { tx_end = 0; }
free_packet(p);
// print_packets("free tx head");
irq_restore();
if(bit_is_set(*NIPEND, INT_NUM_MACA)) { *INTFRC = (1 << INT_NUM_MACA); }
return;
}
void set_power(uint8_t power) {
safe_irq_disable(MACA);
reg(ADDR_POW1) = PSMVAL[power];
/* see http://devl.org/pipermail/mc1322x/2009-October/000065.html */
/* reg(ADDR_POW2) = (ADDR_POW1>>18) | PAVAL[power]; */
#ifdef USE_PA
reg(ADDR_POW2) = 0xffffdfff & PAVAL[power]; /* single port */
#else
reg(ADDR_POW2) = 0x00002000 | PAVAL[power]; /* dual port */
#endif
reg(ADDR_POW3) = AIMVAL[power];
irq_restore();
if(bit_is_set(*NIPEND, INT_NUM_MACA)) { *INTFRC = (1 << INT_NUM_MACA); }
}
