const char *
get_system_type(void)
{
static char s[32];
if (bcm947xx_sbh) {
sprintf(s, "Broadcom BCM%X chip rev %d", sb_chip(bcm947xx_sbh),
sb_chiprev(bcm947xx_sbh));
return s;
}
else
return "Broadcom BCM947XX";
}
void __init bcm947xx_time_init(void)
{
unsigned int hz;
extifregs_t *eir;
/*
* Use deterministic values for initial counter interrupt
* so that calibrate delay avoids encountering a counter wrap.
*/
write_c0_count(0);
write_c0_compare(0xffff);
if (!(hz = sb_mips_clock(sbh)))
hz = 100000000;
#if defined(CONFIG_BCM94702_CPCI) || defined(CONFIG_BCM94704_CPCI)
/* Init RTC */
rtc17xx_tod_init();
rtc17xx_tod_print();
/* Use RTC from local bus */
rtc_get_time = rtc17xx_get_time;
rtc_set_time = rtc17xx_set_time;
#endif
printk("CPU: BCM%04x rev %d at %d MHz\n", sb_chip(sbh),
sb_chiprev(sbh), (hz + 500000) / 1000000);
/* Set MIPS counter frequency for fixed_rate_gettimeoffset() */
mips_hpt_frequency = hz / 2;
/* Set watchdog interval in ms */
watchdog = simple_strtoul(nvram_safe_get("watchdog"), NULL, 0);
/* Set panic timeout in seconds */
panic_timeout = watchdog / 1000;
/* Setup blink */
if ((eir = sb_setcore(sbh, SB_EXTIF, 0))) {
sbconfig_t *sb =
(sbconfig_t *) ((unsigned int) eir + SBCONFIGOFF);
unsigned long base =
EXTIF_CFGIF_BASE(sb_base
(readl((void *) (&sb->sbadmatch1))));
mcr = (u8 *) ioremap_nocache(base + UART_MCR, 1);
}
}
