int sc_main(int ac, char *av[]) { sc_trace_file *tf; sc_signal<bool> clock; sc_signal<int> I; sc_signal<char> C; sc_signal<float> F; sc_signal<sc_logic> L; proc1 P1("P1", clock, I, C, F, L); tf = sc_create_wif_trace_file("test08"); sc_trace(tf, clock, "Clock"); sc_trace(tf, I, "Int", 32); sc_trace(tf, C, "Char", 8); sc_trace(tf, F, "Float"); sc_trace(tf, L, "Logic"); clock.write(0); sc_start(0, SC_NS); for (int i = 0; i< 10; i++) { clock.write(1); sc_start(10, SC_NS); clock.write(0); sc_start(10, SC_NS); } sc_close_wif_trace_file( tf ); return 0; }
int sc_main(int argc, char *argv[]) //(int ac, char** av) { sc_signal<sc_uint<1> > int1 ; sc_signal<sc_uint<1> > int2 ; sc_clock clk("clk", 20, SC_NS, 0.5); // instanciate Processes flop FLOP("flip_flop"); FLOP.clk(clk) ; FLOP.in(int1) ; FLOP.out(int2) ; sc_trace_file * tf = sc_create_wif_trace_file("test"); sc_trace( tf, clk, "clk"); sc_trace( tf, int1, "int1"); sc_trace( tf, int2, "int2"); /* sc_trace_file * tf2 = sc_create_vcd_trace_file("dump_vcd"); sc_trace( tf2, clk, "clk"); sc_trace( tf2, int1, "int1"); sc_trace( tf2, int2, "int2"); */ sc_start(1000, SC_NS); sc_close_wif_trace_file( tf ); return 0; }
int sc_main(int ac, char *av[]) { sc_trace_file *tf; sc_signal<bool> clock; sc_signal<sc_bv<4> > bv; sc_signal<sc_lv<4> > sv; proc1 P1("P1", clock, bv, sv); tf = sc_create_wif_trace_file("test07"); sc_trace(tf, P1.obj1, "Signed"); sc_trace(tf, P1.obj2, "Unsigned"); sc_trace(tf, bv, "BV"); sc_trace(tf, sv, "SV"); clock.write(0); sc_start(0, SC_NS); for (int i = 0; i< 10; i++) { clock.write(1); sc_start(10, SC_NS); clock.write(0); sc_start(10, SC_NS); } sc_close_wif_trace_file( tf ); return 0; }
int sc_main (int argc, char *argv[]) { sc_signal<bool> clear, left_in, right_in; sc_signal<sc_uint<SEL_WIDTH> > sel_op; sc_signal<sc_uint<WIDTH> > data_in, usr_out, expected_usr_out; // Generate clock: sc_clock clock ("usr_clock", 2); // Instantiate design under test before applying stimulus: usr u1 ("usr_u1"); u1.clk (clock); u1.clr (clear); u1.lin (left_in); u1.rin (right_in); u1.select (sel_op); u1.par_in (data_in); u1.q(usr_out); // Instantiate read vectors: read_vectors rv ("read_vectors_rv"); rv.read_clk (clock); rv.read_clear(clear); rv.read_left_in (left_in); rv.read_right_in (right_in); rv.read_sel_op (sel_op); rv.read_data_in (data_in); rv.read_usr_out (expected_usr_out); // Instantiate checking module: check_results cr1 ("check_results_cr1"); cr1.check_clk (clock); cr1.expected_out (expected_usr_out); cr1.actual_out (usr_out); // Tracing: sc_trace_file *tf = sc_create_wif_trace_file ("usrout"); sc_trace (tf, clock, "clock"); sc_trace (tf, clear, "clear"); sc_trace (tf, left_in, "left_in"); sc_trace (tf, right_in, "right_in"); sc_trace (tf, sel_op, "sel_op"); sc_trace (tf, data_in, "data_in"); sc_trace (tf, usr_out, "usr_out"); sc_start (-1); // Run forever. However simulation // stops because of sc_stop() method in module read_vectors. sc_close_wif_trace_file (tf); return (0); }