int __init __clock_init_early(void)
{
pr_info("ahb ctl0 %08x, ctl2 %08x glb aon apb0 %08x aon apb1 %08x clk_en %08x\n",
sci_glb_raw_read(REG_AP_AHB_AHB_EB),
sci_glb_raw_read(REG_AP_AHB_AHB_RST),
sci_glb_raw_read(REG_AON_APB_APB_EB0),
sci_glb_raw_read(REG_AON_APB_APB_EB1),
sci_glb_raw_read(REG_AON_CLK_PUB_AHB_CFG));
sci_glb_clr(REG_AP_AHB_AHB_EB,
BIT_BUSMON2_EB |
BIT_BUSMON1_EB |
BIT_BUSMON0_EB |
BIT_GPS_EB |
BIT_DRM_EB |
BIT_NFC_EB |
0);
sci_glb_clr(REG_AP_APB_APB_EB,
BIT_INTC3_EB |
BIT_INTC2_EB |
BIT_INTC1_EB |
BIT_IIS1_EB |
BIT_UART2_EB |
BIT_UART0_EB |
BIT_SPI1_EB |
BIT_SPI0_EB |
BIT_IIS0_EB |
BIT_I2C0_EB |
BIT_SPI2_EB |
BIT_UART3_EB |
0);
sci_glb_clr(REG_AON_APB_APB_RTC_EB,
BIT_KPD_RTC_EB |
BIT_KPD_EB |
BIT_EFUSE_EB |
0);
sci_glb_clr(REG_AON_APB_APB_EB0,
BIT_AUDIF_EB |
BIT_VBC_EB |
BIT_PWM3_EB |
BIT_PWM1_EB |
0);
sci_glb_clr(REG_AON_APB_APB_EB1,
BIT_AUX1_EB |
BIT_AUX0_EB |
0);
pr_debug("sc clock module early init ok\n");
return 0;
}
static void sdhci_sprd_enable_clock(struct sdhci_host *host, unsigned int clock)
{
#ifndef CONFIG_MACH_SPX35FPGA
struct sprd_host_data *host_data= sdhci_priv(host);
if(clock == 0){
if (host_data->clk_enable) {
sdhci_sdclk_enable(host, 0);
clk_disable(host->clk);
pr_debug("******* %s, call clk_disable*******\n", mmc_hostname(host->mmc));
host->clock = 0;
host_data->clk_enable = 0;
}
}else{
if (0 == host_data->clk_enable) {
clk_enable(host->clk);
pr_debug("******* %s, call clk_enable*******\n", mmc_hostname(host->mmc));
sdhci_sdclk_enable(host, 1);
host_data->clk_enable = 1;
}
}
pr_debug("clock:%d, host->clock:%d, AHB_CTL1:0x%x\n", clock,host->clock,
sci_glb_raw_read(REG_AP_AHB_AHB_EB));
#endif
return;
}
int __init sc8825_regulator_init(void)
{
static struct platform_device sc8825_regulator_device = {
.name = "sprd-regulator",
.id = -1,
};
return platform_device_register(&sc8825_regulator_device);
}
int __init sc8825_clock_init_early(void)
{
pr_info("ahb ctl0 %08x, ctl2 %08x glb gen0 %08x gen1 %08x clk_en %08x\n",
sci_glb_raw_read(REG_AHB_AHB_CTL0),
sci_glb_raw_read(REG_AHB_AHB_CTL2),
sci_glb_raw_read(REG_GLB_GEN0),
sci_glb_raw_read(REG_GLB_GEN1),
sci_glb_raw_read(REG_GLB_CLK_EN));
/* FIXME: Force disable all unused clocks */
sci_glb_clr(REG_AHB_AHB_CTL0,
BIT_AXIBUSMON2_EB |
BIT_AXIBUSMON1_EB |
BIT_AXIBUSMON0_EB |
// BIT_EMC_EB |
// BIT_AHB_ARCH_EB |
// BIT_SPINLOCK_EB |
BIT_SDIO2_EB |
BIT_EMMC_EB |
// BIT_DISPC_EB |
BIT_G3D_EB |
BIT_SDIO1_EB |
BIT_DRM_EB |
BIT_BUSMON4_EB |
BIT_BUSMON3_EB |
BIT_BUSMON2_EB |
BIT_ROT_EB |
BIT_VSP_EB |
BIT_ISP_EB |
BIT_BUSMON1_EB |
BIT_DCAM_MIPI_EB |
BIT_CCIR_EB |
BIT_NFC_EB |
BIT_BUSMON0_EB |
// BIT_DMA_EB |
// BIT_USBD_EB |
BIT_SDIO0_EB |
// BIT_LCDC_EB |
BIT_CCIR_IN_EB |
BIT_DCAM_EB |
0);
sci_glb_clr(REG_AHB_AHB_CTL2,
// BIT_DISPMTX_CLK_EN |
BIT_MMMTX_CLK_EN |
// BIT_DISPC_CORE_CLK_EN|
// BIT_LCDC_CORE_CLK_EN|
BIT_ISP_CORE_CLK_EN |
BIT_VSP_CORE_CLK_EN |
BIT_DCAM_CORE_CLK_EN|
0);
sci_glb_clr(REG_AHB_AHB_CTL3,
// BIT_CLK_ULPI_EN |
// BIT_CLK_USB_REF_EN |
0);
sci_glb_clr(REG_GLB_GEN0,
BIT_IC3_EB |
BIT_IC2_EB |
BIT_IC1_EB |
// BIT_RTC_TMR_EB |
// BIT_RTC_SYST0_EB |
BIT_RTC_KPD_EB |
BIT_IIS1_EB |
// BIT_RTC_EIC_EB |
BIT_UART2_EB |
// BIT_UART1_EB |
BIT_UART0_EB |
// BIT_SYST0_EB |
BIT_SPI1_EB |
BIT_SPI0_EB |
// BIT_SIM1_EB |
// BIT_EPT_EB |
BIT_CCIR_MCLK_EN |
// BIT_PINREG_EB |
BIT_IIS0_EB |
// BIT_MCU_DSP_RST |
// BIT_EIC_EB |
BIT_KPD_EB |
BIT_EFUSE_EB |
// BIT_ADI_EB |
// BIT_GPIO_EB |
BIT_I2C0_EB |
// BIT_SIM0_EB |
// BIT_TMR_EB |
BIT_SPI2_EB |
BIT_UART3_EB |
0);
sci_glb_clr(REG_AHB_CA5_CFG,
// BIT_CA5_CLK_DBG_EN |
0);
sci_glb_clr(REG_GLB_GEN1,
BIT_AUDIF_AUTO_EN |
BIT_VBC_EN |
BIT_AUD_TOP_EB |
BIT_AUD_IF_EB |
BIT_CLK_AUX1_EN |
BIT_CLK_AUX0_EN |
0);
sci_glb_clr(REG_GLB_CLK_EN,
BIT_PWM3_EB |
// BIT_PWM2_EB |
BIT_PWM1_EB |
// BIT_PWM0_EB |
0);
sci_glb_clr(REG_GLB_PCTRL,
// BIT_MCU_MPLL_EN |
// BIT_MCU_TDPLL_EN |
// BIT_MCU_DPLL_EN |
BIT_MCU_GPLL_EN); /* clk_gpu */
sci_glb_set(REG_GLB_TD_PLL_CTL,
// BIT_TDPLL_DIV2OUT_FORCE_PD | /* clk_384m */
// BIT_TDPLL_DIV3OUT_FORCE_PD | /* clk_256m */
// BIT_TDPLL_DIV4OUT_FORCE_PD | /* clk_192m */
// BIT_TDPLL_DIV5OUT_FORCE_PD | /* clk_153p6m */
0);
printk("sc8825 clock module early init ok\n");
return 0;
}
int __init __clock_init_early(void)
{
#if defined(CONFIG_ARCH_SCX15)
#else
pr_info("ahb ctl0 %08x, ctl2 %08x glb aon apb0 %08x aon apb1 %08x clk_en %08x\n",
sci_glb_raw_read(REG_AP_AHB_AHB_EB),
sci_glb_raw_read(REG_AP_AHB_AHB_RST),
sci_glb_raw_read(REG_AON_APB_APB_EB0),
sci_glb_raw_read(REG_AON_APB_APB_EB1),
sci_glb_raw_read(REG_AON_CLK_PUB_AHB_CFG));
#endif
sci_glb_clr(REG_AP_AHB_AHB_EB,
BIT_BUSMON2_EB |
BIT_BUSMON1_EB |
BIT_BUSMON0_EB |
//BIT_SPINLOCK_EB |
BIT_GPS_EB |
//BIT_EMMC_EB |
//BIT_SDIO2_EB |
//BIT_SDIO1_EB |
//BIT_SDIO0_EB |
BIT_DRM_EB |
BIT_NFC_EB |
//BIT_DMA_EB |
//BIT_USB_EB |
//BIT_GSP_EB |
//BIT_DISPC1_EB |
//BIT_DISPC0_EB |
//BIT_DSI_EB |
0);
sci_glb_clr(REG_AP_APB_APB_EB,
BIT_INTC3_EB |
BIT_INTC2_EB |
BIT_INTC1_EB |
BIT_IIS1_EB |
BIT_UART2_EB |
BIT_UART0_EB |
BIT_SPI1_EB |
BIT_SPI0_EB |
BIT_IIS0_EB |
BIT_I2C0_EB |
BIT_SPI2_EB |
BIT_UART3_EB |
0);
sci_glb_clr(REG_AON_APB_APB_RTC_EB,
BIT_KPD_RTC_EB |
BIT_KPD_EB |
BIT_EFUSE_EB |
0);
sci_glb_clr(REG_AON_APB_APB_EB0,
BIT_AUDIF_EB |
BIT_VBC_EB |
BIT_PWM3_EB |
BIT_PWM1_EB |
0);
sci_glb_clr(REG_AON_APB_APB_EB1,
BIT_AUX1_EB |
BIT_AUX0_EB |
0);
printk("sc clock module early init ok\n");
return 0;
}
int mmc_go_idle(struct mmc_host *host)
{
int err;
struct mmc_command cmd = {0};
#ifdef CONFIG_MMC_SDHCI_SCX35
unsigned int tmp_flag = 0, reg_val = 0;
#endif
/*
* Non-SPI hosts need to prevent chipselect going active during
* GO_IDLE; that would put chips into SPI mode. Remind them of
* that in case of hardware that won't pull up DAT3/nCS otherwise.
*
* SPI hosts ignore ios.chip_select; it's managed according to
* rules that must accommodate non-MMC slaves which this layer
* won't even know about.
*/
if (!mmc_host_is_spi(host)) {
mmc_set_chip_select(host, MMC_CS_HIGH);
#ifdef CONFIG_MMC_SDHCI_SCX35
/* if sdio0 set data[3] to gpio out mode, and data is 1 , for shark*/
if ((host->pm_flags & MMC_PM_ONLY_USED_SDIO0_SHARK) != 0) {
tmp_flag = 0;
if ((sci_glb_raw_read(REG_AON_APB_APB_EB0) & BIT_GPIO_EB) == 0) {
sci_glb_set(REG_AON_APB_APB_EB0, BIT_GPIO_EB);
tmp_flag |= 1 << 0;
}
if ((sci_glb_raw_read(REG_AON_APB_APB_EB0) & BIT_PIN_EB) == 0) {
sci_glb_set(REG_AON_APB_APB_EB0, BIT_PIN_EB);
tmp_flag |= 1 << 1;
}
/* set sdio0 data[3] to gpio mode*/
reg_val = __raw_readl( SPRD_PIN_BASE + 0x1E0 );
__raw_writel( 0x30, SPRD_PIN_BASE + 0x1E0 );
/* set gpio output mode ,and out put 1 */
sci_glb_set((CTL_GPIO_BASE + 0x308), (1 << 4));
sci_glb_set((CTL_GPIO_BASE + 0x304), (1 << 4));
sci_glb_set((CTL_GPIO_BASE + 0x300), (1 << 4));
}
#endif
mmc_delay(1);
}
cmd.opcode = MMC_GO_IDLE_STATE;
cmd.arg = 0;
cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_NONE | MMC_CMD_BC;
err = mmc_wait_for_cmd(host, &cmd, 0);
mmc_delay(1);
if (!mmc_host_is_spi(host)) {
mmc_set_chip_select(host, MMC_CS_DONTCARE);
#ifdef CONFIG_MMC_SDHCI_SCX35
/* if sdio0 set data[3] to gpio out mode, and data is 1 , for shark*/
if ((host->pm_flags & MMC_PM_ONLY_USED_SDIO0_SHARK) != 0) {
if ((tmp_flag & 1) != 0) {
sci_glb_clr(REG_AON_APB_APB_EB0, BIT_GPIO_EB);
}
if ((tmp_flag & (1 << 1)) != 0) {
sci_glb_clr(REG_AON_APB_APB_EB0, BIT_PIN_EB);
}
/* set sdio0 data[3] to sdio data pin*/
__raw_writel( reg_val, SPRD_PIN_BASE + 0x1E0 );
}
#endif
mmc_delay(1);
}
host->use_spi_crc = 0;
return err;
}
static void print_gr(void)
{
u32 val = sci_glb_read(REG_GLB_GEN0, -1UL);
printk("##: GR_GEN0 = %08x.\n", val);
if (val & GEN0_UART3_EN) printk("GEN0_UART3_EN =1.\n");
if (val & GEN0_SPI2_EN) printk("GEN0_SPI2_EN =1.\n");
if (val & GEN0_TIMER_EN) printk("GEN0_TIMER_EN =1.\n");
if (val & GEN0_SIM0_EN) printk("GEN0_SIM0_EN =1.\n");
if (val & GEN0_I2C_EN) printk("GEN0_I2C_EN =1.\n");
if (val & GEN0_GPIO_EN) printk("GEN0_GPIO_EN =1.\n");
if (val & GEN0_ADI_EN) printk("GEN0_ADI_EN =1.\n");
if (val & GEN0_EFUSE_EN) printk("GEN0_EFUSE_EN =1.\n");
if (val & GEN0_KPD_EN) printk("GEN0_KPD_EN =1.\n");
if (val & GEN0_EIC_EN) printk("GEN0_EIC_EN =1.\n");
if (val & GEN0_I2S0_EN) printk("GEN0_I2S0_EN =1.\n");
if (val & GEN0_PIN_EN) printk("GEN0_PIN_EN =1.\n");
if (val & GEN0_CCIR_MCLK_EN) printk("GEN0_CCIR_MCLK_EN =1.\n");
if (val & GEN0_EPT_EN) printk("GEN0_EPT_EN =1.\n");
if (val & GEN0_SIM1_EN) printk("GEN0_SIM1_EN =1.\n");
if (val & GEN0_SPI0_EN) printk("GEN0_SPI0_EN =1.\n");
if (val & GEN0_SPI1_EN) printk("GEN0_SPI1_EN =1.\n");
if (val & GEN0_SYST_EN) printk("GEN0_SYST_EN =1.\n");
if (val & GEN0_UART0_EN) printk("GEN0_UART0_EN =1.\n");
if (val & GEN0_UART1_EN) printk("GEN0_UART1_EN =1.\n");
if (val & GEN0_UART2_EN) printk("GEN0_UART2_EN =1.\n");
if (val & GEN0_VB_EN) printk("GEN0_VB_EN =1.\n");
if (val & GEN0_EIC_RTC_EN) printk("GEN0_EIC_RTC_EN =1.\n");
if (val & GEN0_I2S1_EN) printk("GEN0_I2S1_EN =1.\n");
if (val & GEN0_KPD_RTC_EN) printk("GEN0_KPD_RTC_EN =1.\n");
if (val & GEN0_SYST_RTC_EN) printk("GEN0_SYST_RTC_EN =1.\n");
if (val & GEN0_TMR_RTC_EN) printk("GEN0_TMR_RTC_EN =1.\n");
if (val & GEN0_I2C1_EN) printk("GEN0_I2C1_EN =1.\n");
if (val & GEN0_I2C2_EN) printk("GEN0_I2C2_EN =1.\n");
if (val & GEN0_I2C3_EN) printk("GEN0_I2C3_EN =1.\n");
val = sci_glb_read(REG_GLB_GEN1, -1UL);
printk("##: REG_GLB_GEN1 = %08x.\n", val);
if (val & BIT_CLK_AUX0_EN ) printk(" CLK_AUX0_EN =1.\n");
if (val & BIT_CLK_AUX1_EN ) printk(" CLK_AUX1_EN =1.\n");
if (val & BIT_AUD_IF_EB ) printk(" AUD_IF_EB =1.\n");
if (val & BIT_AUD_TOP_EB ) printk(" AUD_TOP_EB =1.\n");
if (val & BIT_VBC_EN ) printk(" VBC_EN =1.\n");
if (val & BIT_AUDIF_AUTO_EN ) printk(" AUDIF_AUTO_EN =1.\n");
val = sci_glb_read(REG_GLB_CLK_EN, -1UL);
printk("##: GR_CLK_EN = %08x.\n", val);
if (val & CLK_PWM0_EN) printk("CLK_PWM0_EN =1.\n");
if (val & CLK_PWM1_EN) printk("CLK_PWM1_EN = 1.\n");
if (val & CLK_PWM2_EN) printk("CLK_PWM2_EN = 1.\n");
if (val & CLK_PWM3_EN) printk("CLK_PWM3_EN = 1.\n");
val = sci_glb_read(REG_GLB_BUSCLK, -1UL);
printk("##: GR_BUSCLK_ALM = %08x.\n", val);
if (val & ARM_VB_MCLKON) printk("ARM_VB_MCLKON =1.\n");
if (val & ARM_VB_DA0ON) printk("ARM_VB_DA0ON = 1.\n");
if (val & ARM_VB_DA1ON) printk("ARM_VB_DA1ON = 1.\n");
if (val & ARM_VB_ADCON) printk("ARM_VB_ADCON = 1.\n");
if (val & ARM_VB_ANAON) printk("ARM_VB_ANAON = 1.\n");
if (val & ARM_VB_ACC) printk("ARM_VB_ACC = 1.\n");
val = sci_glb_read(REG_GLB_CLK_GEN5, -1UL);
printk("##: GR_CLK_GEN5 = %08x.\n", val);
if (val & BIT(9)) printk("LDO_USB_PD =1.\n");
val = sci_glb_raw_read(REG_GLB_PCTRL);
printk("##: GLB_PCTL = %08x.\n", val);
if (val & BIT_MCU_MPLL_EN) printk("MCU_MPLL = 1.\n");
if (val & BIT_MCU_GPLL_EN) printk("MCU_GPLL = 1.\n");
if (val & BIT_MCU_DPLL_EN) printk("MCU_DPLL = 1.\n");
if (val & BIT_MCU_TDPLL_EN) printk("MCU_TDPLL = 1.\n");
val = sci_glb_raw_read(REG_GLB_TD_PLL_CTL);
printk("##: GLB_TD_PLL_CTL = %08x.\n", val);
if (!(val & BIT_TDPLL_DIV2OUT_FORCE_PD)) printk("clk_384m = 1.\n");
if (!(val & BIT_TDPLL_DIV3OUT_FORCE_PD)) printk("clk_256m = 1.\n");
if (!(val & BIT_TDPLL_DIV4OUT_FORCE_PD)) printk("clk_192m = 1.\n");
if (!(val & BIT_TDPLL_DIV5OUT_FORCE_PD)) printk("clk_153p6m = 1.\n");
val = sci_glb_read(REG_GLB_POWCTL1, -1UL);
printk("##: GR_POWCTL1 = %08x.\n", val);
val = sci_glb_read(REG_GLB_M_PLL_CTL0, -1UL);
printk("##: REG_GLB_M_PLL_CTL0 = %08x.\n", val);
val = sci_glb_read(REG_GLB_MM_PWR_CTL, -1UL);
printk("##: REG_GLB_MM_PWR_CTL = %08x.\n", val);
val = sci_glb_read(REG_GLB_CEVA_L1RAM_PWR_CTL, -1UL);
printk("##: REG_GLB_CEVA_L1RAM_PWR_CTL = %08x.\n", val);
val = sci_glb_read(REG_GLB_GSM_PWR_CTL, -1UL);
printk("##: REG_GLB_GSM_PWR_CTL = %08x.\n", val);
val = sci_glb_read(REG_GLB_TD_PWR_CTL, -1UL);
printk("##: GR_TD_PWR_CTRL = %08x.\n", val);
val = sci_glb_read(REG_GLB_PERI_PWR_CTL, -1UL);
printk("##: GR_PERI_PWR_CTRL = %08x.\n", val);
val = sci_glb_read(REG_GLB_ARM_SYS_PWR_CTL, -1UL);
printk("##: GR_ARM_SYS_PWR_CTRL = %08x.\n", val);
val = sci_glb_read(REG_GLB_G3D_PWR_CTL, -1UL);
printk("##: GR_G3D_PWR_CTRL = %08x.\n", val);
}
