static void bfin_sdh_set_ios(struct mmc *mmc) { u16 cfg = 0; u16 clk_ctl = 0; if (mmc->bus_width == 4) { cfg = bfin_read_SDH_CFG(); cfg &= ~0x80; cfg |= 0x40; bfin_write_SDH_CFG(cfg); clk_ctl |= WIDE_BUS; } bfin_write_SDH_CLK_CTL(clk_ctl); sdh_set_clk(mmc->clock); }
static void bfin_sdh_set_ios(struct mmc *mmc) { u16 cfg = 0; u16 clk_ctl = 0; if (mmc->bus_width == 4) { cfg = bfin_read_SDH_CFG(); #ifndef RSI_BLKSZ cfg &= ~PD_SDDAT3; #endif cfg |= PUP_SDDAT3; bfin_write_SDH_CFG(cfg); clk_ctl |= WIDE_BUS_4; } bfin_write_SDH_CLK_CTL(clk_ctl); sdh_set_clk(mmc->clock); }