phys_size_t initdram(int board) { register uint reg; int tr1_bank1, tr1_bank2; /*-------------------------------------------------------------------- * Setup some default *------------------------------------------------------------------*/ mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */ mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */ mtsdram(mem_clktr, 0x40000000); /* ?? */ mtsdram(mem_wddctr, 0x40000000); /* ?? */ /*clear this first, if the DDR is enabled by a debugger then you can not make changes. */ mtsdram(mem_cfg0, 0x00000000); /* Disable EEC */ /*-------------------------------------------------------------------- * Setup for board-specific specific mem *------------------------------------------------------------------*/ /* * Following for CAS Latency = 2.5 @ 133 MHz PLB */ mtsdram(mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */ mtsdram(mem_b1cr, 0x080a4001); /* SDBA=0x080 128MB, Mode 3, enabled */ mtsdram(mem_tr0, 0x410a4012); /* ?? */ mtsdram(mem_rtr, 0x04080000); /* ?? */ mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */ mtsdram(mem_cfg0, 0x30000000); /* Disable EEC */ udelay(400); /* Delay 200 usecs (min) */ /*-------------------------------------------------------------------- * Enable the controller, then wait for DCEN to complete *------------------------------------------------------------------*/ mtsdram(mem_cfg0, 0x80000000); /* Enable */ for (;;) { mfsdram(mem_mcsts, reg); if (reg & 0x80000000) break; } sdram_tr1_set(0x00000000, &tr1_bank1); sdram_tr1_set(0x08000000, &tr1_bank2); mtsdram(mem_tr1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800)); return CFG_SDRAM_BANKS * (CFG_KBYTES_SDRAM * 1024); /* return bytes */ }
/* * Autodetect onboard DDR SDRAM on 440 platforms * * NOTE: Some of the hardcoded values are hardware dependant, * so this should be extended for other future boards * using this routine! */ long int initdram(int board_type) { int i; int tr1_bank1; for (i=0; i<N_MB0CF; i++) { /* * Disable memory controller. */ mtsdram(mem_cfg0, 0x00000000); /* * Setup some default */ mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */ mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */ mtsdram(mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */ mtsdram(mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ /* * Following for CAS Latency = 2.5 @ 133 MHz PLB */ mtsdram(mem_b0cr, mb0cf[i].reg); mtsdram(mem_tr0, 0x41094012); mtsdram(mem_tr1, 0x80800800); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/ mtsdram(mem_rtr, 0x7e000000); /* Interval 15.20µs @ 133MHz PLB*/ mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM*/ udelay(400); /* Delay 200 usecs (min) */ /* * Enable the controller, then wait for DCEN to complete */ mtsdram(mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */ udelay(10000); if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) { /* * Optimize TR1 to current hardware environment */ sdram_tr1_set(0x00000000, &tr1_bank1); mtsdram(mem_tr1, (tr1_bank1 | 0x80800800)); #ifdef CONFIG_SDRAM_ECC ecc_init(0, mb0cf[i].size); #endif /* * OK, size detected -> all done */ return mb0cf[i].size; } } return 0; /* nothing found ! */ }
/* * Autodetect onboard DDR SDRAM on 440 platforms * * NOTE: Some of the hardcoded values are hardware dependant, * so this should be extended for other future boards * using this routine! */ phys_size_t initdram(int board_type) { int i; int tr1_bank1; #if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \ defined(CONFIG_440GR) || defined(CONFIG_440SP) /* * Soft-reset SDRAM controller. */ mtsdr(SDR0_SRST, SDR0_SRST_DMC); mtsdr(SDR0_SRST, 0x00000000); #endif for (i=0; i<N_MB0CF; i++) { /* * Disable memory controller. */ mtsdram(SDRAM0_CFG0, 0x00000000); /* * Setup some default */ mtsdram(SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */ mtsdram(SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ mtsdram(SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */ mtsdram(SDRAM0_WDDCTR, CONFIG_SYS_SDRAM0_WDDCTR); mtsdram(SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ /* * Following for CAS Latency = 2.5 @ 133 MHz PLB */ mtsdram(SDRAM0_B0CR, mb0cf[i].reg); mtsdram(SDRAM0_TR0, CONFIG_SYS_SDRAM0_TR0); mtsdram(SDRAM0_TR1, 0x80800800); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/ mtsdram(SDRAM0_RTR, CONFIG_SYS_SDRAM0_RTR); mtsdram(SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM*/ udelay(400); /* Delay 200 usecs (min) */ /* * Enable the controller, then wait for DCEN to complete */ mtsdram(SDRAM0_CFG0, CONFIG_SYS_SDRAM0_CFG0); udelay(10000); if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) { phys_size_t size = mb0cf[i].size; /* * Optimize TR1 to current hardware environment */ sdram_tr1_set(0x00000000, &tr1_bank1); mtsdram(SDRAM0_TR1, (tr1_bank1 | 0x80800800)); /* * OK, size detected. Enable second bank if * defined (assumes same type as bank 0) */ #ifdef CONFIG_SDRAM_BANK1 mtsdram(SDRAM0_CFG0, 0); mtsdram(SDRAM0_B1CR, mb0cf[i].size | mb0cf[i].reg); mtsdram(SDRAM0_CFG0, CONFIG_SYS_SDRAM0_CFG0); udelay(10000); /* * Check if 2nd bank is really available. * If the size not equal to the size of the first * bank, then disable the 2nd bank completely. */ if (get_ram_size((long *)mb0cf[i].size, mb0cf[i].size) != mb0cf[i].size) { mtsdram(SDRAM0_CFG0, 0); mtsdram(SDRAM0_B1CR, 0); mtsdram(SDRAM0_CFG0, CONFIG_SYS_SDRAM0_CFG0); udelay(10000); } else { /* * We have two identical banks, so the size * is twice the bank size */ size = 2 * size; } #endif #ifdef CONFIG_SDRAM_ECC ecc_init(0, size); #endif /* * OK, size detected -> all done */ return size; } } return 0; /* nothing found ! */ }