/* Used by the clock framework during CORE DPLL changes */
void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode)
{
unsigned long dll_cnt;
u32 fast_dll = 0;
/* DDR = 1, SDR = 0 */
mem_timings.m_type = !((sdrc_read_reg(SDRC_MR_0) & 0x3) == 0x1);
/* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others.
* In the case of 2422, its ok to use CS1 instead of CS0.
*/
if (cpu_is_omap2422())
mem_timings.base_cs = 1;
else
mem_timings.base_cs = 0;
if (mem_timings.m_type != M_DDR)
return;
/* With DDR we need to determine the low frequency DLL value */
if (((mem_timings.fast_dll_ctrl & (1 << 2)) == M_LOCK_CTRL))
mem_timings.dll_mode = M_UNLOCK;
else
mem_timings.dll_mode = M_LOCK;
if (mem_timings.base_cs == 0) {
fast_dll = sdrc_read_reg(SDRC_DLLA_CTRL);
dll_cnt = sdrc_read_reg(SDRC_DLLA_STATUS) & 0xff00;
} else {
fast_dll = sdrc_read_reg(SDRC_DLLB_CTRL);
dll_cnt = sdrc_read_reg(SDRC_DLLB_STATUS) & 0xff00;
}
if (force_lock_to_unlock_mode) {
fast_dll &= ~0xff00;
fast_dll |= dll_cnt; /* Current lock mode */
}
/* set fast timings with DLL filter disabled */
mem_timings.fast_dll_ctrl = (fast_dll | (3 << 8));
/* No disruptions, DDR will be offline & C-ABI not followed */
omap2_sram_ddr_init(&mem_timings.slow_dll_ctrl,
mem_timings.fast_dll_ctrl,
mem_timings.base_cs,
force_lock_to_unlock_mode);
mem_timings.slow_dll_ctrl &= 0xff00; /* Keep lock value */
/* Turn status into unlock ctrl */
mem_timings.slow_dll_ctrl |=
((mem_timings.fast_dll_ctrl & 0xF) | (1 << 2));
/* 90 degree phase for anything below 133Mhz + disable DLL filter */
mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8));
}
/* Return the size of memory on a CS */
unsigned int omap2_sdrc_cs_size(int cs)
{
unsigned int mcfg;
if (cs)
mcfg = sdrc_read_reg(SDRC_MCFG_1);
else
mcfg = sdrc_read_reg(SDRC_MCFG_0);
printk("%s: cs %d = %x\n", __FUNCTION__, cs, mcfg);
mcfg >>= 8;
mcfg &= 0x2ff;
return (mcfg << 21); /* MCFG RAMSIZE field is in 2MB chunks */
}
/**
* omap2_sdrc_init - initialize SMS, SDRC devices on boot
* @sdrc_cs[01]: pointers to a null-terminated list of struct omap_sdrc_params
* Support for 2 chip selects timings
*
* Turn on smart idle modes for SDRAM scheduler and controller.
* Program a known-good configuration for the SDRC to deal with buggy
* bootloaders.
*/
void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
struct omap_sdrc_params *sdrc_cs1)
{
u32 l;
l = sms_read_reg(SMS_SYSCONFIG);
l &= ~(0x3 << 3);
l |= (0x2 << 3);
sms_write_reg(l, SMS_SYSCONFIG);
l = sdrc_read_reg(SDRC_SYSCONFIG);
l &= ~(0x3 << 3);
l |= (0x2 << 3);
sdrc_write_reg(l, SDRC_SYSCONFIG);
sdrc_init_params_cs0 = sdrc_cs0;
sdrc_init_params_cs1 = sdrc_cs1;
/* XXX Enable SRFRONIDLEREQ here also? */
/*
* PWDENA should not be set due to 34xx erratum 1.150 - PWDENA
* can cause random memory corruption
*/
l = (1 << SDRC_POWER_PAGEPOLICY_SHIFT);
sdrc_write_reg(l, SDRC_POWER);
omap2_sms_save_context();
}
int __init omap3_sdrc_init(struct omap3_sdrc_params *sdrc_cs0,
struct omap3_sdrc_params *sdrc_cs1)
{
u32 l;
/* This function does the task same as omap2_init_common_devices() of
* <linux>/arch/arm/mach-omap2/io.c
*/
if(!omap3_sdrc_base) {
omap3_sdrc_base = vmm_host_iomap(OMAP3_SDRC_BASE,
OMAP3_SDRC_SIZE);
if(!omap3_sdrc_base) {
return VMM_EFAIL;
}
}
if(!omap3_sms_base) {
omap3_sms_base = vmm_host_iomap(OMAP3_SMS_BASE,
OMAP3_SMS_SIZE);
if(!omap3_sms_base) {
return VMM_EFAIL;
}
}
/* Initiaize SDRC as per omap2_sdrc_init() of
* <linux>/arch/arm/mach-omap2/sdrc.c
*/
l = sms_read_reg(SMS_SYSCONFIG);
l &= ~(0x3 << 3);
l |= (0x2 << 3);
sms_write_reg(l, SMS_SYSCONFIG);
l = sdrc_read_reg(SDRC_SYSCONFIG);
l &= ~(0x3 << 3);
l |= (0x2 << 3);
sdrc_write_reg(l, SDRC_SYSCONFIG);
sdrc_init_params_cs0 = sdrc_cs0;
sdrc_init_params_cs1 = sdrc_cs1;
/* XXX Enable SRFRONIDLEREQ here also? */
/*
* PWDENA should not be set due to 34xx erratum 1.150 - PWDENA
* can cause random memory corruption
*/
l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) |
(1 << SDRC_POWER_PAGEPOLICY_SHIFT);
sdrc_write_reg(l, SDRC_POWER);
/* FIXME: Reprogram SDRC timing parameters as per
* _omap2_init_reprogram_sdrc() function of
* <linux>/arch/arm/mach-omap2/io.c
*/
return VMM_OK;
}
/*
* Check the DLL lock state, and return tue if running in unlock mode.
* This is needed to compensate for the shifted DLL value in unlock mode.
*/
u32 omap2xxx_sdrc_dll_is_unlocked(void)
{
/* dlla and dllb are a set */
u32 dll_state = sdrc_read_reg(SDRC_DLLA_CTRL);
if ((dll_state & (1 << 2)) == (1 << 2))
return 1;
else
return 0;
}
/*
* Check the DLL lock state, and return tue if running in unlock mode.
* This is needed to compensate for the shifted DLL value in unlock mode.
*/
u32 omap2_dll_force_needed(void)
{
/* dlla and dllb are a set */
u32 dll_state = sdrc_read_reg(SDRC_DLLA_CTRL);
if ((dll_state & (1 << 2)) == (1 << 2))
return 1;
else
return 0;
}
static int omap2_enter_full_retention(void)
{
u32 l;
clk_disable(osc_ck);
omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
omap2_gpio_prepare_for_idle(0);
if (omap_irq_pending())
goto no_sleep;
omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
OMAP_SDRC_REGADDR(SDRC_POWER));
no_sleep:
omap2_gpio_resume_after_idle();
clk_enable(osc_ck);
omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
omap2_prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST);
l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
if (l & 0x01)
omap2_prm_write_mod_reg(0x01, OCP_MOD,
OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
if (l & 0x20)
omap2_prm_write_mod_reg(0x20, OCP_MOD,
OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
omap2_prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
return 0;
}
/* turn on smart idle modes for SDRAM scheduler and controller */
void __init omap2_init_memory(void)
{
u32 l;
l = sms_read_reg(SMS_SYSCONFIG);
l &= ~(0x3 << 3);
l |= (0x2 << 3);
sms_write_reg(l, SMS_SYSCONFIG);
l = sdrc_read_reg(SDRC_SYSCONFIG);
l &= ~(0x3 << 3);
l |= (0x2 << 3);
sdrc_write_reg(l, SDRC_SYSCONFIG);
}
/**
* omap2_sdrc_init - initialize SMS, SDRC devices on boot
* @sp: pointer to a null-terminated list of struct omap_sdrc_params
*
* Turn on smart idle modes for SDRAM scheduler and controller.
* Program a known-good configuration for the SDRC to deal with buggy
* bootloaders.
*/
void __init omap2_sdrc_init(struct omap_sdrc_params *sp)
{
u32 l;
l = sms_read_reg(SMS_SYSCONFIG);
l &= ~(0x3 << 3);
l |= (0x2 << 3);
sms_write_reg(l, SMS_SYSCONFIG);
l = sdrc_read_reg(SDRC_SYSCONFIG);
l &= ~(0x3 << 3);
l |= (0x2 << 3);
sdrc_write_reg(l, SDRC_SYSCONFIG);
sdrc_init_params = sp;
/* XXX Enable SRFRONIDLEREQ here also? */
l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) |
(1 << SDRC_POWER_PWDENA_SHIFT) |
(1 << SDRC_POWER_PAGEPOLICY_SHIFT);
sdrc_write_reg(l, SDRC_POWER);
omap2_sms_save_context();
}
static void omap2_enter_full_retention(void)
{
u32 l;
struct timespec ts_preidle, ts_postidle, ts_idle;
/* There is 1 reference hold for all children of the oscillator
* clock, the following will remove it. If no one else uses the
* oscillator itself it will be disabled if/when we enter retention
* mode.
*/
clk_disable(osc_ck);
/* Clear old wake-up events */
/* REVISIT: These write to reserved bits? */
omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
/*
* Set MPU powerdomain's next power state to RETENTION;
* preserve logic state during retention
*/
pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
/* Workaround to kill USB */
l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
omap2_gpio_prepare_for_idle(0);
if (omap2_pm_debug) {
omap2_pm_dump(0, 0, 0);
getnstimeofday(&ts_preidle);
}
/* One last check for pending IRQs to avoid extra latency due
* to sleeping unnecessarily. */
if (omap_irq_pending())
goto no_sleep;
/* Block console output in case it is on one of the OMAP UARTs */
if (!is_suspending())
if (!console_trylock())
goto no_sleep;
omap_uart_prepare_idle(0);
omap_uart_prepare_idle(1);
omap_uart_prepare_idle(2);
/* Jump to SRAM suspend code */
omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
OMAP_SDRC_REGADDR(SDRC_POWER));
omap_uart_resume_idle(2);
omap_uart_resume_idle(1);
omap_uart_resume_idle(0);
if (!is_suspending())
console_unlock();
no_sleep:
if (omap2_pm_debug) {
unsigned long long tmp;
getnstimeofday(&ts_postidle);
ts_idle = timespec_sub(ts_postidle, ts_preidle);
tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC;
omap2_pm_dump(0, 1, tmp);
}
omap2_gpio_resume_after_idle();
clk_enable(osc_ck);
/* clear CORE wake-up events */
omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
/* wakeup domain events - bit 1: GPT1, bit5 GPIO */
omap2_prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST);
/* MPU domain wake events */
l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
if (l & 0x01)
omap2_prm_write_mod_reg(0x01, OCP_MOD,
OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
if (l & 0x20)
omap2_prm_write_mod_reg(0x20, OCP_MOD,
OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
/* Mask future PRCM-to-MPU interrupts */
omap2_prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
}
static int omap3_enter_idle(struct cpuidle_device *dev,
struct cpuidle_state *state)
{
struct omap3_processor_cx *cx;
u8 cur_per_state, cur_neon_state, pre_neon_state, pre_per_state;
struct timespec ts_preidle, ts_postidle, ts_idle;
u32 fclken_core, iclken_core, fclken_per, iclken_per;
u32 sdrcpwr_val, sdrc_power_register = 0x0;
int wakeup_latency;
int core_sleep_flg = 0;
u32 per_ctx_saved = 0;
int ret = -1;
#ifdef CONFIG_ENABLE_SWLATENCY_MEASURE
int idle_status = 0;
#endif
local_irq_disable();
local_fiq_disable();
if (need_resched()) {
local_irq_enable();
local_fiq_enable();
return 0;
}
#ifdef CONFIG_ENABLE_SWLATENCY_MEASURE
sw_latency_arr[swlat_arr_wrptr].sleep_start =
omap_32k_sync_timer_read();
#endif
PM_PREPWSTST_MPU = 0xFF;
PM_PREPWSTST_CORE = 0xFF;
PM_PREPWSTST_NEON = 0xFF;
PM_PREPWSTST_PER = 0xFF;
cx = cpuidle_get_statedata(state);
target_state.mpu_state = cx->mpu_state;
target_state.core_state = cx->core_state;
/* take a time marker for residency */
getnstimeofday(&ts_preidle);
if (cx->type == OMAP3_STATE_C0) {
omap_sram_idle();
goto return_sleep_time;
}
if (cx->type > OMAP3_STATE_C1)
sched_clock_idle_sleep_event(); /* about to enter deep idle */
correct_target_state();
wakeup_latency = cx->wakeup_latency;
if (target_state.core_state != cx->core_state) {
/* Currently, this can happen only for core_off */
/* Adjust wakeup latency to that of core_cswr state */
/* Hard coded now and needs to be made more generic */
/* omap3_power_states[4] is CSWR for core */
wakeup_latency = omap3_power_states[4].wakeup_latency;
}
/* Reprogram next wake up tick to adjust for wake latency */
if (wakeup_latency > 1000) {
struct tick_device *d = tick_get_device(smp_processor_id());
ktime_t adjust, next, now = ktime_get();
if (ktime_to_ns(ktime_sub(d->evtdev->next_event, now)) >
(wakeup_latency * 1000 + NSEC_PER_MSEC)) {
adjust = ktime_set(0, (wakeup_latency * 1000));
next = ktime_sub(d->evtdev->next_event, adjust);
clockevents_program_event(d->evtdev, next, now);
}
}
/* Check for pending interrupts. If there is an interrupt, return */
if (INTCPS_PENDING_IRQ0 | INTCPS_PENDING_IRQ1 | INTCPS_PENDING_IRQ2)
goto return_sleep_time;
prcm_get_power_domain_state(DOM_PER, &cur_per_state);
prcm_get_power_domain_state(DOM_NEON, &cur_neon_state);
fclken_core = CM_FCLKEN1_CORE;
iclken_core = CM_ICLKEN1_CORE;
fclken_per = CM_FCLKEN_PER;
iclken_per = CM_ICLKEN_PER;
/* If target state if core_off, save registers
* before changing anything
*/
if (target_state.core_state >= PRCM_CORE_OSWR_MEMRET) {
prcm_save_registers(&target_state);
omap_uart_save_ctx(0);
omap_uart_save_ctx(1);
}
/* Check for pending interrupts. If there is an interrupt, return */
if (INTCPS_PENDING_IRQ0 | INTCPS_PENDING_IRQ1 | INTCPS_PENDING_IRQ2)
goto return_sleep_time;
/* Program MPU and NEON to target state */
if (target_state.mpu_state > PRCM_MPU_ACTIVE) {
if ((cur_neon_state == PRCM_ON) &&
(target_state.neon_state != PRCM_ON)) {
if (target_state.neon_state == PRCM_OFF)
omap3_save_neon_context();
#ifdef CONFIG_HW_SUP_TRANS
/* Facilitating SWSUP RET, from HWSUP mode */
prcm_set_clock_domain_state(DOM_NEON,
PRCM_NO_AUTO, PRCM_FALSE);
prcm_set_power_domain_state(DOM_NEON, PRCM_ON,
PRCM_FORCE);
#endif
prcm_force_power_domain_state(DOM_NEON,
target_state.neon_state);
}
#ifdef CONFIG_MPU_OFF
/* Populate scrathpad restore address */
*(scratchpad_restore_addr) = restore_pointer_address;
#endif
if (target_state.core_state > PRCM_CORE_CSWR_MEMRET) {
ret = omap3_save_secure_ram_context(
target_state.core_state);
if (ret)
printk(KERN_ERR "omap3_save_secure_ram_context"
"failed in idle %x\n", ret);
if (core_off_notification != NULL)
core_off_notification(PRCM_TRUE);
}
prcm_set_mpu_domain_state(target_state.mpu_state);
}
/* Check for pending interrupts. If there is an interrupt, return */
if (INTCPS_PENDING_IRQ0 | INTCPS_PENDING_IRQ1 | INTCPS_PENDING_IRQ2)
goto restore;
/* Program CORE and PER to target state */
if (target_state.core_state > PRCM_CORE_ACTIVE) {
/* Log core sleep attmept */
core_sleep_flg = 1;
#ifdef CONFIG_OMAP_SMARTREFLEX
disable_smartreflex(SR1_ID);
disable_smartreflex(SR2_ID);
#endif
/* Workaround for Silicon Errata 1.64 */
if (is_sil_rev_equal_to(OMAP3430_REV_ES1_0)) {
if (CM_CLKOUT_CTRL & 0x80)
CM_CLKOUT_CTRL &= ~(0x80);
}
prcm_set_core_domain_state(target_state.core_state);
/* Enable Autoidle for GPT1 explicitly - Errata 1.4 */
CM_AUTOIDLE_WKUP |= 0x1;
/* Disable UART-1,2 */
CM_FCLKEN1_CORE &= ~0x6000;
/* Disable HSUSB OTG ICLK explicitly*/
CM_ICLKEN1_CORE &= ~0x10;
/* Enabling IO_PAD capabilities */
PM_WKEN_WKUP |= 0x100;
if (cur_per_state == PRCM_ON && cx->type >= OMAP3_STATE_C3 &&
!(CM_FCLKEN_PER & PER_FCLK_MASK)) {
/* In ES3.1, Enable IO Daisy chain */
if (is_sil_rev_greater_than(OMAP3430_REV_ES3_0)) {
PM_WKEN_WKUP |= 0x10000;
/* Wait for daisy chain to be ready */
while ((PM_WKST_WKUP & 0x10000) == 0x0)
;
/* clear the status */
PM_WKST_WKUP &= ~0x10000;
}
omap3_save_per_context();
prcm_set_power_domain_state(DOM_PER, PRCM_OFF,
PRCM_AUTO);
per_ctx_saved = 1;
CM_FCLKEN_PER = 0;
CM_ICLKEN_PER = 0;
}
}
/* Check for pending interrupts. If there is an interrupt, return */
if (INTCPS_PENDING_IRQ0 | INTCPS_PENDING_IRQ1 | INTCPS_PENDING_IRQ2)
goto restore;
if (target_state.core_state == PRCM_CORE_OFF) {
if (!is_device_type_gp() &&
is_sil_rev_greater_than(OMAP3430_REV_ES2_1)) {
/* es3 series bug */
sdrc_power_register = sdrc_read_reg(SDRC_POWER);
sdrcpwr_val = sdrc_power_register &
~(SDRC_PWR_AUTOCOUNT_MASK |
SDRC_PWR_CLKCTRL_MASK);
lock_scratchpad_sem();
sdrcpwr_val |= 0x120;
save_to_scratchpad(SCRATHPAD_SDRCPWR_OFFSET,
sdrcpwr_val);
unlock_scratchpad_sem();
}
}
#ifdef CONFIG_ENABLE_SWLATENCY_MEASURE
sw_latency_arr[swlat_arr_wrptr].sleep_end = omap_32k_sync_timer_read();
idle_status++;
#endif
omap_sram_idle();
if (target_state.core_state == PRCM_CORE_OFF) {
if (!is_device_type_gp() &&
is_sil_rev_greater_than(OMAP3430_REV_ES2_1))
sdrc_write_reg(sdrc_power_register, SDRC_POWER);
}
restore:
/* In case of ES3.1, disable IO daisy chain */
if (is_sil_rev_greater_than(OMAP3430_REV_ES3_0) && per_ctx_saved)
PM_WKEN_WKUP &= ~(0x10000);
/* Disabling IO_PAD capabilities */
if (core_sleep_flg)
PM_WKEN_WKUP &= ~(0x100);
/* Disabling IO_PAD capabilities */
PM_WKEN_WKUP &= ~(0x100);
#ifdef OMAP3_START_RNG
/*Capture the PM_PREPWSTST_CORE to be used later
* for starting the RNG (Random Number Generator)*/
prepwst_core_rng = PM_PREPWSTST_CORE;
#endif
CM_FCLKEN1_CORE = fclken_core;
CM_ICLKEN1_CORE = iclken_core;
if (target_state.mpu_state > PRCM_MPU_ACTIVE) {
#ifdef CONFIG_MPU_OFF
/* On ES 2.0, if scrathpad is populated with valid
* pointer, warm reset does not work
* So populate scrathpad restore address only in
* cpuidle and suspend calls
*/
*(scratchpad_restore_addr) = 0x0;
#endif
prcm_set_mpu_domain_state(PRCM_MPU_ACTIVE);
if ((cur_neon_state == PRCM_ON) &&
(target_state.mpu_state > PRCM_MPU_INACTIVE)) {
prcm_force_power_domain_state(DOM_NEON, cur_neon_state);
prcm_get_pre_power_domain_state(DOM_NEON,
&pre_neon_state);
if (pre_neon_state == PRCM_OFF)
omap3_restore_neon_context();
#ifdef CONFIG_HW_SUP_TRANS
prcm_set_power_domain_state(DOM_NEON, PRCM_ON,
PRCM_AUTO);
#endif
}
}
/* Continue core restoration part, only if Core-Sleep is attempted */
if ((target_state.core_state > PRCM_CORE_ACTIVE) && core_sleep_flg) {
prcm_set_core_domain_state(PRCM_CORE_ACTIVE);
#ifdef CONFIG_OMAP_SMARTREFLEX
enable_smartreflex(SR1_ID);
enable_smartreflex(SR2_ID);
#endif
if (target_state.core_state >= PRCM_CORE_OSWR_MEMRET) {
#ifdef CONFIG_OMAP34XX_OFFMODE
context_restore_update(DOM_CORE1);
#endif
prcm_restore_registers(&target_state);
prcm_restore_core_context(target_state.core_state);
omap3_restore_core_settings();
}
/* Errata 1.4
* if the timer device gets idled which is when we
* are cutting the timer ICLK which is when we try
* to put Core to RET.
* Wait Period = 2 timer interface clock cycles +
* 1 timer functional clock cycle
* Interface clock = L4 clock. For the computation L4
* clock is assumed at 50MHz (worst case).
* Functional clock = 32KHz
* Wait Period = 2*10^-6/50 + 1/32768 = 0.000030557 = 30.557uSec
* Roundingoff the delay value to a safer 50uSec
*/
omap_udelay(GPTIMER_WAIT_DELAY);
CM_AUTOIDLE_WKUP &= ~(0x1);
if (core_off_notification != NULL)
core_off_notification(PRCM_FALSE);
}
if (cur_per_state == PRCM_ON) {
CM_FCLKEN_PER = fclken_per;
CM_ICLKEN_PER = iclken_per;
prcm_get_pre_power_domain_state(DOM_PER, &pre_per_state);
if (pre_per_state == PRCM_OFF && per_ctx_saved) {
if (enable_debug)
per_off++;
omap3_restore_per_context();
post_uart_inactivity();
#ifdef CONFIG_OMAP34XX_OFFMODE
context_restore_update(DOM_PER);
#endif
}
}
pr_debug("MPU state:%x,CORE state:%x\n", PM_PREPWSTST_MPU,
PM_PREPWSTST_CORE);
store_prepwst();
return_sleep_time:
getnstimeofday(&ts_postidle);
ts_idle = timespec_sub(ts_postidle, ts_preidle);
if (cx->type > OMAP3_STATE_C1)
sched_clock_idle_wakeup_event(timespec_to_ns(&ts_idle));
#ifdef CONFIG_ENABLE_SWLATENCY_MEASURE
if (idle_status) {
sw_latency_arr[swlat_arr_wrptr].wkup_end =
omap_32k_sync_timer_read();
sw_latency_arr[swlat_arr_wrptr].wkup_start =
wakeup_start_32ksync;
sw_latency_arr[swlat_arr_wrptr].cstate =
((PM_PREPWSTST_MPU & 0x3) << 2) |
(PM_PREPWSTST_CORE & 0x3) |
(omap_readl(0x48306CB0) << 16);
swlat_arr_wrptr++;
if (swlat_arr_wrptr == SW_LATENCY_ARR_SIZE)
swlat_arr_wrptr = 0;
}
#endif
local_irq_enable();
local_fiq_enable();
#ifdef OMAP3_START_RNG
if (!is_device_type_gp()) {
/*Start RNG after interrupts are enabled
* and only when CORE OFF was successful
*/
if (!(prepwst_core_rng & 0x3)) {
ret = omap3_start_rng();
if (ret)
printk(KERN_INFO"Failed to generate new"
" RN in idle %x\n", ret);
prepwst_core_rng = 0xFF;
}
}
#endif
return (u32)timespec_to_ns(&ts_idle)/1000;
}
static int omap2_enter_full_retention(void)
{
u32 l;
/* There is 1 reference hold for all children of the oscillator
* clock, the following will remove it. If no one else uses the
* oscillator itself it will be disabled if/when we enter retention
* mode.
*/
clk_disable(osc_ck);
/* Clear old wake-up events */
/* REVISIT: These write to reserved bits? */
omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
/*
* Set MPU powerdomain's next power state to RETENTION;
* preserve logic state during retention
*/
pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
/* Workaround to kill USB */
l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
omap2_gpio_prepare_for_idle(0);
/* One last check for pending IRQs to avoid extra latency due
* to sleeping unnecessarily. */
if (omap_irq_pending())
goto no_sleep;
/* Jump to SRAM suspend code */
omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
OMAP_SDRC_REGADDR(SDRC_POWER));
no_sleep:
omap2_gpio_resume_after_idle();
clk_enable(osc_ck);
/* clear CORE wake-up events */
omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
/* wakeup domain events - bit 1: GPT1, bit5 GPIO */
omap2_prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST);
/* MPU domain wake events */
l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
if (l & 0x01)
omap2_prm_write_mod_reg(0x01, OCP_MOD,
OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
if (l & 0x20)
omap2_prm_write_mod_reg(0x20, OCP_MOD,
OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
/* Mask future PRCM-to-MPU interrupts */
omap2_prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
return 0;
}
/* Populate the scratchpad structure with restore structure */
void omap3_save_scratchpad_contents(void)
{
void __iomem *scratchpad_address;
u32 arm_context_addr;
struct omap3_scratchpad scratchpad_contents;
struct omap3_scratchpad_prcm_block prcm_block_contents;
struct omap3_scratchpad_sdrc_block sdrc_block_contents;
/* Populate the Scratchpad contents */
scratchpad_contents.boot_config_ptr = 0x0;
if (cpu_is_omap3630())
scratchpad_contents.public_restore_ptr =
virt_to_phys(get_omap3630_restore_pointer());
else if (omap_rev() != OMAP3430_REV_ES3_0 &&
omap_rev() != OMAP3430_REV_ES3_1)
scratchpad_contents.public_restore_ptr =
virt_to_phys(get_restore_pointer());
else
scratchpad_contents.public_restore_ptr =
virt_to_phys(get_es3_restore_pointer());
if (omap_type() == OMAP2_DEVICE_TYPE_GP)
scratchpad_contents.secure_ram_restore_ptr = 0x0;
else
scratchpad_contents.secure_ram_restore_ptr =
(u32) __pa(omap3_secure_ram_storage);
scratchpad_contents.sdrc_module_semaphore = 0x0;
scratchpad_contents.prcm_block_offset = 0x2C;
scratchpad_contents.sdrc_block_offset = 0x64;
/* Populate the PRCM block contents */
prcm_block_contents.prm_clksrc_ctrl = prm_read_mod_reg(OMAP3430_GR_MOD,
OMAP3_PRM_CLKSRC_CTRL_OFFSET);
prcm_block_contents.prm_clksel = prm_read_mod_reg(OMAP3430_CCR_MOD,
OMAP3_PRM_CLKSEL_OFFSET);
prcm_block_contents.cm_clksel_core =
cm_read_mod_reg(CORE_MOD, CM_CLKSEL);
prcm_block_contents.cm_clksel_wkup =
cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
prcm_block_contents.cm_clken_pll =
cm_read_mod_reg(PLL_MOD, CM_CLKEN);
prcm_block_contents.cm_autoidle_pll =
cm_read_mod_reg(PLL_MOD, OMAP3430_CM_AUTOIDLE_PLL);
prcm_block_contents.cm_clksel1_pll =
cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL);
prcm_block_contents.cm_clksel2_pll =
cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL);
prcm_block_contents.cm_clksel3_pll =
cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3);
prcm_block_contents.cm_clken_pll_mpu =
cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL);
prcm_block_contents.cm_autoidle_pll_mpu =
cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL);
prcm_block_contents.cm_clksel1_pll_mpu =
cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL);
prcm_block_contents.cm_clksel2_pll_mpu =
cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL);
prcm_block_contents.prcm_block_size = 0x0;
/* Populate the SDRC block contents */
sdrc_block_contents.sysconfig =
(sdrc_read_reg(SDRC_SYSCONFIG) & 0xFFFF);
sdrc_block_contents.cs_cfg =
(sdrc_read_reg(SDRC_CS_CFG) & 0xFFFF);
sdrc_block_contents.sharing =
(sdrc_read_reg(SDRC_SHARING) & 0xFFFF);
sdrc_block_contents.err_type =
(sdrc_read_reg(SDRC_ERR_TYPE) & 0xFFFF);
sdrc_block_contents.dll_a_ctrl = sdrc_read_reg(SDRC_DLLA_CTRL);
sdrc_block_contents.dll_b_ctrl = 0x0;
/*
* Due to a OMAP3 errata (1.142), on EMU/HS devices SRDC should
* be programed to issue automatic self refresh on timeout
* of AUTO_CNT = 1 prior to any transition to OFF mode.
*/
if ((omap_type() != OMAP2_DEVICE_TYPE_GP)
&& (omap_rev() >= OMAP3430_REV_ES3_0))
sdrc_block_contents.power = (sdrc_read_reg(SDRC_POWER) &
~(SDRC_POWER_AUTOCOUNT_MASK|
SDRC_POWER_CLKCTRL_MASK)) |
(1 << SDRC_POWER_AUTOCOUNT_SHIFT) |
SDRC_SELF_REFRESH_ON_AUTOCOUNT;
else
sdrc_block_contents.power = sdrc_read_reg(SDRC_POWER);
sdrc_block_contents.cs_0 = 0x0;
sdrc_block_contents.mcfg_0 = sdrc_read_reg(SDRC_MCFG_0);
sdrc_block_contents.mr_0 = (sdrc_read_reg(SDRC_MR_0) & 0xFFFF);
sdrc_block_contents.emr_1_0 = 0x0;
sdrc_block_contents.emr_2_0 = 0x0;
sdrc_block_contents.emr_3_0 = 0x0;
sdrc_block_contents.actim_ctrla_0 =
sdrc_read_reg(SDRC_ACTIM_CTRL_A_0);
sdrc_block_contents.actim_ctrlb_0 =
sdrc_read_reg(SDRC_ACTIM_CTRL_B_0);
sdrc_block_contents.rfr_ctrl_0 =
sdrc_read_reg(SDRC_RFR_CTRL_0);
sdrc_block_contents.cs_1 = 0x0;
sdrc_block_contents.mcfg_1 = sdrc_read_reg(SDRC_MCFG_1);
sdrc_block_contents.mr_1 = sdrc_read_reg(SDRC_MR_1) & 0xFFFF;
sdrc_block_contents.emr_1_1 = 0x0;
sdrc_block_contents.emr_2_1 = 0x0;
sdrc_block_contents.emr_3_1 = 0x0;
sdrc_block_contents.actim_ctrla_1 =
sdrc_read_reg(SDRC_ACTIM_CTRL_A_1);
sdrc_block_contents.actim_ctrlb_1 =
sdrc_read_reg(SDRC_ACTIM_CTRL_B_1);
sdrc_block_contents.rfr_ctrl_1 =
sdrc_read_reg(SDRC_RFR_CTRL_1);
sdrc_block_contents.dcdl_1_ctrl = 0x0;
sdrc_block_contents.dcdl_2_ctrl = 0x0;
sdrc_block_contents.flags = 0x0;
sdrc_block_contents.block_size = 0x0;
arm_context_addr = virt_to_phys(omap3_arm_context);
/* Copy all the contents to the scratchpad location */
scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
memcpy_toio(scratchpad_address, &scratchpad_contents,
sizeof(scratchpad_contents));
/* Scratchpad contents being 32 bits, a divide by 4 done here */
memcpy_toio(scratchpad_address +
scratchpad_contents.prcm_block_offset,
&prcm_block_contents, sizeof(prcm_block_contents));
memcpy_toio(scratchpad_address +
scratchpad_contents.sdrc_block_offset,
&sdrc_block_contents, sizeof(sdrc_block_contents));
/*
* Copies the address of the location in SDRAM where ARM
* registers get saved during a MPU OFF transition.
*/
memcpy_toio(scratchpad_address +
scratchpad_contents.sdrc_block_offset +
sizeof(sdrc_block_contents), &arm_context_addr, 4);
}
/* Populate the scratchpad structure with restore structure */
void omap3_save_scratchpad_contents(void)
{
void __iomem *scratchpad_address;
u32 arm_context_addr;
struct omap3_scratchpad scratchpad_contents;
struct omap3_scratchpad_prcm_block prcm_block_contents;
struct omap3_scratchpad_sdrc_block sdrc_block_contents;
/*
* Populate the Scratchpad contents
*
* The "get_*restore_pointer" functions are used to provide a
* physical restore address where the ROM code jumps while waking
* up from MPU OFF/OSWR state.
* The restore pointer is stored into the scratchpad.
*/
scratchpad_contents.boot_config_ptr = 0x0;
if (cpu_is_omap3630())
scratchpad_contents.public_restore_ptr =
virt_to_phys(omap3_restore_3630);
else if (omap_rev() != OMAP3430_REV_ES3_0 &&
omap_rev() != OMAP3430_REV_ES3_1 &&
omap_rev() != OMAP3430_REV_ES3_1_2)
scratchpad_contents.public_restore_ptr =
virt_to_phys(omap3_restore);
else
scratchpad_contents.public_restore_ptr =
virt_to_phys(omap3_restore_es3);
if (omap_type() == OMAP2_DEVICE_TYPE_GP)
scratchpad_contents.secure_ram_restore_ptr = 0x0;
else
scratchpad_contents.secure_ram_restore_ptr =
(u32) __pa(omap3_secure_ram_storage);
scratchpad_contents.sdrc_module_semaphore = 0x0;
scratchpad_contents.prcm_block_offset = 0x2C;
scratchpad_contents.sdrc_block_offset = 0x64;
/* Populate the PRCM block contents */
omap3_prm_save_scratchpad_contents(prcm_block_contents.prm_contents);
omap3_cm_save_scratchpad_contents(prcm_block_contents.cm_contents);
prcm_block_contents.prcm_block_size = 0x0;
/* Populate the SDRC block contents */
sdrc_block_contents.sysconfig =
(sdrc_read_reg(SDRC_SYSCONFIG) & 0xFFFF);
sdrc_block_contents.cs_cfg =
(sdrc_read_reg(SDRC_CS_CFG) & 0xFFFF);
sdrc_block_contents.sharing =
(sdrc_read_reg(SDRC_SHARING) & 0xFFFF);
sdrc_block_contents.err_type =
(sdrc_read_reg(SDRC_ERR_TYPE) & 0xFFFF);
sdrc_block_contents.dll_a_ctrl = sdrc_read_reg(SDRC_DLLA_CTRL);
sdrc_block_contents.dll_b_ctrl = 0x0;
/*
* Due to a OMAP3 errata (1.142), on EMU/HS devices SRDC should
* be programed to issue automatic self refresh on timeout
* of AUTO_CNT = 1 prior to any transition to OFF mode.
*/
if ((omap_type() != OMAP2_DEVICE_TYPE_GP)
&& (omap_rev() >= OMAP3430_REV_ES3_0))
sdrc_block_contents.power = (sdrc_read_reg(SDRC_POWER) &
~(SDRC_POWER_AUTOCOUNT_MASK|
SDRC_POWER_CLKCTRL_MASK)) |
(1 << SDRC_POWER_AUTOCOUNT_SHIFT) |
SDRC_SELF_REFRESH_ON_AUTOCOUNT;
else
sdrc_block_contents.power = sdrc_read_reg(SDRC_POWER);
sdrc_block_contents.cs_0 = 0x0;
sdrc_block_contents.mcfg_0 = sdrc_read_reg(SDRC_MCFG_0);
sdrc_block_contents.mr_0 = (sdrc_read_reg(SDRC_MR_0) & 0xFFFF);
sdrc_block_contents.emr_1_0 = 0x0;
sdrc_block_contents.emr_2_0 = 0x0;
sdrc_block_contents.emr_3_0 = 0x0;
sdrc_block_contents.actim_ctrla_0 =
sdrc_read_reg(SDRC_ACTIM_CTRL_A_0);
sdrc_block_contents.actim_ctrlb_0 =
sdrc_read_reg(SDRC_ACTIM_CTRL_B_0);
sdrc_block_contents.rfr_ctrl_0 =
sdrc_read_reg(SDRC_RFR_CTRL_0);
sdrc_block_contents.cs_1 = 0x0;
sdrc_block_contents.mcfg_1 = sdrc_read_reg(SDRC_MCFG_1);
sdrc_block_contents.mr_1 = sdrc_read_reg(SDRC_MR_1) & 0xFFFF;
sdrc_block_contents.emr_1_1 = 0x0;
sdrc_block_contents.emr_2_1 = 0x0;
sdrc_block_contents.emr_3_1 = 0x0;
sdrc_block_contents.actim_ctrla_1 =
sdrc_read_reg(SDRC_ACTIM_CTRL_A_1);
sdrc_block_contents.actim_ctrlb_1 =
sdrc_read_reg(SDRC_ACTIM_CTRL_B_1);
sdrc_block_contents.rfr_ctrl_1 =
sdrc_read_reg(SDRC_RFR_CTRL_1);
sdrc_block_contents.dcdl_1_ctrl = 0x0;
sdrc_block_contents.dcdl_2_ctrl = 0x0;
sdrc_block_contents.flags = 0x0;
sdrc_block_contents.block_size = 0x0;
arm_context_addr = virt_to_phys(omap3_arm_context);
/* Copy all the contents to the scratchpad location */
scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
memcpy_toio(scratchpad_address, &scratchpad_contents,
sizeof(scratchpad_contents));
/* Scratchpad contents being 32 bits, a divide by 4 done here */
memcpy_toio(scratchpad_address +
scratchpad_contents.prcm_block_offset,
&prcm_block_contents, sizeof(prcm_block_contents));
memcpy_toio(scratchpad_address +
scratchpad_contents.sdrc_block_offset,
&sdrc_block_contents, sizeof(sdrc_block_contents));
/*
* Copies the address of the location in SDRAM where ARM
* registers get saved during a MPU OFF transition.
*/
memcpy_toio(scratchpad_address +
scratchpad_contents.sdrc_block_offset +
sizeof(sdrc_block_contents), &arm_context_addr, 4);
}