/* TODO: Parse UART config from the command line */
static int __init exynos4210_uart_init(struct dt_device_node *dev,
const void *data)
{
const char *config = data;
struct exynos4210_uart *uart;
int res;
u64 addr, size;
if ( strcmp(config, "") )
printk("WARNING: UART configuration is not supported\n");
uart = &exynos4210_com;
/* uart->clock_hz = 0x16e3600; */
uart->baud = BAUD_AUTO;
uart->data_bits = 8;
uart->parity = PARITY_NONE;
uart->stop_bits = 1;
res = dt_device_get_address(dev, 0, &addr, &size);
if ( res )
{
printk("exynos4210: Unable to retrieve the base"
" address of the UART\n");
return res;
}
res = platform_get_irq(dev, 0);
if ( res < 0 )
{
printk("exynos4210: Unable to retrieve the IRQ\n");
return -EINVAL;
}
uart->irq = res;
uart->regs = ioremap_nocache(addr, size);
if ( !uart->regs )
{
printk("exynos4210: Unable to map the UART memory\n");
return -ENOMEM;
}
uart->vuart.base_addr = addr;
uart->vuart.size = size;
uart->vuart.data_off = UTXH;
uart->vuart.status_off = UTRSTAT;
uart->vuart.status = UTRSTAT_TXE | UTRSTAT_TXFE;
/* Register with generic serial driver. */
serial_register_uart(SERHND_DTUART, &exynos4210_uart_driver, uart);
dt_device_set_used_by(dev, DOMID_XEN);
return 0;
}
void zynq_uart_init(void)
{
uint32_t uart_cr;
// TODO use dts
zynq_uart_params.io_base = ZYNQ_UART0_BASE_PHY_ADDR;
uart_cr = zynq_uart_params.io_base + XUARTPS_CR_OFFSET;
// disable TX and RX
mmio_writel(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS, uart_cr);
// reset TX and RX
mmio_writel(XUARTPS_CR_TXRST | XUARTPS_CR_RXRST, uart_cr);
// enabled TX and RX
mmio_writel(XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN, uart_cr);
// keep default boudrate, since FPGA
#ifdef TEST
// why AT? please refer history of AT cmd
mmio_writel('A', zynq_uart_params.io_base + XUARTPS_FIFO_OFFSET);
mmio_writel('T', zynq_uart_params.io_base + XUARTPS_FIFO_OFFSET);
#endif
#ifdef TEST
{
struct serial_port port;
int i;
port.uart = &zynq_uart_params;
for( i = 0 ; i < 10 ; ++i ) {
char c;
while ( zynq_uart_getc( &port , &c) == 0 ) ;
zynq_uart_putc( &port, c );
zynq_uart_putc( &port, '-' );
zynq_uart_putc( &port, c + 1 );
zynq_uart_putc( &port, '\r' );
zynq_uart_putc( &port, '\n' );
}
zynq_uart_putc( &port, '\r' );
zynq_uart_putc( &port, '\n' );
}
#endif
serial_register_uart(0, &zynq_uart_driver, &zynq_uart_params);
}
static int __init omap_uart_init(struct dt_device_node *dev,
const void *data)
{
const char *config = data;
struct omap_uart *uart;
u32 clkspec;
int res;
u64 addr, size;
if ( strcmp(config, "") )
printk("WARNING: UART configuration is not supported\n");
uart = &omap_com;
res = dt_property_read_u32(dev, "clock-frequency", &clkspec);
if ( !res )
{
printk("omap-uart: Unable to retrieve the clock frequency\n");
return -EINVAL;
}
uart->clock_hz = clkspec;
uart->baud = 115200;
uart->data_bits = 8;
uart->parity = UART_PARITY_NONE;
uart->stop_bits = 1;
res = dt_device_get_address(dev, 0, &addr, &size);
if ( res )
{
printk("omap-uart: Unable to retrieve the base"
" address of the UART\n");
return res;
}
res = platform_get_irq(dev, 0);
if ( res < 0 )
{
printk("omap-uart: Unable to retrieve the IRQ\n");
return -EINVAL;
}
uart->irq = res;
uart->regs = ioremap_nocache(addr, size);
if ( !uart->regs )
{
printk("omap-uart: Unable to map the UART memory\n");
return -ENOMEM;
}
uart->vuart.base_addr = addr;
uart->vuart.size = size;
uart->vuart.data_off = UART_THR;
uart->vuart.status_off = UART_LSR << REG_SHIFT;
uart->vuart.status = UART_LSR_THRE;
/* Register with generic serial driver */
serial_register_uart(SERHND_DTUART, &omap_uart_driver, uart);
dt_device_set_used_by(dev, DOMID_XEN);
return 0;
}
