OutputChannelForm::OutputChannelForm(const int index, QWidget *parent) :
    ChannelForm(index, parent), ui(), m_inChannelTest(false)
{
    ui.setupUi(this);

    // The convention for OP is Channel 1 to Channel 10.
    ui.actuatorNumber->setText(QString("%1").arg(index + 1));
    setBank("-");
    // Register for ActuatorSettings changes:
    connect(ui.actuatorMin, SIGNAL(editingFinished()), this, SLOT(setChannelRange()));
    connect(ui.actuatorMax, SIGNAL(editingFinished()), this, SLOT(setChannelRange()));
    connect(ui.actuatorRev, SIGNAL(toggled(bool)), this, SLOT(reverseChannel(bool)));
    // Now connect the channel out sliders to our signal to send updates in test mode
    connect(ui.actuatorNeutral, SIGNAL(valueChanged(int)), this, SLOT(sendChannelTest(int)));

    ui.actuatorLink->setChecked(false);
    connect(ui.actuatorLink, SIGNAL(toggled(bool)), this, SLOT(linkToggled(bool)));

    // Set limits
    ui.actuatorMin->setMaximum(MAXOUTPUT_VALUE);
    ui.actuatorMax->setMaximum(MAXOUTPUT_VALUE);
    ui.actuatorValue->setMaximum(MAXOUTPUT_VALUE);
    ui.actuatorMin->setMinimum(MINOUTPUT_VALUE);
    ui.actuatorMax->setMinimum(MINOUTPUT_VALUE);
    ui.actuatorValue->setMinimum(MINOUTPUT_VALUE);

    setChannelRange();

    disableMouseWheelEvents();
}
Example #2
0
void Enc28j60::reset(void)
{
    // Trigger a software reset
    writeOperation(ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET);

    // Errata #2: Wait for at least 1 ms after software reset
    for (uint32_t i = 0x1FFF; i != 0; i--)
        ;

    // Wait until the clock becomes ready
    while(!readOperation(ENC28J60_READ_CTRL_REG, ESTAT) & ESTAT_CLKRDY);

    // Store a pointer to the next packet
    nextPacketPtr = RXSTART_INIT;

    // Set the packet transmit and receive buffers
    writeRegister(ERXST, RXSTART_INIT);
    writeRegister(ERXRDPT, RXSTART_INIT);
    writeRegister(ERXND, RXSTOP_INIT);
    writeRegister(ETXST, TXSTART_INIT);
    writeRegister(ETXND, TXSTOP_INIT);

    // Set MACON1 register
    writeRegisterByte(MACON1, MACON1_MARXEN | MACON1_TXPAUS | MACON1_RXPAUS);

    // Set MACON2 register
    writeRegisterByte(MACON2, 0x00);

    // Set MACON3 registers
    writeOperation(ENC28J60_BIT_FIELD_SET, MACON3, MACON3_PADCFG0 | MACON3_TXCRCEN | MACON3_FRMLNEN);

    // Set Non-Back-to-Back Inter-Packet Gap
    writeRegister(MAIPG, 0x0C12);

    // Set Back-to-Back Inter-Packet Gap
    writeRegisterByte(MABBIPG, 0x12);

    // Set maximum frame length
    writeRegister(MAMXFL, MAX_FRAMELEN);

    // Set MAC address
    writeRegisterByte(MAADR5, macAddress[0]);
    writeRegisterByte(MAADR4, macAddress[1]);
    writeRegisterByte(MAADR3, macAddress[2]);
    writeRegisterByte(MAADR2, macAddress[3]);
    writeRegisterByte(MAADR1, macAddress[4]);
    writeRegisterByte(MAADR0, macAddress[5]);

    // Errata #9/10: Disable loopback in half-duplex
    writePhy(PHCON2, PHCON2_HDLDIS);

    // Set ECON1 bank
    setBank(ECON1);

    // Enable packet interrupt
    writeOperation(ENC28J60_BIT_FIELD_SET, EIE, EIE_INTIE | EIE_PKTIE);

    // Enable packet reception
    writeOperation(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXEN);
}
Example #3
0
/**
 * initWizard
 * Prepares the wizard for use
 **/
void 
initWizard()
{
    int i;
    preprocessor = newPreprocessor( fs, 3 );
    loadPatterns();
    for ( i = 0; i < 3; i++ )
	printf("Found %d patterns in %s bank\n", 
	       npatterns[i], 
	       (i == 0 ? "NATURAL" : (i == 1 ? "NUMERAL" : "EXTENDED")));
    setBank( NATURAL );
}
void Enc28J60Network::init(uint8_t* macaddr)
{
  // initialize I/O
  // ss as output:
  pinMode(ENC28J60_CONTROL_CS, OUTPUT);
  CSPASSIVE; // ss=0
  //
  pinMode(SPI_MOSI, OUTPUT);

  pinMode(SPI_SCK, OUTPUT);

  pinMode(SPI_MISO, INPUT);


  digitalWrite(SPI_MOSI, LOW);

  digitalWrite(SPI_SCK, LOW);

  /*DDRB  |= 1<<PB3 | 1<<PB5; // mosi, sck output
  cbi(DDRB,PINB4); // MISO is input
  //
  cbi(PORTB,PB3); // MOSI low
  cbi(PORTB,PB5); // SCK low
  */
  //
  // initialize SPI interface
  // master mode and Fosc/2 clock:
  SPCR = (1<<SPE)|(1<<MSTR);
  SPSR |= (1<<SPI2X);
  // perform system reset
  writeOp(ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET);
  delay(50);
  // check CLKRDY bit to see if reset is complete
  // The CLKRDY does not work. See Rev. B4 Silicon Errata point. Just wait.
  //while(!(readReg(ESTAT) & ESTAT_CLKRDY));
  // do bank 0 stuff
  // initialize receive buffer
  // 16-bit transfers, must write low byte first
  // set receive buffer start address
  nextPacketPtr = RXSTART_INIT;
  // Rx start
  writeRegPair(ERXSTL, RXSTART_INIT);
  // set receive pointer address
  writeRegPair(ERXRDPTL, RXSTART_INIT);
  // RX end
  writeRegPair(ERXNDL, RXSTOP_INIT);
  // TX start
  //writeRegPair(ETXSTL, TXSTART_INIT);
  // TX end
  //writeRegPair(ETXNDL, TXSTOP_INIT);
  // do bank 1 stuff, packet filter:
  // For broadcast packets we allow only ARP packtets
  // All other packets should be unicast only for our mac (MAADR)
  //
  // The pattern to match on is therefore
  // Type     ETH.DST
  // ARP      BROADCAST
  // 06 08 -- ff ff ff ff ff ff -> ip checksum for theses bytes=f7f9
  // in binary these poitions are:11 0000 0011 1111
  // This is hex 303F->EPMM0=0x3f,EPMM1=0x30
  //TODO define specific pattern to receive dhcp-broadcast packages instead of setting ERFCON_BCEN!
  writeReg(ERXFCON, ERXFCON_UCEN|ERXFCON_CRCEN|ERXFCON_PMEN|ERXFCON_BCEN);
  writeRegPair(EPMM0, 0x303f);
  writeRegPair(EPMCSL, 0xf7f9);
  //
  //
  // do bank 2 stuff
  // enable MAC receive
  // and bring MAC out of reset (writes 0x00 to MACON2)
  writeRegPair(MACON1, MACON1_MARXEN|MACON1_TXPAUS|MACON1_RXPAUS);
  // enable automatic padding to 60bytes and CRC operations
  writeOp(ENC28J60_BIT_FIELD_SET, MACON3, MACON3_PADCFG0|MACON3_TXCRCEN|MACON3_FRMLNEN);
  // set inter-frame gap (non-back-to-back)
  writeRegPair(MAIPGL, 0x0C12);
  // set inter-frame gap (back-to-back)
  writeReg(MABBIPG, 0x12);
  // Set the maximum packet size which the controller will accept
  // Do not send packets longer than MAX_FRAMELEN:
  writeRegPair(MAMXFLL, MAX_FRAMELEN);
  // do bank 3 stuff
  // write MAC address
  // NOTE: MAC address in ENC28J60 is byte-backward
  writeReg(MAADR5, macaddr[0]);
  writeReg(MAADR4, macaddr[1]);
  writeReg(MAADR3, macaddr[2]);
  writeReg(MAADR2, macaddr[3]);
  writeReg(MAADR1, macaddr[4]);
  writeReg(MAADR0, macaddr[5]);
  // no loopback of transmitted frames
  phyWrite(PHCON2, PHCON2_HDLDIS);
  // switch to bank 0
  setBank(ECON1);
  // enable interrutps
  writeOp(ENC28J60_BIT_FIELD_SET, EIE, EIE_INTIE|EIE_PKTIE);
  // enable packet reception
  writeOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXEN);
  //Configure leds
  phyWrite(PHLCON,0x476);
}
void Enc28J60Network::init(uint8_t* macaddr)
{
  MemoryPool::init(); // 1 byte in between RX_STOP_INIT and pool to allow prepending of controlbyte
  // initialize I/O
  // ss as output:
  pinMode(ENC28J60_CONTROL_CS, OUTPUT);
  CSPASSIVE; // ss=0
  //

#ifdef ENC28J60DEBUG
  Serial.println("ENC28J60::initialize / before initSPI()");
#endif
  SPI.begin();
  SPI.setBitOrder(MSBFIRST);
//  SPI.setDataMode(SPI_MODE0);
//  SPI.setClockDivider(SPI_CLOCK_DIV16);
#ifdef ENC28J60DEBUG
  Serial.println("ENC28J60::initialize / after initSPI()");
  Serial.print("ENC28J60::initialize / csPin = ");
  Serial.println(SPI.nssPin());
  Serial.print("ENC28J60::initialize / miso = ");
  Serial.println(SPI.misoPin());
  Serial.print("ENC28J60::initialize / mosi = ");
  Serial.println(SPI.mosiPin());
  Serial.print("ENC28J60::initialize / sck = ");
  Serial.println(SPI.sckPin());
#endif
  selectPin = ENC28J60_CONTROL_CS;
  pinMode(selectPin, OUTPUT);
  digitalWrite(selectPin, HIGH);
	
  // perform system reset
  writeOp(ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET);
  delay(2); // errata B7/2
  delay(50);
  // check CLKRDY bit to see if reset is complete
  // The CLKRDY does not work. See Rev. B4 Silicon Errata point. Just wait.
  //while(!(readReg(ESTAT) & ESTAT_CLKRDY));
  // do bank 0 stuff
  // initialize receive buffer
  // 16-bit transfers, must write low byte first
  // set receive buffer start address
#ifdef ENC28J60DEBUG
  Serial.println("ENC28J60::initialize / before readOp(ENC28J60_READ_CTRL_REG, ESTAT)");
#endif
  while (!readOp(ENC28J60_READ_CTRL_REG, ESTAT) & ESTAT_CLKRDY)
      ;
#ifdef ENC28J60DEBUG
  Serial.println("ENC28J60::initialize / after readOp(ENC28J60_READ_CTRL_REG, ESTAT)");
#endif
  nextPacketPtr = RXSTART_INIT;
  // Rx start
  writeRegPair(ERXSTL, RXSTART_INIT);
  // set receive pointer address
  writeRegPair(ERXRDPTL, RXSTART_INIT);
  // RX end
  writeRegPair(ERXNDL, RXSTOP_INIT);
  // TX start
  //-------------writeRegPair(ETXSTL, TXSTART_INIT);
  // TX end
  //-------------writeRegPair(ETXNDL, TXSTOP_INIT);
  // do bank 1 stuff, packet filter:
  // For broadcast packets we allow only ARP packtets
  // All other packets should be unicast only for our mac (MAADR)
  //
  // The pattern to match on is therefore
  // Type     ETH.DST
  // ARP      BROADCAST
  // 06 08 -- ff ff ff ff ff ff -> ip checksum for theses bytes=f7f9
  // in binary these poitions are:11 0000 0011 1111
  // This is hex 303F->EPMM0=0x3f,EPMM1=0x30
  //TODO define specific pattern to receive dhcp-broadcast packages instead of setting ERFCON_BCEN!
//    enableBroadcast(); // change to add ERXFCON_BCEN recommended by epam
  writeReg(ERXFCON, ERXFCON_UCEN|ERXFCON_CRCEN|ERXFCON_PMEN|ERXFCON_BCEN);
  writeRegPair(EPMM0, 0x303f);
  writeRegPair(EPMCSL, 0xf7f9);
  //
  //
  // do bank 2 stuff
  // enable MAC receive
  // and bring MAC out of reset (writes 0x00 to MACON2)
  writeRegPair(MACON1, MACON1_MARXEN|MACON1_TXPAUS|MACON1_RXPAUS);
  //----------------writeRegPair(MACON2, 0x00);
  // enable automatic padding to 60bytes and CRC operations
  writeOp(ENC28J60_BIT_FIELD_SET, MACON3, MACON3_PADCFG0|MACON3_TXCRCEN|MACON3_FRMLNEN);
  // set inter-frame gap (non-back-to-back)
  writeRegPair(MAIPGL, 0x0C12);
  // set inter-frame gap (back-to-back)
  writeReg(MABBIPG, 0x12);
  // Set the maximum packet size which the controller will accept
  // Do not send packets longer than MAX_FRAMELEN:
  writeRegPair(MAMXFLL, MAX_FRAMELEN);
  // do bank 3 stuff
  // write MAC address
  // NOTE: MAC address in ENC28J60 is byte-backward
  writeReg(MAADR5, macaddr[0]);
  writeReg(MAADR4, macaddr[1]);
  writeReg(MAADR3, macaddr[2]);
  writeReg(MAADR2, macaddr[3]);
  writeReg(MAADR1, macaddr[4]);
  writeReg(MAADR0, macaddr[5]);
  // no loopback of transmitted frames
  phyWrite(PHCON2, PHCON2_HDLDIS);
  // switch to bank 0
  setBank(ECON1);
  // enable interrutps
  writeOp(ENC28J60_BIT_FIELD_SET, EIE, EIE_INTIE|EIE_PKTIE);
  // enable packet reception
  writeOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXEN);
  //Configure leds
  phyWrite(PHLCON,0x476);

  byte rev = readReg(EREVID);
  // microchip forgot to step the number on the silcon when they
  // released the revision B7. 6 is now rev B7. We still have
  // to see what they do when they release B8. At the moment
  // there is no B8 out yet
  if (rev > 5) ++rev;
#ifdef ENC28J60DEBUG
  Serial.print("ENC28J60::initialize returns ");
  Serial.println(rev);
#endif
//  return rev;
}
void Enc28J60Network::writeRegByte (uint8_t address, uint8_t data) {
    setBank(address);
    writeOp(ENC28J60_WRITE_CTRL_REG, address, data);
}
byte Enc28J60Network::readRegByte (uint8_t address) {
    setBank(address);
    return readOp(ENC28J60_READ_CTRL_REG, address);
}
Example #8
0
int THaCrateMap::init(TString the_map)
{
  // initialize the crate-map according to the lines in the string 'the_map'
  // parse each line separately, to ensure that the format is correct

  // be certain the_map ends with a '\0' so we can make a stringstream from it
  the_map += '\0';
  ISSTREAM s(the_map.Data());

  int linecnt = 0;
  string line;
  int crate; // current CRATE
  int slot;

  typedef string::size_type ssiz_t;

  for(crate=0; crate<MAXROC; crate++) {
    crdat[crate].nslot = 0;
    crdat[crate].crate_used = false;
    crdat[crate].bank_structure = false;
    setCrateType(crate,"unknown"); //   crate_type[crate] = "unknown";
    crdat[crate].minslot=MAXSLOT;
    crdat[crate].maxslot=0;
    for(slot=0; slot<MAXSLOT; slot++) {
      crdat[crate].slot_used[slot] = false;
      crdat[crate].model[slot] = 0;
      crdat[crate].header[slot] = 0;
      crdat[crate].slot_clear[slot] = true;
      crdat[crate].bank[slot] = -1;
    }
  }

  crate=-1; // current CRATE

  while ( getline(s,line).good() ) {
    linecnt++;
    ssiz_t l = line.find_first_of("!#");    // drop comments
    if (l != string::npos ) line.erase(l);

    if ( line.length() <= 0 ) continue;

    if ( line.find_first_not_of(" \t") == string::npos ) continue; // nothing useful

    char ctype[21];

// Make the line "==== Crate" not care about how many "=" chars or other
// chars before "Crate", but lines beginning in # are still a comment
    ssiz_t st = line.find("Crate", 0, 5);
    if (st != string::npos) {
      string lcopy = line;
      line.replace(0, lcopy.length(), lcopy, st, st+lcopy.length());
    }

// set the next CRATE number and type

    if ( sscanf(line.c_str(),"Crate %d type %20s",&crate,ctype) == 2 ) {
      if ( setCrateType(crate,ctype) != CM_OK )  {
        cout << "THaCrateMap:: fatal ERROR 2  setCrateType "<<endl;
	return CM_ERR;
      }
      // for a scaler crate, get the 'name' or location as well
      if ( crdat[crate].crate_code == kScaler ) {
	if (sscanf(line.c_str(),"Crate %*d type %*s %20s",ctype) != 1) {
          cout << "THaCrateMap:: fatal ERROR 3   "<<endl;
	  return CM_ERR;
	}
	TString scaler_name(ctype);
	scaler_name.ReplaceAll("\"",""); // drop extra quotes
	setScalerLoc(crate,scaler_name);
      }
      continue; // onto the next line
    }

    // The line is of the format:
    //        slot#  model#  [clear header  mask  nchan ndata ]
    // where clear, header, mask, nchan and ndata are optional interpretted in
    // that order.
    // Another option is "bank decoding" :  all data in this CODA bank
    // belongs to this slot and model.  The line has the format
    //        slot#  model#  bank#

    // Default values:
    int imodel, cword=1;
    unsigned int mask=0, iheader=0, ichan=MAXCHAN, idata=MAXDATA;
    int nread;
    // must read at least the slot and model numbers
    if ( crate>=0 &&
	 (nread=
	  sscanf(line.c_str(),"%d %d %d %x %x %u %u",
		 &slot,&imodel,&cword,&iheader,&mask,&ichan,&idata)) >=2 ) {
      if (nread>=6)
	setModel(crate,slot,imodel,ichan,idata);
      else
	setModel(crate,slot,imodel);

      if (nread==3) 
        setBank(crate, slot, cword);
      if (nread>3)
	setClear(crate,slot,cword);
      if (nread>=4)
	setHeader(crate,slot,iheader);
      if (nread>=5)
	setMask(crate,slot,mask);
      continue;
    }

    // unexpected input
    cout << "THaCrateMap:: fatal ERROR 4   "<<endl<<"Bad line "<<endl<<line<<endl;
    cout << "    Warning: a bad line could cause wrong decoding !"<<endl;

    return CM_ERR;
  }

  for(crate=0; crate<MAXROC; crate++) {
    Int_t imin=MAXSLOT;
    Int_t imax=0;
    for(slot=0; slot<MAXSLOT; slot++) {
      if (crdat[crate].bank[slot]>=0) crdat[crate].bank_structure=true;
      if (crdat[crate].slot_used[slot]) {
	if (slot < imin) imin=slot;
        if (slot > imax) imax=slot;
      }
    }
    crdat[crate].minslot=imin;
    crdat[crate].maxslot=imax;
  }

  return CM_OK;
}