static void set_tcon_pinmux(void) { /* TCON control pins pinmux */ /* GPIOA_5 -> LCD_Clk, GPIOA_0 -> TCON_STH1, GPIOA_1 -> TCON_STV1, GPIOA_2 -> TCON_OEH, */ set_mio_mux(0, ((1<<11)|(1<<14)|(1<<15)|(1<<16))); set_mio_mux(4, (1<<0)|(1<<2)|(1<<4) ); //For 6bits //PP1 -> UPDN:0, PP2 -> SHLR:1 #ifdef CONFIG_SN7325 configIO(1, 0); setIO_level(1, 0, 1); setIO_level(1, 1, 2); #endif }
static void power_off_lcd(void) { msleep(50); //AVDD EIO -> OD4: 0 #ifdef CONFIG_SN7325 configIO(0, 0); setIO_level(0, 0, 4); #endif msleep(20); //LCD3.3V EIO -> OD0: 1 #ifdef CONFIG_SN7325 configIO(0, 0); setIO_level(0, 1, 0); #endif }
static void power_on_lcd(void) { //int setIO_level(unsigned char port, unsigned char iobits, unsigned char offset); //LCD3.3V EIO -> OD0: 0 #ifdef CONFIG_SN7325 configIO(0, 0); setIO_level(0, 0, 0); #endif msleep(20); //AVDD EIO -> OD4: 1 #ifdef CONFIG_SN7325 configIO(0, 0); setIO_level(0, 1, 4); #endif msleep(50); }
static void power_off_lcd(void) { //EIO -> OD0: 1 #ifdef CONFIG_SN7325 configIO(0, 0); setIO_level(0, 1, 0); #endif }
static void power_off_lcd(void) { msleep(50); //AVDD EIO -> OD4: 0 #ifdef CONFIG_SN7325 configIO(0, 0); setIO_level(0, 0, 4); #else set_gpio_val(GPIOA_bank_bit(3), GPIOA_bit_bit0_14(3), 0); set_gpio_mode(GPIOA_bank_bit(3), GPIOA_bit_bit0_14(3), GPIO_OUTPUT_MODE); #endif msleep(20); //LCD3.3V EIO -> OD0: 1 #ifdef CONFIG_SN7325 configIO(0, 0); setIO_level(0, 1, 0); #else set_gpio_val(GPIOD_bank_bit2_24(20), GPIOD_bit_bit2_24(20), 1); set_gpio_mode(GPIOD_bank_bit2_24(20), GPIOD_bit_bit2_24(20), GPIO_OUTPUT_MODE); #endif }
static void power_on_lcd(void) { //EIO -> OD0: 0 #ifdef CONFIG_SN7325 configIO(0, 0); setIO_level(0, 0, 0); #endif msleep(10); //VCCx2_EN D17 GPIOA_6 --> H set_gpio_val(GPIOA_bank_bit(6), GPIOA_bit_bit0_14(6), 1); set_gpio_mode(GPIOA_bank_bit(6), GPIOA_bit_bit0_14(6), GPIO_OUTPUT_MODE); }
void power_off_backlight(void) { //EIO -> PP1: 0 //EIO -> OD4: 1 #ifdef CONFIG_SN7325 configIO(1, 0); //configIO(0, 0); setIO_level(1, 1, 1); //setIO_level(0, 1, 4); #endif CLEAR_CBUS_REG_MASK(PERIPHS_PIN_MUX_2, (1<<31)); CLEAR_CBUS_REG_MASK(PWM_MISC_REG_AB, (1 << 0)); set_gpio_val(GPIOA_bank_bit(7), GPIOA_bit_bit0_14(7), 0); set_gpio_mode(GPIOA_bank_bit(7), GPIOA_bit_bit0_14(7), GPIO_OUTPUT_MODE); }
static void power_on_lcd(void) { //int setIO_level(unsigned char port, unsigned char iobits, unsigned char offset); //LCD3.3V EIO -> OD0: 0 #ifdef CONFIG_SN7325 configIO(0, 0); setIO_level(0, 0, 0); #else set_gpio_val(GPIOD_bank_bit2_24(20), GPIOD_bit_bit2_24(20), 0); set_gpio_mode(GPIOD_bank_bit2_24(20), GPIOD_bit_bit2_24(20), GPIO_OUTPUT_MODE); #endif msleep(20); //AVDD EIO -> OD4: 1 #ifdef CONFIG_SN7325 configIO(0, 0); setIO_level(0, 1, 4); #else set_gpio_val(GPIOA_bank_bit(3), GPIOA_bit_bit0_14(3), 1); set_gpio_mode(GPIOA_bank_bit(3), GPIOA_bit_bit0_14(3), GPIO_OUTPUT_MODE); #endif msleep(50); }
static void power_off_lcd(void) { msleep(50); //AVDD & BL VCC EIO -> OD4: 0 #ifdef CONFIG_SN7325 configIO(0, 0); setIO_level(0, 0, 4); #endif // msleep(20); // //AVDD EIO -> PP5: 0 //#ifdef CONFIG_SN7325 // configIO(1, 0); // setIO_level(1, 0, 5); //#endif msleep(50); //LCD3.3V EIO -> OD0: 1 #ifdef CONFIG_SN7325 configIO(0, 0); setIO_level(0, 1, 0); #endif }
void power_on_backlight(void) { msleep(100); SET_CBUS_REG_MASK(PWM_MISC_REG_AB, (1 << 0)); msleep(100); SET_CBUS_REG_MASK(PERIPHS_PIN_MUX_2, (1<<31)); msleep(100); //EIO -> PP1: 0 //EIO -> OD4: 0 #ifdef CONFIG_SN7325 configIO(1, 0); //configIO(0, 0); setIO_level(1, 0, 1); //setIO_level(0, 0, 4); #endif printk("\n\npower_on_backlight.\n\n"); }
static void aml_8726m_power_on_bl(void) { debug("%s\n", __FUNCTION__); mdelay(100); SET_CBUS_REG_MASK(PWM_MISC_REG_AB, (1 << 0)); mdelay(100); SET_CBUS_REG_MASK(PERIPHS_PIN_MUX_2, (1<<31)); mdelay(100); //EIO -> OD4: 1 #ifdef CONFIG_SN7325 configIO(0, 0); setIO_level(0, 1, 4); #endif }
static void power_on_lcd(void) { //int setIO_level(unsigned char port, unsigned char iobits, unsigned char offset); //LCD3.3V EIO -> OD0: 0 #ifdef CONFIG_SN7325 configIO(0, 0); setIO_level(0, 0, 0); #endif msleep(80); // //AVDD EIO -> PP5: 1 //#ifdef CONFIG_SN7325 // configIO(1, 0); // setIO_level(1, 1, 5); //#endif // msleep(50); //AVDD & BL VCC EIO -> OD4: 1 #ifdef CONFIG_SN7325 configIO(0, 0); setIO_level(0, 1, 4); #endif msleep(80); }