void nouveau_hw_setpll(struct drm_device *dev, uint32_t reg1, struct nouveau_pll_vals *pv) { struct drm_nouveau_private *dev_priv = dev->dev_private; int cv = dev_priv->vbios.chip_version; if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 || cv >= 0x40) { if (reg1 > 0x405c) setPLL_double_highregs(dev, reg1, pv); else setPLL_double_lowregs(dev, reg1, pv); } else setPLL_single(dev, reg1, pv); }
int nv04_clock_pll_prog(struct nouveau_clock *clk, u32 reg1, struct nouveau_pll_vals *pv) { struct nv04_clock_priv *priv = (void *)clk; int cv = nouveau_bios(clk)->version.chip; if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 || cv >= 0x40) { if (reg1 > 0x405c) setPLL_double_highregs(priv, reg1, pv); else setPLL_double_lowregs(priv, reg1, pv); } else setPLL_single(priv, reg1, pv); return 0; }
int nv04_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq) { struct nouveau_bios *bios = nouveau_bios(devinit); struct nouveau_pll_vals pv; struct nvbios_pll info; int cv = bios->version.chip; int N1, M1, N2, M2, P; int ret; ret = nvbios_pll_parse(bios, type > 0x405c ? type : type - 4, &info); if (ret) return ret; ret = nv04_pll_calc(nv_subdev(devinit), &info, freq, &N1, &M1, &N2, &M2, &P); if (!ret) return -EINVAL; pv.refclk = info.refclk; pv.N1 = N1; pv.M1 = M1; pv.N2 = N2; pv.M2 = M2; pv.log2P = P; if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 || cv >= 0x40) { if (type > 0x405c) setPLL_double_highregs(devinit, type, &pv); else setPLL_double_lowregs(devinit, type, &pv); } else setPLL_single(devinit, type, &pv); return 0; }