void __init init_IRQ(void)
{
struct device_node *np;
/* Mask all priority IRQs */
and_creg(IER, ~0xfff0);
np = of_find_compatible_node(NULL, NULL, "ti,c64x+core-pic");
if (np != NULL) {
/* create the core host */
core_domain = irq_domain_add_linear(np, NR_PRIORITY_IRQS,
&core_domain_ops, NULL);
if (core_domain)
irq_set_default_host(core_domain);
of_node_put(np);
}
printk(KERN_INFO "Core interrupt controller initialized\n");
/* now we're ready for other SoC controllers */
megamod_pic_init();
/* Clear all general IRQ flags */
set_creg(ICR, 0xfff0);
}
void time_init(void)
{
u64 tmp = (u64)NSEC_PER_SEC << SCHED_CLOCK_SHIFT;
do_div(tmp, c6x_core_freq);
sched_clock_multiplier = tmp;
clocksource_register_hz(&clocksource_tsc, c6x_core_freq);
/* write anything into TSCL to enable counting */
set_creg(TSCL, 0);
/* probe for timer64 event timer */
timer64_init();
}
