static inline void raise()
{
udelay(1); /* >= 60ns after RS or RW transition */
set_cs();
udelay(1); /* >= 450ns enable hold time */
clr_cs();
udelay(1); /* >= 20ns before RS or RW transition */
}
void eth_v_reset( void ){
clear_cs();
spi_u8_send( ETH_SPI_OP_SRC );
set_cs();
}
uint8_t eth_u8_read_buffer( void ){
clear_cs();
spi_u8_send( ETH_SPI_OP_RBM );
uint8_t data = spi_u8_send( 0 );
set_cs();
return data;
}
// set bank based on register address
void eth_v_set_bank( uint8_t addr ){
// clear the bank sel bits
clear_cs();
spi_u8_send( ETH_SPI_OP_BFC | ( ECON1 & ADDR_MSK ) );
spi_u8_send( ECON1_BSEL1 | ECON1_BSEL0 );
set_cs();
// set the bank sel bits
clear_cs();
spi_u8_send( ETH_SPI_OP_BFS | ( ECON1 & ADDR_MSK ) );
spi_u8_send( ( addr & BANK_MSK ) >> 5 );
set_cs();
}
int init_sdmmc_device()
{
int result;
// Set clock to 200k_hz (50Mhz system clock)
set_clock_divisor(125);
// After power on, send a bunch of clocks to initialize the chip
set_cs(1);
for (int i = 0; i < 10; i++)
spi_transfer(0xff);
set_cs(0);
// Reset the card
result = send_sd_command(SD_CMD_RESET, 0);
if (result != 1)
return -1;
// Poll until it is ready
while (1)
{
result = send_sd_command(SD_CMD_INIT, 0);
if (result == 0)
break;
if (result != 1)
return -1;
}
// Configure the block size
result = send_sd_command(SD_CMD_SET_BLOCK_LEN, BLOCK_SIZE);
if (result != 0)
return -1;
// Increase clock rate to 5 Mhz
set_clock_divisor(5);
return 0;
}
void eth_v_clear_bits( uint8_t addr, uint8_t bits ){
// set bank
eth_v_set_bank( addr );
// write to the control reg
clear_cs();
spi_u8_send( ETH_SPI_OP_BFC | ( addr & ADDR_MSK ) );
spi_u8_send( bits );
set_cs();
}
// write to a control reg.
// this will automatically set the correct bank
void eth_v_write_reg( uint8_t addr, uint8_t data ){
// set bank
eth_v_set_bank( addr );
// write to the control reg
clear_cs();
spi_u8_send( ETH_SPI_OP_WCR | ( addr & ADDR_MSK ) );
spi_u8_send( data );
set_cs();
}
void eth_v_write_buffer( uint8_t *data, uint16_t length ){
clear_cs();
spi_u8_send( ETH_SPI_OP_WBM );
while( length > 0 ){
spi_u8_send( *data );
data++;
length--;
}
set_cs();
}
void eth_v_read_buffer( uint8_t *data, uint16_t length ){
clear_cs();
spi_u8_send( ETH_SPI_OP_RBM );
while( length > 0 ){
*data = spi_u8_send( 0 );
data++;
length--;
}
set_cs();
}
uint8_t eth_u8_read_reg( uint8_t addr ){
// set bank
eth_v_set_bank( addr );
clear_cs();
spi_u8_send( ETH_SPI_OP_RCR | ( addr & ADDR_MSK ) );
// check if this is a MAC or PHY register
// if so, we need a dummy byte
if( ( addr & MAC_PHY ) != 0 ){
spi_u8_send( 0 );
}
uint8_t data = spi_u8_send( 0 );
set_cs();
return data;
}
// call this init function before using any devices on the SPI bus
void eth_v_io_init( void ){
rev_4_4 = FALSE;
// check board rev:
// set GPIO1 to pull up
io_v_set_mode( IO_PIN_GPIO1, IO_MODE_INPUT_PULLUP );
if( io_b_digital_read( IO_PIN_GPIO1 ) == FALSE ){
rev_4_4 = TRUE;
}
if( rev_4_4 ){
// set up io pins:
ETH_4_4_CS_DDR |= _BV( ETH_4_4_CS_PIN );
ETH_4_4_RST_DDR |= _BV( ETH_4_4_RST_PIN );
ETH_4_4_IRQ_DDR &= ~_BV( ETH_4_4_IRQ_PIN );
ETH_4_4_RST_PORT &= ~_BV( ETH_4_4_RST_PIN );
ETH_4_4_RST_PORT |= _BV( ETH_4_4_RST_PIN );
}
else{
// set up io pins:
ETH_CS_DDR |= _BV( ETH_CS_PIN );
ETH_RST_DDR |= _BV( ETH_RST_PIN );
ETH_IRQ_DDR &= ~_BV( ETH_IRQ_PIN );
ETH_RST_PORT &= ~_BV( ETH_RST_PIN );
ETH_RST_PORT |= _BV( ETH_RST_PIN );
}
set_cs();
}
