void set_vmode_clk(vmode_t mode)
{
int i = 0;
int j = 0;
hw_enc_clk_val_t *p_enc =NULL;
printk("set_vmode_clk mode is %d\n", mode);
p_enc=&setting_enc_clk_val[0];
i = ARRAY_SIZE(setting_enc_clk_val);
for (j = 0; j < i; j++){
if(mode == p_enc[j].mode)
break;
}
if(j == i) {
printk("set_vmode_clk: not valid mode %d\n", mode);
return;
}
set_viu_path(p_enc[j].viu_path, p_enc[j].viu_type);
set_hdmitx_sys_clk();
set_hpll_clk_out(p_enc[j].hpll_clk_out);
set_hpll_od1(p_enc[j].od1);
set_hpll_od2(p_enc[j].od2);
set_hpll_od3(p_enc[j].od3);
set_vid_pll_div(p_enc[j].vid_pll_div);
set_vid_clk_div(p_enc[j].vid_clk_div);
set_hdmi_tx_pixel_div(p_enc[j].hdmi_tx_pixel_div);
set_encp_div(p_enc[j].encp_div);
set_enci_div(p_enc[j].enci_div);
set_encl_div(p_enc[j].encl_div);
set_vdac0_div(p_enc[j].vdac0_div);
}
void set_vmode_clk(vmode_t mode)
{
enc_clk_val_t *p_enc = &setting_enc_clk_val[0];
int i = sizeof(setting_enc_clk_val) / sizeof(enc_clk_val_t);
int j = 0;
printf("mode is: %d\n", mode);
for (j = 0; j < i; j++){
if(mode == p_enc[j].mode)
break;
}
set_viu_path(p_enc[j].viu_path, p_enc[j].viu_type);
set_hpll_clk_out(p_enc[j].hpll_clk_out);
set_hpll_lvds_od(p_enc[j].hpll_lvds_od);
set_hpll_hdmi_od(p_enc[j].hpll_hdmi_od);
set_vid_pll_div(p_enc[j].vid_pll_div);
set_clk_final_div(p_enc[j].clk_final_div);
set_hdmi_tx_pixel_div(p_enc[j].hdmi_tx_pixel_div);
set_encp_div(p_enc[j].encp_div);
set_enci_div(p_enc[j].enci_div);
set_enct_div(p_enc[j].enct_div);
set_encl_div(p_enc[j].encl_div);
set_vdac0_div(p_enc[j].vdac0_div);
set_vdac1_div(p_enc[j].vdac1_div);
}
void set_vmode_clk(vmode_t mode)
{
enc_clk_val_t *p_enc =NULL;
int i = 0;
int j = 0;
mutex_lock(&setclk_mutex);
if(IS_MESON_M8M2_CPU){
p_enc=&setting_enc_clk_val_m8m2[0];
i = sizeof(setting_enc_clk_val_m8m2) / sizeof(enc_clk_val_t);
}else{
p_enc=&setting_enc_clk_val[0];
i = sizeof(setting_enc_clk_val) / sizeof(enc_clk_val_t);
}
printk("mode is: %d\n", mode);
for (j = 0; j < i; j++){
if(mode == p_enc[j].mode)
break;
}
set_viu_path(p_enc[j].viu_path, p_enc[j].viu_type);
set_hpll_clk_out(p_enc[j].hpll_clk_out);
#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
set_hpll_lvds_od(p_enc[j].hpll_lvds_od);
#endif
mutex_unlock(&setclk_mutex);
set_hpll_hdmi_od(p_enc[j].hpll_hdmi_od);
#if MESON_CPU_TYPE == MESON_CPU_TYPE_MESON8B
if((mode == VMODE_800X600P_60HZ) || (mode == VMODE_1024X600P_60HZ) || (mode == VMODE_1024X768P_60HZ))
aml_set_reg32_bits(P_HHI_VID_PLL_CNTL, 2, 18, 2);
#endif
set_vid_pll_div(p_enc[j].vid_pll_div);
set_clk_final_div(p_enc[j].clk_final_div);
set_hdmi_tx_pixel_div(p_enc[j].hdmi_tx_pixel_div);
set_encp_div(p_enc[j].encp_div);
set_enci_div(p_enc[j].enci_div);
set_enct_div(p_enc[j].enct_div);
set_encl_div(p_enc[j].encl_div);
set_vdac0_div(p_enc[j].vdac0_div);
set_vdac1_div(p_enc[j].vdac1_div);
#if MESON_CPU_TYPE == MESON_CPU_TYPE_MESON6
// If VCO outputs 1488, then we will reset it to exact 1485
// please note, don't forget to re-config CNTL3/4
if(((READ_CBUS_REG(HHI_VID_PLL_CNTL) & 0x7fff) == 0x43e)||((READ_CBUS_REG(HHI_VID_PLL_CNTL) & 0x7fff) == 0x21ef)) {
WRITE_CBUS_REG_BITS(HHI_VID_PLL_CNTL, 0x21ef, 0, 14);
WRITE_CBUS_REG(HHI_VID_PLL_CNTL3, 0x4b525012);
WRITE_CBUS_REG(HHI_VID_PLL_CNTL4, 0x42000101);
}
#endif
// For debug only
#if 0
printk("hdmi debug tag\n%s\n%s[%d]\n", __FILE__, __FUNCTION__, __LINE__);
#define P(a) printk("%s 0x%04x: 0x%08x\n", #a, a, READ_CBUS_REG(a))
P(HHI_VID_PLL_CNTL);
P(HHI_VID_DIVIDER_CNTL);
P(HHI_VID_CLK_CNTL);
P(HHI_VID_CLK_DIV);
P(HHI_HDMI_CLK_CNTL);
P(HHI_VIID_CLK_DIV);
#define PP(a) printk("%s(%d): %d MHz\n", #a, a, clk_util_clk_msr(a))
PP(CTS_PWM_A_CLK );
PP(CTS_PWM_B_CLK );
PP(CTS_PWM_C_CLK );
PP(CTS_PWM_D_CLK );
PP(CTS_ETH_RX_TX );
PP(CTS_PCM_MCLK );
PP(CTS_PCM_SCLK );
PP(CTS_VDIN_MEAS_CLK );
PP(CTS_VDAC_CLK1 );
PP(CTS_HDMI_TX_PIXEL_CLK);
PP(CTS_MALI_CLK );
PP(CTS_SDHC_CLK1 );
PP(CTS_SDHC_CLK0 );
PP(CTS_AUDAC_CLKPI );
PP(CTS_A9_CLK );
PP(CTS_DDR_CLK );
PP(CTS_VDAC_CLK0 );
PP(CTS_SAR_ADC_CLK );
PP(CTS_ENCI_CLK );
PP(SC_CLK_INT );
PP(USB_CLK_12MHZ );
PP(LVDS_FIFO_CLK );
PP(HDMI_CH3_TMDSCLK );
PP(MOD_ETH_CLK50_I );
PP(MOD_AUDIN_AMCLK_I );
PP(CTS_BTCLK27 );
PP(CTS_HDMI_SYS_CLK );
PP(CTS_LED_PLL_CLK );
PP(CTS_VGHL_PLL_CLK );
PP(CTS_FEC_CLK_2 );
PP(CTS_FEC_CLK_1 );
PP(CTS_FEC_CLK_0 );
PP(CTS_AMCLK );
PP(VID2_PLL_CLK );
PP(CTS_ETH_RMII );
PP(CTS_ENCT_CLK );
PP(CTS_ENCL_CLK );
PP(CTS_ENCP_CLK );
PP(CLK81 );
PP(VID_PLL_CLK );
PP(AUD_PLL_CLK );
PP(MISC_PLL_CLK );
PP(DDR_PLL_CLK );
PP(SYS_PLL_CLK );
PP(AM_RING_OSC_CLK_OUT1 );
PP(AM_RING_OSC_CLK_OUT0 );
#endif
}
void set_vmode_clk(vmode_t mode)
{
int i = 0;
int j = 0;
hw_enc_clk_val_t *p_enc =NULL;
hpll_load_initial();
printk("set_vmode_clk mode is %d\n", mode);
#if 0
if( (VMODE_576CVBS==mode) || (VMODE_480CVBS==mode) )
{
printk("g9tv: cvbs clk!\n");
aml_write_reg32_d(P_HHI_HDMI_PLL_CNTL, 0x5000022d);
aml_write_reg32_d(P_HHI_HDMI_PLL_CNTL2, 0x00890000);
aml_write_reg32_d(P_HHI_HDMI_PLL_CNTL3, 0x135c5091);
aml_write_reg32_d(P_HHI_HDMI_PLL_CNTL4, 0x801da72c);
// P_HHI_HDMI_PLL_CNTL5
// 0x71c86900 for div2 disable inside PLL2 of HPLL
// 0x71486900 for div2 enable inside PLL2 of HPLL
aml_write_reg32_d(P_HHI_HDMI_PLL_CNTL5, 0x71c86900);
aml_write_reg32_d(P_HHI_HDMI_PLL_CNTL6, 0x00000e55);
aml_write_reg32_d(P_HHI_HDMI_PLL_CNTL, 0x4000022d);
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL);
clocks_set_vid_clk_div(CLK_UTIL_VID_PLL_DIV_5);
// select vid_pll_clk for muxing
aml_write_reg32_d(P_HHI_VID_CLK_CNTL, (aml_read_reg32_d(P_HHI_VID_CLK_CNTL)&(~(0x7<<16))) );
// disable divider for clk_rst_tst()
aml_write_reg32_d(P_HHI_VID_CLK_DIV, (aml_read_reg32_d(P_HHI_VID_CLK_DIV)&(~0xff)) );
// select clk_div1 for enci clk muxing
aml_write_reg32_d(P_HHI_VID_CLK_DIV, (aml_read_reg32_d(P_HHI_VID_CLK_DIV)&(~(0xf<<28))) );
// select clk_div1 for vdac clk muxing
aml_write_reg32_d(P_HHI_VIID_CLK_DIV, (aml_read_reg32_d(P_HHI_VIID_CLK_DIV)&(~(0x1<<19))) );
aml_write_reg32_d(P_HHI_VIID_CLK_DIV, (aml_read_reg32_d(P_HHI_VIID_CLK_DIV)&(~(0xf<<28))) );
// clk gate for enci(bit0) and vdac(bit4)
aml_write_reg32_d(P_HHI_VID_CLK_CNTL2, (aml_read_reg32_d(P_HHI_VID_CLK_CNTL2)|0x1|(0x1<<4)) );
return;
}
if(!vmode_clk_match(mode)) {
}
#endif
p_enc=&setting_enc_clk_val[0];
i = sizeof(setting_enc_clk_val) / sizeof(enc_clk_val_t);
printk("mode is: %d\n", mode);
for (j = 0; j < i; j++){
if(mode == p_enc[j].mode)
break;
}
set_viu_path(p_enc[j].viu_path, p_enc[j].viu_type);
set_hdmitx_sys_clk();
set_hpll_clk_out(p_enc[j].hpll_clk_out);
set_hpll_od1(p_enc[j].od1);
set_hpll_od2(p_enc[j].od2);
set_hpll_od3(p_enc[j].od3);
set_hpll_od3_clk_div(p_enc[j].vid_pll_div);
printk("j = %d vid_clk_div = %d\n", j, p_enc[j].vid_clk_div); //???
set_vid_clk_div(p_enc[j].vid_clk_div);
set_hdmi_tx_pixel_div(p_enc[j].hdmi_tx_pixel_div);
set_encp_div(p_enc[j].encp_div);
set_enci_div(p_enc[j].enci_div);
set_encl_div(p_enc[j].encl_div);
set_vdac0_div(p_enc[j].vdac0_div);
return;
}
void set_vmode_clk(vmode_t mode)
{
enc_clk_val_t *p_enc = &setting_enc_clk_val[0];
int i = sizeof(setting_enc_clk_val) / sizeof(enc_clk_val_t);
int j = 0;
printk("mode is: %d\n", mode);
for (j = 0; j < i; j++){
if(mode == p_enc[j].mode)
break;
}
set_viu_path(p_enc[j].viu_path, p_enc[j].viu_type);
set_hpll_clk_out(p_enc[j].hpll_clk_out);
set_hpll_hdmi_od(p_enc[j].hpll_hdmi_od);
set_vid_pll_div(p_enc[j].vid_pll_div);
set_clk_final_div(p_enc[j].clk_final_div);
set_hdmi_tx_pixel_div(p_enc[j].hdmi_tx_pixel_div);
set_encp_div(p_enc[j].encp_div);
set_enci_div(p_enc[j].enci_div);
set_enct_div(p_enc[j].enct_div);
set_encl_div(p_enc[j].encl_div);
set_vdac0_div(p_enc[j].vdac0_div);
set_vdac1_div(p_enc[j].vdac1_div);
// For debug only
#if 0
printk("hdmi debug tag\n%s\n%s[%d]\n", __FILE__, __FUNCTION__, __LINE__);
#define P(a) printk("%s 0x%04x: 0x%08x\n", #a, a, READ_CBUS_REG(a))
P(HHI_VID_PLL_CNTL);
P(HHI_VID_DIVIDER_CNTL);
P(HHI_VID_CLK_CNTL);
P(HHI_VID_CLK_DIV);
P(HHI_HDMI_CLK_CNTL);
P(HHI_VIID_CLK_DIV);
#define PP(a) printk("%s(%d): %d MHz\n", #a, a, clk_util_clk_msr(a))
PP(CTS_PWM_A_CLK );
PP(CTS_PWM_B_CLK );
PP(CTS_PWM_C_CLK );
PP(CTS_PWM_D_CLK );
PP(CTS_ETH_RX_TX );
PP(CTS_PCM_MCLK );
PP(CTS_PCM_SCLK );
PP(CTS_VDIN_MEAS_CLK );
PP(CTS_VDAC_CLK1 );
PP(CTS_HDMI_TX_PIXEL_CLK);
PP(CTS_MALI_CLK );
PP(CTS_SDHC_CLK1 );
PP(CTS_SDHC_CLK0 );
PP(CTS_AUDAC_CLKPI );
PP(CTS_A9_CLK );
PP(CTS_DDR_CLK );
PP(CTS_VDAC_CLK0 );
PP(CTS_SAR_ADC_CLK );
PP(CTS_ENCI_CLK );
PP(SC_CLK_INT );
PP(USB_CLK_12MHZ );
PP(LVDS_FIFO_CLK );
PP(HDMI_CH3_TMDSCLK );
PP(MOD_ETH_CLK50_I );
PP(MOD_AUDIN_AMCLK_I );
PP(CTS_BTCLK27 );
PP(CTS_HDMI_SYS_CLK );
PP(CTS_LED_PLL_CLK );
PP(CTS_VGHL_PLL_CLK );
PP(CTS_FEC_CLK_2 );
PP(CTS_FEC_CLK_1 );
PP(CTS_FEC_CLK_0 );
PP(CTS_AMCLK );
PP(VID2_PLL_CLK );
PP(CTS_ETH_RMII );
PP(CTS_ENCT_CLK );
PP(CTS_ENCL_CLK );
PP(CTS_ENCP_CLK );
PP(CLK81 );
PP(VID_PLL_CLK );
PP(AUD_PLL_CLK );
PP(MISC_PLL_CLK );
PP(DDR_PLL_CLK );
PP(SYS_PLL_CLK );
PP(AM_RING_OSC_CLK_OUT1 );
PP(AM_RING_OSC_CLK_OUT0 );
#endif
}