void __init init_apic_mappings(void) { unsigned long apic_phys; /* * If no local APIC can be found then set up a fake all * zeroes page to simulate the local APIC and another * one for the IO-APIC. */ if (!smp_found_config && detect_init_APIC()) { apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); apic_phys = __pa(apic_phys); } else apic_phys = mp_lapic_addr; set_fixmap_nocache(FIX_APIC_BASE, apic_phys); Dprintk("mapped APIC to %08lx (%08lx)\n", APIC_BASE, apic_phys); /* * Fetch the APIC ID of the BSP in case we have a * default configuration (or the MP table is broken). */ if (boot_cpu_id == -1U) boot_cpu_id = GET_APIC_ID(apic_read(APIC_ID)); #ifdef CONFIG_X86_IO_APIC { unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; int i; for (i = 0; i < nr_ioapics; i++) { if (smp_found_config) { ioapic_phys = mp_ioapics[i].mpc_apicaddr; if (!ioapic_phys) { printk(KERN_ERR "WARNING: bogus zero IO-APIC address found in MPTABLE, disabling IO-APIC support\n"); smp_found_config = 0; skip_ioapic_setup = 1; goto fake_ioapic_page; } } else { fake_ioapic_page: ioapic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); ioapic_phys = __pa(ioapic_phys); } set_fixmap_nocache(idx, ioapic_phys); Dprintk("mapped IOAPIC to %08lx (%08lx)\n", __fix_to_virt(idx), ioapic_phys); idx++; } } #endif }
void __init init_apic_mappings(void) { unsigned long apic_phys; /* * If no local APIC can be found then set up a fake all * zeroes page to simulate the local APIC and another * one for the IO-APIC. */ if (!smp_found_config && detect_init_APIC()) { apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); apic_phys = __pa(apic_phys); } else apic_phys = mp_lapic_addr; set_fixmap_nocache(FIX_APIC_BASE, apic_phys); apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", APIC_BASE, apic_phys); /* Put local APIC into the resource map. */ lapic_resource.start = apic_phys; lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; insert_resource(&iomem_resource, &lapic_resource); /* * Fetch the APIC ID of the BSP in case we have a * default configuration (or the MP table is broken). */ boot_cpu_id = GET_APIC_ID(apic_read(APIC_ID)); { unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; int i; struct resource *ioapic_res; ioapic_res = ioapic_setup_resources(); for (i = 0; i < nr_ioapics; i++) { if (smp_found_config) { ioapic_phys = mp_ioapics[i].mpc_apicaddr; } else { ioapic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); ioapic_phys = __pa(ioapic_phys); } set_fixmap_nocache(idx, ioapic_phys); apic_printk(APIC_VERBOSE, "mapped IOAPIC to %016lx (%016lx)\n", __fix_to_virt(idx), ioapic_phys); idx++; if (ioapic_res != NULL) { ioapic_res->start = ioapic_phys; ioapic_res->end = ioapic_phys + (4 * 1024) - 1; ioapic_res++; } } } }
/** * init_apic_mappings - initialize APIC mappings */ void __init init_apic_mappings(void) { /* * If no local APIC can be found then set up a fake all * zeroes page to simulate the local APIC and another * one for the IO-APIC. */ if (!smp_found_config && detect_init_APIC()) { apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); apic_phys = __pa(apic_phys); } else apic_phys = mp_lapic_addr; set_fixmap_nocache(FIX_APIC_BASE, apic_phys); apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", APIC_BASE, apic_phys); /* Put local APIC into the resource map. */ lapic_resource.start = apic_phys; lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; insert_resource(&iomem_resource, &lapic_resource); /* * Fetch the APIC ID of the BSP in case we have a * default configuration (or the MP table is broken). */ boot_cpu_id = GET_APIC_ID(apic_read(APIC_ID)); }
/* * map IGD MMIO+0x2000 page to allow Xen access to IGD 3D register. */ static void *map_igd_reg(void) { u64 igd_mmio, igd_reg; if ( !is_cantiga_b3 && !is_snb_gfx ) return NULL; if ( igd_reg_va ) return igd_reg_va; /* get IGD mmio address in PCI BAR */ igd_mmio = ((u64)pci_conf_read32(0, IGD_DEV, 0, 0x14) << 32) + pci_conf_read32(0, IGD_DEV, 0, 0x10); /* offset of IGD regster we want to access is in 0x2000 range */ igd_reg = (igd_mmio & IGD_BAR_MASK) + 0x2000; /* ioremap this physical page */ #if defined(CONFIG_X86) set_fixmap_nocache(FIX_IGD_MMIO, igd_reg); igd_reg_va = (u8 *)fix_to_virt(FIX_IGD_MMIO); #else igd_reg_va = ioremap_nocache(igd_reg, 0x100); #endif return igd_reg_va; }
void mrfld_early_console_init(void) { u32 ctrlr0 = 0; set_fixmap_nocache(FIX_EARLYCON_MEM_BASE, MRFLD_REGBASE_SSP5); pssp = (void *)(__fix_to_virt(FIX_EARLYCON_MEM_BASE) + (MRFLD_REGBASE_SSP5 & (PAGE_SIZE - 1))); if (intel_mid_identify_sim() == INTEL_MID_CPU_SIMULATION_NONE) ssp_timing_wr = 1; /* mask interrupts, clear enable and set DSS config */ /* SSPSCLK on active transfers only */ if (intel_mid_identify_sim() != INTEL_MID_CPU_SIMULATION_SLE) { if (ssp_timing_wr) { dw_writel(pssp, ctrl0, 0xc12c0f); dw_writel(pssp, ctrl1, 0x0); } else { dw_writel(pssp, ctrl0, 0xc0000f); dw_writel(pssp, ctrl1, 0x10000000); } } dw_readl(pssp, sr); /* enable port */ if (intel_mid_identify_sim() != INTEL_MID_CPU_SIMULATION_SLE) { ctrlr0 = dw_readl(pssp, ctrl0); ctrlr0 |= 0x80; dw_writel(pssp, ctrl0, ctrlr0); } }
void __init init_apic_mappings(void) { unsigned long apic_phys; if ( x2apic_enabled ) goto __next; /* * If no local APIC can be found then set up a fake all * zeroes page to simulate the local APIC and another * one for the IO-APIC. */ if (!smp_found_config && detect_init_APIC()) { apic_phys = __pa(alloc_xenheap_page()); clear_page(__va(apic_phys)); } else apic_phys = mp_lapic_addr; set_fixmap_nocache(FIX_APIC_BASE, apic_phys); apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n", APIC_BASE, apic_phys); __next: /* * Fetch the APIC ID of the BSP in case we have a * default configuration (or the MP table is broken). */ if (boot_cpu_physical_apicid == -1U) boot_cpu_physical_apicid = get_apic_id(); x86_cpu_to_apicid[0] = get_apic_id(); init_ioapic_mappings(); }
static void ce4100_serial_fixup(int port, struct uart_port *up, unsigned short *capabilites) { #ifdef CONFIG_EARLY_PRINTK /* * Over ride the legacy port configuration that comes from * asm/serial.h. Using the ioport driver then switching to the * PCI memmaped driver hangs the IOAPIC */ if (up->iotype != UPIO_MEM32) { up->uartclk = 14745600; up->mapbase = 0xdffe0200; set_fixmap_nocache(FIX_EARLYCON_MEM_BASE, up->mapbase & PAGE_MASK); up->membase = (void __iomem *)__fix_to_virt(FIX_EARLYCON_MEM_BASE); up->membase += up->mapbase & ~PAGE_MASK; up->mapbase += port * 0x100; up->membase += port * 0x100; up->iotype = UPIO_MEM32; up->regshift = 2; up->irq = 4; } #endif up->iobase = 0; up->serial_in = ce4100_mem_serial_in; up->serial_out = ce4100_mem_serial_out; *capabilites |= (1 << 12); }
void __init init_apic_mappings(void) { unsigned int new_apicid; if (x2apic_mode) { boot_cpu_physical_apicid = read_apic_id(); return; } if (!smp_found_config && detect_init_APIC()) { pr_info("APIC: disable apic facility\n"); apic_disable(); } else { apic_phys = mp_lapic_addr; if (!acpi_lapic) set_fixmap_nocache(FIX_APIC_BASE, apic_phys); apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n", APIC_BASE, apic_phys); } new_apicid = read_apic_id(); if (boot_cpu_physical_apicid != new_apicid) { boot_cpu_physical_apicid = new_apicid; apic_version[new_apicid] = GET_APIC_VERSION(apic_read(APIC_LVR)); } }
static inline void pci_exp_set_dev_base(unsigned int base, int bus, int devfn) { u32 dev_base = base | (bus << 20) | (devfn << 12); if (dev_base != mmcfg_last_accessed_device) { mmcfg_last_accessed_device = dev_base; set_fixmap_nocache(FIX_PCIE_MCFG, dev_base); } }
void __init init_apic_mappings(void) { unsigned long apic_phys; /* * If no local APIC can be found then set up a fake all * zeroes page to simulate the local APIC and another * one for the IO-APIC. */ if (!smp_found_config && detect_init_APIC()) { apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); apic_phys = __pa(apic_phys); } else apic_phys = mp_lapic_addr; set_fixmap_nocache(FIX_APIC_BASE, apic_phys); apic_printk(APIC_VERBOSE,"mapped APIC to %16lx (%16lx)\n", APIC_BASE, apic_phys); /* * Fetch the APIC ID of the BSP in case we have a * default configuration (or the MP table is broken). */ boot_cpu_id = GET_APIC_ID(apic_read(APIC_ID)); #ifdef CONFIG_X86_IO_APIC { unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; int i; for (i = 0; i < nr_ioapics; i++) { if (smp_found_config) { ioapic_phys = mp_ioapics[i].mpc_apicaddr; } else { ioapic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); ioapic_phys = __pa(ioapic_phys); } set_fixmap_nocache(idx, ioapic_phys); apic_printk(APIC_VERBOSE,"mapped IOAPIC to %016lx (%016lx)\n", __fix_to_virt(idx), ioapic_phys); idx++; } } #endif }
void __init mp_sfi_register_lapic_address(unsigned long address) { mp_lapic_addr = address; set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr); if (boot_cpu_physical_apicid == -1U) boot_cpu_physical_apicid = read_apic_id(); pr_info("Boot CPU = %d\n", boot_cpu_physical_apicid); }
static int __init parse_options(struct early_serial8250_device *device, char *options) { struct uart_port *port = &device->port; int mmio, length; if (!options) return -ENODEV; port->uartclk = BASE_BAUD * 16; if (!strncmp(options, "mmio,", 5)) { port->iotype = UPIO_MEM; port->mapbase = simple_strtoul(options + 5, &options, 0); #ifdef CONFIG_FIX_EARLYCON_MEM set_fixmap_nocache(FIX_EARLYCON_MEM_BASE, port->mapbase & PAGE_MASK); port->membase = (void __iomem *)__fix_to_virt(FIX_EARLYCON_MEM_BASE); port->membase += port->mapbase & ~PAGE_MASK; #else port->membase = ioremap_nocache(port->mapbase, 64); if (!port->membase) { printk(KERN_ERR "%s: Couldn't ioremap 0x%llx\n", __func__, (unsigned long long)port->mapbase); return -ENOMEM; } #endif mmio = 1; } else if (!strncmp(options, "io,", 3)) { port->iotype = UPIO_PORT; port->iobase = simple_strtoul(options + 3, &options, 0); mmio = 0; } else return -EINVAL; options = strchr(options, ','); if (options) { options++; device->baud = simple_strtoul(options, NULL, 0); length = min(strcspn(options, " "), sizeof(device->options)); strncpy(device->options, options, length); } else { device->baud = probe_baud(port); snprintf(device->options, sizeof(device->options), "%u", device->baud); } printk(KERN_INFO "Early serial console at %s 0x%llx (options '%s')\n", mmio ? "MMIO" : "I/O port", mmio ? (unsigned long long) port->mapbase : (unsigned long long) port->iobase, device->options); return 0; }
/* * This is always called under pci_config_lock */ static void pci_exp_set_dev_base(unsigned int base, int bus, int devfn) { u32 dev_base = base | PCI_MMCFG_BUS_OFFSET(bus) | (devfn << 12); int cpu = smp_processor_id(); if (dev_base != mmcfg_last_accessed_device || cpu != mmcfg_last_accessed_cpu) { mmcfg_last_accessed_device = dev_base; mmcfg_last_accessed_cpu = cpu; set_fixmap_nocache(FIX_PCIE_MCFG, dev_base); } }
void __init early_init_lapic_mapping(void) { if (!smp_found_config) return; set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr); apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", APIC_BASE, mp_lapic_addr); boot_cpu_physical_apicid = read_apic_id(); }
/* * paging_init() sets up the page tables */ void __init paging_init(void) { unsigned long max_zone_pfns[MAX_NR_ZONES]; int nid; /* We don't need to map the kernel through the TLB, as * it is permanatly mapped using P1. So clear the * entire pgd. */ memset(swapper_pg_dir, 0, sizeof(swapper_pg_dir)); /* Set an initial value for the MMU.TTB so we don't have to * check for a null value. */ set_TTB(swapper_pg_dir); /* Populate the relevant portions of swapper_pg_dir so that * we can use the fixmap entries without calling kmalloc. * pte's will be filled in by __set_fixmap(). */ page_table_range_init(FIXADDR_START, FIXADDR_TOP, swapper_pg_dir); memset(max_zone_pfns, 0, sizeof(max_zone_pfns)); for_each_online_node(nid) { pg_data_t *pgdat = NODE_DATA(nid); unsigned long low, start_pfn; start_pfn = pgdat->bdata->node_min_pfn; low = pgdat->bdata->node_low_pfn; if (max_zone_pfns[ZONE_NORMAL] < low) max_zone_pfns[ZONE_NORMAL] = low; printk("Node %u: start_pfn = 0x%lx, low = 0x%lx\n", nid, start_pfn, low); } free_area_init_nodes(max_zone_pfns); #ifdef CONFIG_SUPERH32 /* Set up the uncached fixmap */ set_fixmap_nocache(FIX_UNCACHED, __pa(&__uncached_start)); #ifdef CONFIG_29BIT /* * Handle trivial transitions between cached and uncached * segments, making use of the 1:1 mapping relationship in * 512MB lowmem. */ cached_to_uncached = P2SEG - P1SEG; #endif #endif }
/* * paging_init() sets up the page tables */ void __init paging_init(void) { unsigned long max_zone_pfns[MAX_NR_ZONES]; unsigned long vaddr; int nid; /* We don't need to map the kernel through the TLB, as * it is permanatly mapped using P1. So clear the * entire pgd. */ memset(swapper_pg_dir, 0, sizeof(swapper_pg_dir)); /* Set an initial value for the MMU.TTB so we don't have to * check for a null value. */ set_TTB(swapper_pg_dir); /* * Populate the relevant portions of swapper_pg_dir so that * we can use the fixmap entries without calling kmalloc. * pte's will be filled in by __set_fixmap(). */ vaddr = __fix_to_virt(__end_of_fixed_addresses - 1) & PMD_MASK; page_table_range_init(vaddr, 0, swapper_pg_dir); kmap_coherent_init(); memset(max_zone_pfns, 0, sizeof(max_zone_pfns)); for_each_online_node(nid) { pg_data_t *pgdat = NODE_DATA(nid); unsigned long low, start_pfn; start_pfn = pgdat->bdata->node_min_pfn; low = pgdat->bdata->node_low_pfn; if (max_zone_pfns[ZONE_NORMAL] < low) max_zone_pfns[ZONE_NORMAL] = low; printk("Node %u: start_pfn = 0x%lx, low = 0x%lx\n", nid, start_pfn, low); } free_area_init_nodes(max_zone_pfns); /* Set up the uncached fixmap */ set_fixmap_nocache(FIX_UNCACHED, __pa(&__uncached_start)); }
/** * Creates a kernel mapping for the local APIC. * * The hardware/platform/BIOS maps each CPU's local APIC at the same location * in physical memory. This function uses the 'fixmap' to map the local APIC * into the kernel's virtual memory space at a fixed virtual address that is * known at compile time. Since the local APIC's virtual address is known * at compile time, local APIC registers can be accessed directly, without * any pointer dereferencing. */ void __init lapic_map(void) { if (!cpu_has_apic) panic("No local APIC."); /* Reserve physical memory used by the local APIC */ lapic_resource.start = lapic_phys_addr; lapic_resource.end = lapic_phys_addr + 4096 - 1; request_resource(&iomem_resource, &lapic_resource); /* Map local APIC into the kernel */ set_fixmap_nocache(FIX_APIC_BASE, lapic_phys_addr); printk(KERN_DEBUG "Local APIC mapped to virtual address 0x%016lx\n", fix_to_virt(FIX_APIC_BASE)); }
int hpet_arch_init(void) { unsigned int id; u64 tmp; if (!hpet_address) return -1; set_fixmap_nocache(FIX_HPET_BASE, hpet_address); __set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VSYSCALL_NOCACHE); /* * Read the period, compute tick and quotient. */ id = hpet_readl(HPET_ID); if (!(id & HPET_ID_VENDOR) || !(id & HPET_ID_NUMBER)) return -1; hpet_period = hpet_readl(HPET_PERIOD); if (hpet_period < 100000 || hpet_period > 100000000) return -1; hpet_tick = (FSEC_PER_TICK + hpet_period / 2) / hpet_period; hpet_use_timer = (id & HPET_ID_LEGSUP); /* * hpet period is in femto seconds per cycle * so we need to convert this to ns/cyc units * aproximated by mult/2^shift * * fsec/cyc * 1nsec/1000000fsec = nsec/cyc = mult/2^shift * fsec/cyc * 1ns/1000000fsec * 2^shift = mult * fsec/cyc * 2^shift * 1nsec/1000000fsec = mult * (fsec/cyc << shift)/1000000 = mult * (hpet_period << shift)/FSEC_PER_NSEC = mult */ tmp = (u64)hpet_period << HPET_SHIFT; do_div(tmp, FSEC_PER_NSEC); clocksource_hpet.mult = (u32)tmp; clocksource_register(&clocksource_hpet); return hpet_timer_stop_set_go(hpet_tick); }
static void ce4100_serial_fixup(int port, struct uart_port *up, unsigned short *capabilites) { #ifdef CONFIG_EARLY_PRINTK if (up->iotype != UPIO_MEM32) { up->uartclk = 14745600; up->mapbase = 0xdffe0200; set_fixmap_nocache(FIX_EARLYCON_MEM_BASE, up->mapbase & PAGE_MASK); up->membase = (void __iomem *)__fix_to_virt(FIX_EARLYCON_MEM_BASE); up->membase += up->mapbase & ~PAGE_MASK; up->iotype = UPIO_MEM32; up->regshift = 2; } #endif up->iobase = 0; up->serial_in = ce4100_mem_serial_in; up->serial_out = ce4100_mem_serial_out; *capabilites |= (1 << 12); }
void __init early_init_lapic_mapping(void) { unsigned long phys_addr; /* * If no local APIC can be found then go out * : it means there is no mpatable and MADT */ if (!smp_found_config) return; phys_addr = mp_lapic_addr; set_fixmap_nocache(FIX_APIC_BASE, phys_addr); apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", APIC_BASE, phys_addr); /* * Fetch the APIC ID of the BSP in case we have a * default configuration (or the MP table is broken). */ boot_cpu_physical_apicid = GET_APIC_ID(read_apic_id()); }
static int lapic_resume(struct sys_device *dev) { unsigned int l, h; unsigned long flags; if (!apic_pm_state.active) return 0; /* XXX: Pavel needs this for S3 resume, but can't explain why */ set_fixmap_nocache(FIX_APIC_BASE, APIC_DEFAULT_PHYS_BASE); local_irq_save(flags); rdmsr(MSR_IA32_APICBASE, l, h); l &= ~MSR_IA32_APICBASE_BASE; l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE; wrmsr(MSR_IA32_APICBASE, l, h); apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); apic_write(APIC_ID, apic_pm_state.apic_id); apic_write(APIC_DFR, apic_pm_state.apic_dfr); apic_write(APIC_LDR, apic_pm_state.apic_ldr); apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); apic_write(APIC_SPIV, apic_pm_state.apic_spiv); apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); apic_write(APIC_TMICT, apic_pm_state.apic_tmict); apic_write(APIC_ESR, 0); apic_read(APIC_ESR); apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); apic_write(APIC_ESR, 0); apic_read(APIC_ESR); local_irq_restore(flags); return 0; }
static void early_pti_write_to_aperture(struct pti_masterchannel *mc, u8 *buf, int len) { int dwordcnt, final, i; u32 ptiword; u8 *p ; u32 pti_phys_address ; u32 __iomem *aperture; p = buf; /* calculate the aperture offset from the base using the master and channel id's. */ pti_phys_address = PTI_ADDRESS + (mc->master << 15) + (mc->channel << 8); set_fixmap_nocache(FIX_EARLYCON_MEM_BASE, pti_phys_address); aperture = (void *)(__fix_to_virt(FIX_EARLYCON_MEM_BASE) + (pti_phys_address & (PAGE_SIZE - 1))); dwordcnt = len >> 2; final = len - (dwordcnt << 2); /* final = trailing bytes */