/* ************************************************************************************************************ * * function * * name : * * parmeters : * * return : * * note : * * ************************************************************************************************************ */ int main(void) { __s32 dram_size=0; timer_init(); //serial init sunxi_serial_init(fes1_head.prvt_head.uart_port, (void *)fes1_head.prvt_head.uart_ctrl, 2); set_pll(); //enable gpio gate set_gpio_gate(); //dram init printf("beign to init dram\n"); #ifdef FPGA_PLATFORM dram_size = mctl_init((void *)fes1_head.prvt_head.dram_para); #else dram_size = init_DRAM(0, (void *)fes1_head.prvt_head.dram_para); #endif if (dram_size) { note_dram_log(1); printf("init dram ok\n"); } else { note_dram_log(0); printf("init dram fail\n"); } __msdelay(10); return dram_size; }
/* ************************************************************************************************************ * * function * * name : * * parmeters : * * return : * * note : * * ************************************************************************************************************ */ int main(void) { __s32 dram_size=0; timer_init(); #ifdef CONFIG_ARCH_SUN9IW1P1 if(readl(CCM_PLL1_C0_CTRL)) { set_pll(); } #elif defined(CONFIG_ARCH_SUN8IW6P1) if(readl(CCMU_PLL_C0CPUX_CTRL_REG)) { set_pll(); } #else set_pll(); #endif //serial init sunxi_serial_init(fes1_head.prvt_head.uart_port, (void *)fes1_head.prvt_head.uart_ctrl, 2); //enable gpio gate set_gpio_gate(); //dram init printf("beign to init dram\n"); dram_size = init_DRAM(0, (void *)fes1_head.prvt_head.dram_para); if (dram_size) { note_dram_log(1); printf("init dram ok\n"); } else { note_dram_log(0); printf("init dram fail\n"); } __msdelay(10); return dram_size; }