void cycle5 (void) {
if (do_cycle5 == 1) {
// Set Halt
set_halt_until_mbus_tx();
// Copy SRAM data into Flash SRAM (bulk)
// Source Addr: 0x00000000 ~ 0x0000000F (16 words)
// Target Addr: 0x00000000~
mbus_copy_mem_from_local_to_remote_bulk (FLS_ADDR, 0x00000000, 0x00000000, 15);
// Put the Flash SRAM data on the bus (to NODE_A)
set_halt_until_mbus_fwd();
mbus_copy_mem_from_remote_to_any_bulk (FLS_ADDR, 0x00000000, NODE_A_ADDR, 0x00000000, 15);
// Put the Flash SRAM data (very long) on the bus (to NODE_B)
set_halt_until_mbus_tx();
mbus_copy_mem_from_remote_to_any_bulk (FLS_ADDR, 0x00000000, NODE_B_ADDR, 0x00000000, 127);
// Halt CPU
set_halt_until_mbus_fwd(); // CPU will resume when an MBus FWD operation is done.
halt_cpu(); // Halt CPU!
// Read FLS's REG#0x23 ~ REG#0x27 (5 Registers)
set_halt_until_mbus_rx();
mbus_copy_registers_from_remote_to_local (FLS_ADDR, 0x23, 0x00, 4);
// Put those register values on the bus (to an fake address)
set_halt_until_mbus_tx();
mbus_copy_registers_from_local_to_remote (0xD, 0x15, 0x00, 4);
}
}
void cycle6 (void) {
if (do_cycle6 == 1) {
// Set Halt
set_halt_until_mbus_tx();
// Copy SRAM data into Flash SRAM (stream)
// From 0x00000000, a quarter of SRAM
mbus_copy_mem_from_local_to_remote_stream (0, FLS_ADDR, 0x00000000, 511);
// Put the Flash SRAM data on the bus (to NODE_A)
set_halt_until_mbus_fwd();
mbus_copy_mem_from_remote_to_any_stream (0, FLS_ADDR, 0x00000000, NODE_A_ADDR, 511);
// Put the Flash SRAM data (very long) on the bus (to NODE_B). I will use halt_cpu() here.
set_halt_until_mbus_tx();
mbus_copy_mem_from_remote_to_any_stream (1, FLS_ADDR, 0x00000000, NODE_B_ADDR, 511);
// Halt CPU
set_halt_until_mbus_fwd(); // CPU will resume when an MBus FWD operation is done.
halt_cpu(); // Halt CPU!
// Set Halt
set_halt_until_mbus_tx();
}
}
static void send_radio_data_ppm(bool last_packet, uint32_t radio_data){
// Write Data: Only up to 24bit data for now
radv9_r3.RAD_FSM_DATA = radio_data;
mbus_remote_register_write(RAD_ADDR,3,radv9_r3.as_int);
if (!radio_ready){
radio_ready = 1;
// Release FSM Reset
radv9_r13.RAD_FSM_RESETn = 1;
mbus_remote_register_write(RAD_ADDR,13,radv9_r13.as_int);
delay(MBUS_DELAY);
}
#ifdef DEBUG_MBUS_MSG
mbus_write_message32(0xBB, 0x0);
#endif
// Set CPU Halt Option as RX --> Use for register read e.g.
set_halt_until_mbus_rx();
// Fire off data
uint32_t count;
mbus_msg_flag = 0;
radv9_r13.RAD_FSM_ENABLE = 1;
mbus_remote_register_write(RAD_ADDR,13,radv9_r13.as_int);
for( count=0; count<RADIO_TIMEOUT_COUNT; count++ ){
if( mbus_msg_flag ){
set_halt_until_mbus_tx();
mbus_msg_flag = 0;
if (last_packet){
radio_ready = 0;
radio_power_off();
}else{
radv9_r13.RAD_FSM_ENABLE = 0;
mbus_remote_register_write(RAD_ADDR,13,radv9_r13.as_int);
}
return;
}else{
delay(MBUS_DELAY);
}
}
// Timeout
set_halt_until_mbus_tx();
mbus_write_message32(0xBB, 0xFAFAFAFA);
}
void VIMv1_load_imem() {
// VIMv1_CTRL power must be on and un-isolated to access IMEM
// Release Sleep
VIMv1_R41_CTRL_POWER.CTRL_RESET = 0x1;
VIMv1_R41_CTRL_POWER.CTRL_ISOLATE = 0x1;
VIMv1_R41_CTRL_POWER.CTRL_SLEEP = 0x0;
mbus_remote_register_write(VIM_ADDR, 0x41, VIMv1_R41_CTRL_POWER.as_int);
// Release Isolation
VIMv1_R41_CTRL_POWER.CTRL_RESET = 0x1;
VIMv1_R41_CTRL_POWER.CTRL_ISOLATE = 0x0;
VIMv1_R41_CTRL_POWER.CTRL_SLEEP = 0x0;
mbus_remote_register_write(VIM_ADDR, 0x41, VIMv1_R41_CTRL_POWER.as_int);
// Enable LC_MEM interface in VIMv1
VIMv1_R40_ENABLE_LC_MEM.DEBUG_CLK_SOURCE = 0x0;
VIMv1_R40_ENABLE_LC_MEM.ENABLE_DEBUG = 0x0;
VIMv1_R40_ENABLE_LC_MEM.ENABLE_LC_MEM = 0x1;
mbus_remote_register_write(VIM_ADDR, 0x40, VIMv1_R40_ENABLE_LC_MEM.as_int);
// Copy the instruction from Flash (Total 2kB)
set_halt_until_mbus_fwd();
mbus_copy_mem_from_remote_to_any_bulk (FLP_ADDR, (uint32_t *) 0x0, VIM_ADDR, (uint32_t *) 0x0, 0x1FF);
set_halt_until_mbus_tx();
// Disable LC_MEM interface in VIMv1
VIMv1_R40_ENABLE_LC_MEM.DEBUG_CLK_SOURCE = 0x0;
VIMv1_R40_ENABLE_LC_MEM.ENABLE_DEBUG = 0x0;
VIMv1_R40_ENABLE_LC_MEM.ENABLE_LC_MEM = 0x0;
mbus_remote_register_write(VIM_ADDR, 0x40, VIMv1_R40_ENABLE_LC_MEM.as_int);
}
void cycle8 (void) {
if (do_cycle8 == 1) {
// Set Halt
set_halt_until_mbus_tx();
// Enable TIMER32 IRQ
clear_all_pend_irq();
*NVIC_ISER = (0 /*GPIO*/ << 16) | (0 /*SPI*/ << 15) | (0 /*GOCEP*/ << 14) | (0 /*MBUS_FWD*/ << 13)
| (0 /*MBUS_TX*/ << 12) | (0 /*MBUS_RX*/ << 11) | (0 /*MEM_WR*/ << 10) | (0 /*REG7*/ << 9)
| (0 /*REG6*/ << 8) | (0 /*REG5*/ << 7) | (0 /*REG4*/ << 6) | (0 /*REG3*/ << 5)
| (0 /*REG2*/ << 4) | (0 /*REG1*/ << 3) | (0 /*REG0*/ << 2)
| (0 /*TIMER16*/ << 1) | (1 /*TIMER32*/ << 0);
// Timer16 with ROI (Reset-On-Interrupt)
config_timer32(/*cmp*/ 0x2000, /*roi*/ 0x1, /*cnt*/ 0x0, /*status*/ 0x0); // Start Timer32. Trigger when it reaches 0x2000. Reset on Interrupt.
// Wait for Interrupt
WFI();
// 1 IRQ: TIMER16
if (irq_history == (1 << 0)) {
pass (0xB, irq_history); irq_history = 0;}
else { fail (0xB, irq_history); }
// Reset Timer16
*TIMER32_GO = 0x0;
*TIMER32_CNT = 0x0;
}
}
void cycle3 (void) {
if (do_cycle3 == 1) {
// Set Halt
set_halt_until_mbus_rx();
// Copy MEM 0x00000000 in FLS and store those in PRE's 0x00001400~
mbus_copy_mem_from_remote_to_any_bulk (FLS_ADDR, 0x00000000, PRE_ADDR, (uint32_t *) 0x00001400, 0);
// Copy MEM 0x00000000~0x0000003C in FLS and store those in PRE's 0x00001500~
mbus_copy_mem_from_remote_to_any_bulk (FLS_ADDR, 0x00000000, PRE_ADDR, (uint32_t *) 0x00001500, 9);
// Before streaming, set the pointer to start from.
*REG_STR0_OFF = 0x00000510;
*REG_STR1_OFF = 0x00000500;
// Copy MEM 0x00000000 in FLS and store those in PRE's 0x00000F9C~
mbus_copy_mem_from_remote_to_any_stream (1, FLS_ADDR, 0x00000000, PRE_ADDR, 0);
if (*REG_STR1_OFF == 0x501) pass (0x4, *REG_STR1_OFF);
else fail (0x4, *REG_STR1_OFF);
// Copy MEM 0x00000000~0x0000003C in FLS and store those in PRE's 0x00000FA0~
mbus_copy_mem_from_remote_to_any_stream (0, FLS_ADDR, 0x00000000, PRE_ADDR, 9);
if (*REG_STR0_OFF == 0x51A) pass (0x5, *REG_STR0_OFF);
else fail (0x5, *REG_STR0_OFF);
// Configre Halt Setting; Now use HALT_UNTIL_MBUS_TX (maybe the most useful one)
set_halt_until_mbus_tx();
}
}
int main() {
// Wakeup timer value
//mbus_write_message32(0xAA,*REG_WUPT_VAL);
// Only enable relevant interrupts (PRCv17)
//enable_reg_irq();
//enable_all_irq();
*NVIC_ISER = (1 << IRQ_WAKEUP) | (1 << IRQ_GOCEP) | (1 << IRQ_TIMER32) | (1 << IRQ_REG0)| (1 << IRQ_REG1)| (1 << IRQ_REG2)| (1 << IRQ_REG3);
// Config watchdog timer to about 10 sec; default: 0x02FFFFFF
config_timerwd(TIMERWD_VAL);
// Initialization sequence
if (enumerated != 0xDEADBEE0){
operation_init();
sns_wakeup_timer_test();
}
set_halt_until_mbus_tx();
mbus_write_message32(0xAA,0xABCD1234);
delay(MBUS_DELAY);
//sns_temp_test();
//set_wakeup_timer(WAKEUP_PERIOD_CONT, 0x1, 0x1);
//mbus_write_message32(0xFF,*REG_WUPT_VAL);
operation_sleep();
while(1);
}
void initialization (void) {
// Disable MBus Watchdog Timer
*REG_MBUS_WD = 0;
// Global Variables
enumerated = 0xDEADBEEF;
cyc_num = 0;
// Enumeration
set_halt_until_mbus_rx();
mbus_enumerate(FLS_ADDR);
mbus_enumerate(PMU_ADDR);
set_halt_until_mbus_tx();
// PMU Optimization
PMU_optimization();
// XO Setting
XO_initialization ();
// Set up XOT timer
uint32_t xot_sat_val_upper = (XOT_SAT_VAL & 0xFFFF0000) >> 16;
uint32_t xot_sat_val_lower = XOT_SAT_VAL & 0x0000FFFF;
*REG_XOT_CONFIGU = xot_sat_val_upper;
*REG_XOT_CONFIG = (0x1 << 17) | (0x1 << 16) | (xot_sat_val_lower << 0);
}
static void operation_init(void){
// Set CPU & Mbus Clock Speeds
prcv13_r0B.CLK_GEN_RING = 0x1; // Default 0x1
prcv13_r0B.CLK_GEN_DIV_MBC = 0x1; // Default 0x1
prcv13_r0B.CLK_GEN_DIV_CORE = 0x3; // Default 0x3
*((volatile uint32_t *) REG_CLKGEN_TUNE ) = prcv13_r0B.as_int;
delay(MBUS_DELAY*20);
//Enumerate & Initialize Registers
Pstack_state = PSTK_IDLE; //0x0;
enumerated = 0xDEADBEEF;
exec_count = 0;
exec_count_irq = 0;
mbus_msg_flag = 0;
// Set CPU Halt Option as RX --> Use for register read e.g.
set_halt_until_mbus_rx();
//Enumeration
mbus_enumerate(RAD_ADDR);
// Set CPU Halt Option as TX --> Use for register write e.g.
set_halt_until_mbus_tx();
// Sleep
operation_sleep_for(2);
operation_sleep_notimer();
}
static void sns_temp_test(void){
// Read temp result
set_halt_until_mbus_rx();
mbus_remote_register_read(SNS_ADDR,0x6,1);
set_halt_until_mbus_tx();
mbus_write_message32(0xC0,*REG1);
// Reset the counter and temp sensor
snsv11_r01.TSNS_RESETn = 0;
mbus_remote_register_write(SNS_ADDR,1,snsv11_r01.as_int);
// Set temp sensor conversion time
snsv11_r03.TSNS_SEL_CONV_TIME = 0x6;
mbus_remote_register_write(SNS_ADDR,0x03,snsv11_r03.as_int);
// Turn on SNS LDO
// snsv11_r00
//snsv11_r00.LDO_VREF_I_AMP = 0;
//snsv11_r00.LDO_SEL_TSNS = 4;
//snsv11_r00.LDO_SEL_CDC = 4;
snsv11_r00.LDO_EN_VREF = 1;
mbus_remote_register_write(SNS_ADDR,0,snsv11_r00.as_int);
delay(MBUS_DELAY*10);
snsv11_r00.LDO_EN_IREF = 1;
snsv11_r00.LDO_EN_TSNS_OUT = 1; // Default: 1
mbus_remote_register_write(SNS_ADDR,0,snsv11_r00.as_int);
delay(MBUS_DELAY*10);
// Turn on digital block
snsv11_r01.TSNS_SEL_LDO = 1;
mbus_remote_register_write(SNS_ADDR,1,snsv11_r01.as_int);
// Turn on analog block
snsv11_r01.TSNS_EN_SENSOR_LDO = 1;
mbus_remote_register_write(SNS_ADDR,1,snsv11_r01.as_int);
snsv11_r01.TSNS_ISOLATE = 0;
mbus_remote_register_write(SNS_ADDR,1,snsv11_r01.as_int);
delay(MBUS_DELAY*10);
// Disable all timers
//disable_timerwd();
//*REG_MBUS_WD = 0;
mbus_write_message32(0xAA,0xABCD1111);
// Start temp measurement
snsv11_r01.TSNS_RESETn = 1;
mbus_remote_register_write(SNS_ADDR,1,snsv11_r01.as_int);
operation_sleep();
WFI();
mbus_write_message32(0xAA,0xABCD2222);
}
void cycle2 (void) {
if (do_cycle2 == 1) {
arb_debug_reg(0x42, 0x00000000);
//----------------------------------------------------------------------------------------------------------
// Copy from Flash and triggers Soft Reset
if (!get_flag(FLAG_SOFT_RESET)) {
set_flag(FLAG_SOFT_RESET, 1);
*REG_SYS_CONF = 0x60;
arb_debug_reg(0x42, 0x00000001);
mbus_copy_mem_from_local_to_remote_bulk (FLP_ADDR, 0x0, 0x0, 15);
set_halt_until_mbus_trx();
arb_debug_reg(0x42, 0x00000002);
mbus_copy_mem_from_remote_to_any_bulk (FLP_ADDR, 0x0, PRC_ADDR, (uint32_t *) 0x6C840000, 15);
set_halt_until_mbus_tx();
*REG_SYS_CONF = 0x70;
set_halt_until_mbus_trx();
arb_debug_reg(0x42, 0x00000003);
mbus_copy_mem_from_remote_to_any_bulk (FLP_ADDR, 0x0, PRC_ADDR, (uint32_t *) 0x6C840000, 15);
set_halt_until_mbus_tx();
}
//----------------------------------------------------------------------------------------------------------
// End of Testing
else {
*REG_SYS_CONF = 0x60;
if (irq_history == (0x1 << IRQ_SOFT_RESET)) {
pass (0x0, irq_history); irq_history = 0; disable_all_irq(); }
else { fail (0x0, irq_history); disable_all_irq(); }
arb_debug_reg(0x42, 0x00000004);
}
}
}
static void operation_goc_trigger_init(void){
// This is critical
set_halt_until_mbus_tx();
mbus_write_message32(0xAA,0xABCD1234);
mbus_write_message32(0xAA,wakeup_data);
// Initialize variables & registers
sns_running = 0;
Pstack_state = PSTK_IDLE;
}
void cycle11 (void) {
if (do_cycle11 == 1) {
arb_debug_reg (0x3B, 0x00000000);
set_halt_until_mbus_tx();
// Watch-Dog Timer (You should see TIMERWD triggered)
arb_debug_reg (0x3B, 0x00000001);
config_timerwd(100);
// Wait here until PMU resets everything
while(1);
}
}
void cycle9 (void) {
if (do_cycle9 == 1) {
// Set Halt
set_halt_until_mbus_tx();
// Watch-Dog Timer (You should see TIMERWD triggered)
config_timerwd(100);
delay(200);
// Reset Watch-Dog Timer
config_timerwd(0x001E8480); // Default value. Approx. ~20 sec @ 100kHz
}
}
//*******************************************************************
// USER FUNCTIONS
//*******************************************************************
void initialization (void) {
enumerated = 0xDEADBEEF;
cyc_num = 0;
irq_history = 0;
// Set Halt
set_halt_until_mbus_rx();
// Enumeration
//mbus_enumerate(DLC_ADDR);
//Set Halt
set_halt_until_mbus_tx();
}
static void operation_goc_trigger_init(void){
// This is critical
set_halt_until_mbus_tx();
mbus_write_message32(0xAA,0xABCD1234);
mbus_write_message32(0xAA,wakeup_data);
// Initialize variables & registers
temp_running = 0;
Tstack_state = TSTK_IDLE;
radio_power_off();
ldo_power_off();
temp_power_off();
}
//*******************************************************************
// USER FUNCTIONS
//*******************************************************************
void initialization (void) {
set_flag(FLAG_ENUM, 1);
cyc_num = 0;
irq_history = 0;
// Set Halt
set_halt_until_mbus_trx();
// Enumeration
mbus_enumerate(FLP_ADDR);
mbus_enumerate(VIM_ADDR);
mbus_enumerate(PMU_ADDR);
//Set Halt
set_halt_until_mbus_tx();
}
//*******************************************************************
// USER FUNCTIONS
//*******************************************************************
void initialization (void) {
enumerated = 0xDEADBEEF;
cyc_num = 0;
irq_history = 0;
// Set Halt
set_halt_until_mbus_rx();
// Enumeration
mbus_enumerate(FLS_ADDR);
mbus_enumerate(NODE_A_ADDR);
mbus_enumerate(NODE_B_ADDR);
mbus_enumerate(PMU_ADDR);
//Set Halt
set_halt_until_mbus_tx();
}
void cycle11 (void) {
if (do_cycle11 == 1) {
// Set Halt
set_halt_until_mbus_tx();
gpio_init(0xFFFF); // All Output
gpio_write_data(0xF0F0); // 1111 0000 1111 0000
gpio_kill_bit(15); // 0111 0000 1111 0000
gpio_set_bit(1); // 0111 0000 1111 0010
gpio_set_2bits(11, 8); // 0111 1001 1111 0010
gpio_kill_bit(12); // 0110 1001 1111 0010
if (gpio_get_data() == 0xF2) {pass (0xC, gpio_get_data());}
else {fail (0xC, gpio_get_data());}
gpio_close();
}
}
//*******************************************************************
// USER FUNCTIONS
//*******************************************************************
void initialization (void) {
set_flag(FLAG_ENUM, 1);
cyc_num = 0;
// Set Halt
set_halt_until_mbus_trx();
// Enumeration
mbus_enumerate(FLP_ADDR);
mbus_enumerate(NODE_A_ADDR);
mbus_enumerate(SNS_ADDR);
mbus_enumerate(RDC_ADDR);
mbus_enumerate(PMU_ADDR);
//Set Halt
set_halt_until_mbus_tx();
}
void cycle10 (void) {
if (do_cycle10 == 1) {
// Set Halt
set_halt_until_mbus_tx();
// Enable I/O Pads
enable_io_pad();
*SPI_SSPCR0 = 0x0287; // Motorola Mode
*SPI_SSPCR1 = 0x2;
*SPI_SSPCPSR = 0x02; // Clock Prescale Register
//*SPI_SSPDMACR = 0x3;
*SPI_SSPDR = 0x1234;
delay(1000);
// Disable I/O Pads
disable_io_pad();
}
}
int main() {
// Initialize IRQ
disable_all_irq();
if (*REG_CHIP_ID != 0xBEEF) {
set_halt_until_mbus_rx();
mbus_enumerate(FLS_ADDR);
set_halt_until_mbus_tx();
}
mbus_write_message32(0xE0, *REG0);
delay(MBUS_DELAY);
mbus_write_message32(0xE1, *REG1);
delay(MBUS_DELAY);
mbus_write_message32(0xE2, *REG2);
delay(MBUS_DELAY);
mbus_write_message32(0xE3, *REG3);
delay(MBUS_DELAY);
mbus_write_message32(0xE4, *REG4);
delay(MBUS_DELAY);
mbus_write_message32(0xE5, *REG5);
delay(MBUS_DELAY);
mbus_write_message32(0xE6, *REG6);
delay(MBUS_DELAY);
set_halt_until_mbus_rx();
mbus_copy_registers_from_remote_to_local(FLS_ADDR, 0x26, 0x07, 0);
delay(MBUS_DELAY);
mbus_copy_registers_from_remote_to_local(FLS_ADDR, 0x27, 0x07, 0);
delay(MBUS_DELAY);
set_halt_until_mbus_rx();
// Go to indefinite sleep
mbus_sleep_all();
while(1) {
asm("nop;");
}
return 1;
}
void cycle1 (void) {
if (do_cycle1 == 1) {
// Set up RDC IRQ Configuration
RDCv2_REG_BRDC_IRQ_2.BRDC_IRQ_LENGTH_1 = 3;
RDCv2_REG_BRDC_IRQ_2.BRDC_IRQ_PAYLOAD_ADDR = 0x20;
mbus_remote_register_write(RDC_ADDR, 0x11, RDCv2_REG_BRDC_IRQ_2.as_int);
// Un-isolate BRDC
RDCv2_REG_BRDC_ISOL.BRDC_ISOLATE = 0;
RDCv2_REG_BRDC_ISOL.BRDC_V3P6_PG_EN = 0;
RDCv2_REG_BRDC_ISOL.BRDC_V3P6_ISOLB = 1;
RDCv2_REG_BRDC_ISOL.BRDC_V1P2_PG_EN = 0;
RDCv2_REG_BRDC_ISOL.BRDC_OSC_V1P2_PG_EN = 0;
RDCv2_REG_BRDC_ISOL.BRDC_OSC_ISOLATE = 0;
RDCv2_REG_BRDC_ISOL.BRDC_ISOLATE_DOUT = 0;
mbus_remote_register_write(RDC_ADDR, 0x13, RDCv2_REG_BRDC_ISOL.as_int);
// Start BRDC
set_halt_until_mbus_trx();
RDCv2_REG_BRDC_RST.BRDC_RSTB = 1;
RDCv2_REG_BRDC_RST.BRDC_IB_ENB = 0;
RDCv2_REG_BRDC_RST.BRDC_OSC_RESET = 0;
mbus_remote_register_write(RDC_ADDR, 0x12, RDCv2_REG_BRDC_RST.as_int);
set_halt_until_mbus_tx();
// Isolate BRDC
RDCv2_REG_BRDC_ISOL.BRDC_ISOLATE = 1;
RDCv2_REG_BRDC_ISOL.BRDC_V3P6_PG_EN = 1;
RDCv2_REG_BRDC_ISOL.BRDC_V3P6_ISOLB = 0;
RDCv2_REG_BRDC_ISOL.BRDC_V1P2_PG_EN = 1;
RDCv2_REG_BRDC_ISOL.BRDC_OSC_V1P2_PG_EN = 1;
RDCv2_REG_BRDC_ISOL.BRDC_OSC_ISOLATE = 1;
RDCv2_REG_BRDC_ISOL.BRDC_ISOLATE_DOUT = 1;
mbus_remote_register_write(RDC_ADDR, 0x13, RDCv2_REG_BRDC_ISOL.as_int);
}
}
void cycle7 (void) {
if (do_cycle7 == 1) {
// Set Halt
set_halt_until_mbus_tx();
// Enable TIMER16 IRQ
clear_all_pend_irq();
*NVIC_ISER = (0 /*GPIO*/ << 16) | (0 /*SPI*/ << 15) | (0 /*GOCEP*/ << 14) | (0 /*MBUS_FWD*/ << 13)
| (0 /*MBUS_TX*/ << 12) | (0 /*MBUS_RX*/ << 11) | (0 /*MEM_WR*/ << 10) | (0 /*REG7*/ << 9)
| (0 /*REG6*/ << 8) | (0 /*REG5*/ << 7) | (0 /*REG4*/ << 6) | (0 /*REG3*/ << 5)
| (0 /*REG2*/ << 4) | (0 /*REG1*/ << 3) | (0 /*REG0*/ << 2)
| (1 /*TIMER16*/ << 1) | (0 /*TIMER32*/ << 0);
// Timer16
config_timer16(/*cmp0*/ 0x1000, /*cmp1*/0xF000, /*irq_en*/0x3, /*cnt*/0x0, /*status*/0x0); // Start Timer16. Trigger when it reaches 0x1000 or 0xF000.
// Wait for Interrupt
WFI();
// 1 IRQ: TIMER16
if (irq_history == (1 << 1)) {
pass (0x9, irq_history); irq_history = 0;}
else { fail (0x9, irq_history); }
// Wait for Interrupt
WFI();
// 1 IRQ: TIMER16
if (irq_history == (1 << 1)) {
pass (0xA, irq_history); irq_history = 0; disable_all_irq(); }
else { fail (0xA, irq_history); disable_all_irq(); }
// Reset Timer16
*TIMER16_GO = 0x0;
*TIMER16_CNT = 0x0;
}
}
//*******************************************************************
// USER FUNCTIONS
//*******************************************************************
static void initialization(void){
//Enumeration
enumerated = 0xDEADBEEF;
//Chip ID
write_regfile (REG_CHIP_ID, 0xDEAD);
// Notify the start of the program
mbus_write_message32(0xAA, 0xAAAAAAAA);
//Set Halt
set_halt_until_mbus_rx();
//Enumeration
mbus_enumerate(COR_ADDR);
delay(1000);
mbus_enumerate(AFE_ADDR);
//Set Halt
set_halt_until_mbus_tx();
//Enable DSP
afev1_rB.DSP_EN = 1;
afev1_rB.ADC_EN = 1;
mbus_remote_register_write(AFE_ADDR,0x0B,afev1_rB.as_int);
afev1_rB.DSP_EN = 1;
afev1_rB.ADC_EN = 1;
mbus_remote_register_write(AFE_ADDR,0x0B,afev1_rB.as_int);
//DSP Reset
afev1_rA.DSP_RESET_N = 0;
mbus_remote_register_write(AFE_ADDR,0x0A,afev1_rA.as_int);
delay(20000);
//Release DSP Reset
afev1_rA.DSP_RESET_N = 1;
mbus_remote_register_write(AFE_ADDR,0x0A,afev1_rA.as_int);
//Set DSP configuation - external clk on
afev1_rA.DSP_CONFIG = 0x16A15A;
mbus_remote_register_write(AFE_ADDR,0x0A,afev1_rA.as_int);
afev1_rA.DSP_CONFIG = 0x16A15A;
mbus_remote_register_write(AFE_ADDR,0x0A,afev1_rA.as_int);
delay(10000);
//PLL Tuning
afev1_r7.PLL_TRI_7_8_EN = 1;
afev1_r7.PLL_TRI_CK_EN = 0; // Not working,
afev1_r7.PLL_TRI_MODE = 0; //1:Tri state(24MHz), 0:L1 band(2.4MHz)
afev1_r7.PLL_L1_CK_EN = 1; //0:Tri state, 1:L1 band , Not working
afev1_r7.PLL_CK_DIV = 0;
afev1_r7.PLL_REFDIV_EN = 1; //Not working
afev1_r7.PLL_VCO_TRIM = 3; //3b,
afev1_r7.PLL_FBDIV_EN =1;
afev1_r7.PLL_VCO_EN =1;
mbus_remote_register_write(AFE_ADDR,7,afev1_r7.as_int);
delay(10000);
afev1_r8.PLL_MISC =0x07;
afev1_r8.PLL_PFD_EN =1;
afev1_r8.PLL_CP_EN =1;
afev1_r8.PLL_IREF_EN =1;
afev1_r8.PLL_CP_IMISM_TRIM =0x7;
afev1_r8.PLL_VCO_IBIAS_TRIM =0x7;
afev1_r8.PLL_CP_IBIAS_TRIM =0x7;
mbus_remote_register_write(AFE_ADDR,8,afev1_r8.as_int);
delay(10000);
afev1_r9.PLL_PFD_DEL_TRIM =0x00F7;
mbus_remote_register_write(AFE_ADDR,9,afev1_r9.as_int);
delay(10000);
//Rx Tuning
afev1_r5.RX_GA2_b2 = 0xF;
afev1_r5.RX_GA2_b1 = 0xF;
afev1_r5.RX_GA2_b0 = 0x6;
afev1_r5.RX_GA2_EN = 1; // VGA Enalber, Active high
afev1_r5.RX_BETA_b = 0x0; //BETA_b is tuning bits for DAC_ANT
afev1_r5.RX_BETA_EN = 1; //Enabler for BETA multiplier
mbus_remote_register_write(AFE_ADDR,5,afev1_r5.as_int);
delay(10000);
afev1_r6.RX_BGR_b0 =0x4;
afev1_r6.RX_BGR_b1 =0x2;
afev1_r6.RX_BGR_b2 =0x1;
afev1_r6.RX_BGR_b3 =0x0;
mbus_remote_register_write(AFE_ADDR,6,afev1_r6.as_int);
delay(10000);
afev1_r1.RX_LNA_EN = 1;
afev1_r1.RX_LNA_b = 0x3;
afev1_r1.RX_FLTR1_b0 = 0x0;
afev1_r1.RX_FLTR1_b1 = 0x0;
afev1_r1.RX_FLTR1_BYPASS = 0; //EN1 Enable at GMC, Active low
afev1_r1.RX_GA1_EN = 0; //EN0 Enabler at GMC, Active low
afev1_r1.RX_GA1_b = 1; //4b, Tuning bits for VR, VC
afev1_r1.RX_FLTR2_EN = 1; //GMC BQ, Active high
afev1_r1.RX_FLTR2_SEL = 1; //2b, 1: band pass, 2: low pass at GMC filter
mbus_remote_register_write(AFE_ADDR,1,afev1_r1.as_int);
delay(10000);
//Band pass mode
afev1_r2.RX_FLTR2_BQ1_b3 = 0x0;
afev1_r2.RX_FLTR2_BQ1_b2 = 0xE;
afev1_r2.RX_FLTR2_BQ1_b1 = 0x0;
afev1_r2.RX_FLTR2_BQ1_b0 = 0x4;
mbus_remote_register_write(AFE_ADDR,2,afev1_r2.as_int);
delay(10000);
afev1_r3.RX_FLTR2_BQ2_b3 = 0x0;
afev1_r3.RX_FLTR2_BQ2_b2 = 0xF;
afev1_r3.RX_FLTR2_BQ2_b1 = 0x0;
afev1_r3.RX_FLTR2_BQ2_b0 = 0xF;
mbus_remote_register_write(AFE_ADDR,3,afev1_r3.as_int);
delay(10000);
afev1_r4.RX_FLTR2_BQ_b4 = 0x2; //3bit BQ cap tuning
afev1_r4.RX_FLTR2_BQ3_b3 = 0xF;
afev1_r4.RX_FLTR2_BQ3_b2 = 0xF;
afev1_r4.RX_FLTR2_BQ3_b1 = 0x0;
afev1_r4.RX_FLTR2_BQ3_b0 = 0xF;
mbus_remote_register_write(AFE_ADDR,4,afev1_r4.as_int);
delay(10000);
//Low pass mode
/*
afev1_r2.RX_FLTR2_BQ1_b3 = 0x3;
afev1_r2.RX_FLTR2_BQ1_b2 = 0x4;
afev1_r2.RX_FLTR2_BQ1_b1 = 0x0;
afev1_r2.RX_FLTR2_BQ1_b0 = 0xF;
mbus_remote_register_write(AFE_ADDR,2,afev1_r2.as_int);
delay(10000);
afev1_r3.RX_FLTR2_BQ2_b3 = 0x3;
afev1_r3.RX_FLTR2_BQ2_b2 = 0x4;
afev1_r3.RX_FLTR2_BQ2_b1 = 0x0;
afev1_r3.RX_FLTR2_BQ2_b0 = 0xF;
mbus_remote_register_write(AFE_ADDR,3,afev1_r3.as_int);
delay(10000);
afev1_r4.RX_FLTR2_BQ_b4 = 0x1; //3bit BQ cap tuning
afev1_r4.RX_FLTR2_BQ3_b3 = 0x3;
afev1_r4.RX_FLTR2_BQ3_b2 = 0x4;
afev1_r4.RX_FLTR2_BQ3_b1 = 0x1;
afev1_r4.RX_FLTR2_BQ3_b0 = 0xF;
mbus_remote_register_write(AFE_ADDR,4,afev1_r4.as_int);
delay(10000);
*/
//ADC test
afev1_rB.ADC_COMP3_T2_I = 0x7;
afev1_rB.ADC_COMP3_T1_I = 0;
afev1_rB.ADC_COMP2_T2_I = 0x0;
afev1_rB.ADC_COMP2_T1_I = 0x0;
mbus_remote_register_write(AFE_ADDR,0xB,afev1_rB.as_int);
afev1_rC.ADC_COMP1_T2_I = 0;
afev1_rC.ADC_COMP1_T1_I = 0x7;
afev1_rC.ADC_COMP3_T2_Q = 0x1;
afev1_rC.ADC_COMP3_T1_Q = 0;
mbus_remote_register_write(AFE_ADDR,0xC,afev1_rC.as_int);
afev1_rD.ADC_COMP2_T2_Q = 0;
afev1_rD.ADC_COMP2_T1_Q = 0;
afev1_rD.ADC_COMP1_T2_Q = 0;
afev1_rD.ADC_COMP1_T1_Q = 0x1;
mbus_remote_register_write(AFE_ADDR,0xD,afev1_rD.as_int);
//Set DSP configuation - external clk off/Internal clk on
afev1_rA.DSP_CONFIG = 0x16A15A;
mbus_remote_register_write(AFE_ADDR,0xA,afev1_rA.as_int);
afev1_rA.DSP_CONFIG = 0x16A15A;
mbus_remote_register_write(AFE_ADDR,0xA,afev1_rA.as_int);
delay(10000);
}
inline static void mbus_pmu_register_read(uint32_t reg_id){
set_halt_until_mbus_rx();
mbus_remote_register_write(PMU_ADDR,0x00,reg_id);
set_halt_until_mbus_tx();
}
//*******************************************************************
// USER FUNCTIONS
//*******************************************************************
inline static void mbus_pmu_register_write(uint32_t reg_id, uint32_t reg_data){
set_halt_until_mbus_rx();
mbus_remote_register_write(PMU_ADDR,reg_id,reg_data);
set_halt_until_mbus_tx();
}
void cycle0 (void) {
if (do_cycle0 == 1) {
arb_debug_reg(0x70, 0x00000000);
if (!get_flag(FLAG_VCO)) {
set_flag(FLAG_VCO, 1);
// Reset VCO_CNT_ENABLE (unnecessary, but..)
PMUv9_REG_VCO.VCO_CNT_ENABLE = 0x0;
PMUv9_REG_VCO.VCO_CNT_MODE = 0x0;
PMUv9_REG_VCO.VCO_CNT_THRESHOLD = 0x0;
mbus_remote_register_write(PMU_ADDR, 0x53, PMUv9_REG_VCO.as_int);
// Reset TIMER32 (unnecessary, but..)
*TIMER32_GO = 0;
*TIMER32_CMP = 0;
*TIMER32_ROI = 0;
*TIMER32_CNT = 0;
*TIMER32_STAT = 0;
*TIMER32_GO = 0x1;
// Start Active Measurement
arb_debug_reg(0x70, 0x10000000);
set_halt_until_mbus_trx();
PMUv9_REG_VCO.VCO_CNT_ENABLE = 0x1;
PMUv9_REG_VCO.VCO_CNT_MODE = 0x1;
PMUv9_REG_VCO.VCO_CNT_THRESHOLD = 1000;
mbus_remote_register_write(PMU_ADDR, 0x53, PMUv9_REG_VCO.as_int);
// Get TIMER32 measurement
temp_val = *TIMER32_CNT;
*TIMER32_GO = 0;
set_halt_until_mbus_tx();
arb_debug_reg(0x70, (0x20 << 24) | temp_val);
// Reset VCO_CNT_ENABLE
PMUv9_REG_VCO.VCO_CNT_ENABLE = 0x0;
PMUv9_REG_VCO.VCO_CNT_MODE = 0x0;
PMUv9_REG_VCO.VCO_CNT_THRESHOLD = 0x0;
mbus_remote_register_write(PMU_ADDR, 0x53, PMUv9_REG_VCO.as_int);
// Start Sleep Measurement
PMUv9_REG_VCO.VCO_CNT_ENABLE = 0x1;
PMUv9_REG_VCO.VCO_CNT_MODE = 0x0;
PMUv9_REG_VCO.VCO_CNT_THRESHOLD = 0x1000;
mbus_remote_register_write(PMU_ADDR, 0x53, PMUv9_REG_VCO.as_int);
// Go to sleep
arb_debug_reg(0x70, 0x30000000);
set_wakeup_timer(100, 0, 1);
mbus_sleep_all();
}
else {
// Reset VCO_CNT_ENABLE
PMUv9_REG_VCO.VCO_CNT_ENABLE = 0x0;
PMUv9_REG_VCO.VCO_CNT_MODE = 0x0;
PMUv9_REG_VCO.VCO_CNT_THRESHOLD = 0x0;
mbus_remote_register_write(PMU_ADDR, 0x53, PMUv9_REG_VCO.as_int);
arb_debug_reg(0x70, 0x40000000);
}
}
}
//*****************************************************************************
// Temperature, battery voltage, light intensity measurement operation (SNSv7)
//*****************************************************************************
static void operation_run(void){
uint32_t count;
if (Tstack_state == TSTK_IDLE){
#ifdef DEBUG_MBUS_MSG
mbus_write_message32(0xAA, 0x0);
delay(MBUS_DELAY*10);
#endif
Tstack_state = TSTK_TEMP_LDO;
mbus_remote_register_read(HRV_ADDR,0x02,1);
delay(MBUS_DELAY);
read_data_lux = *((volatile uint32_t *) REG1);
delay(MBUS_DELAY);
snail_cnt_reset();
temp_reset_timeout_count = 0;
// Power on radio
if (radio_tx_option || ((exec_count+1) < SENSING_CYCLE_INIT)){
radio_power_on();
}
snsv7_r18.ADC_LDO_ADC_LDO_ENB = 0x0;
mbus_remote_register_write(SNS_ADDR,18,snsv7_r18.as_int);
// Put system to sleep
set_wakeup_timer(WAKEUP_PERIOD_LDO, 0x1, 0x1);
operation_sleep_noirqreset();
}else if (Tstack_state == TSTK_TEMP_LDO){
#ifdef DEBUG_MBUS_MSG
mbus_write_message32(0xAA, 0x1);
delay(MBUS_DELAY*10);
#endif
Tstack_state = TSTK_TEMP_RSTRL;
snsv7_r18.ADC_LDO_ADC_LDO_DLY_ENB = 0x0;
mbus_remote_register_write(SNS_ADDR,18,snsv7_r18.as_int);
// Put system to sleep
set_wakeup_timer(WAKEUP_PERIOD_LDO, 0x1, 0x1);
operation_sleep_noirqreset();
}else if (Tstack_state == TSTK_TEMP_RSTRL){
#ifdef DEBUG_MBUS_MSG
mbus_write_message32(0xAA, 0x2);
delay(MBUS_DELAY*10);
#endif
Tstack_state = TSTK_TEMP_START;
// Release Temp Sensor Reset
temp_sensor_release_reset();
}else if (Tstack_state == TSTK_TEMP_START){
// Start temp measurement
#ifdef DEBUG_MBUS_MSG
mbus_write_message32(0xAA, 0x3);
delay(MBUS_DELAY*10);
#endif
mbus_msg_flag = 0;
temp_sensor_enable();
for(count=0; count<TEMP_TIMEOUT_COUNT; count++){
if( mbus_msg_flag ){
mbus_msg_flag = 0;
temp_reset_timeout_count = 0;
Tstack_state = TSTK_DATA_READ;
return;
}else{
delay(MBUS_DELAY);
}
}
// Time out
mbus_write_message32(0xAA, 0xFAFAFAFA);
temp_sensor_disable();
temp_reset_timeout_count++;
Tstack_state = TSTK_DATA_READ;
}else if (Tstack_state == TSTK_DATA_READ){
#ifdef DEBUG_MBUS_MSG
mbus_write_message32(0xAA, 0x4);
delay(MBUS_DELAY*10);
#endif
//***************************************************
// Grab Data
//***************************************************
uint32_t read_data_temp_done; // [0] Temp Sensor Done
uint32_t read_data_temp_data; // [23:0] Temp Sensor D Out
// PMUv2 register read is handled differently
mbus_remote_register_write(PMU_ADDR,0x00,0x03);
delay(MBUS_DELAY);
read_data_batadc = *((volatile uint32_t *) REG0) & 0xFF;
delay(MBUS_DELAY);
batadc_reset();
delay(MBUS_DELAY);
// Set CPU Halt Option as Rx --> Use for register read e.g.
set_halt_until_mbus_rx();
mbus_remote_register_read(SNS_ADDR,0x10,1);
read_data_temp_done = *((volatile uint32_t *) REG1);
delay(MBUS_DELAY);
if (temp_reset_timeout_count == 0){
mbus_remote_register_read(SNS_ADDR,0x11,1);
read_data_temp_data = *((volatile uint32_t *) REG1);
}else{
read_data_temp_data = 0;
temp_reset_timeout_count = 0;
temp_error_count++;
}
delay(MBUS_DELAY);
// Set CPU Halt Option as TX --> Use for register write e.g.
set_halt_until_mbus_tx();
delay(MBUS_DELAY);
batadc_resetrelease();
//***************************************************
// Finalize Sensing Operation
//***************************************************
temp_sensor_disable();
temp_sensor_assert_reset();
temp_power_off();
Tstack_state = TSTK_IDLE;
#ifdef DEBUG_MBUS_MSG
mbus_write_message32(0xCC, exec_count);
delay(MBUS_DELAY);
mbus_write_message32(0xCC, read_data_temp_done);
delay(MBUS_DELAY);
mbus_write_message32(0xCC, read_data_temp_data);
delay(MBUS_DELAY);
mbus_write_message32(0xCC, read_data_lux);
delay(MBUS_DELAY);
mbus_write_message32(0xCC, read_data_batadc);
delay(MBUS_DELAY);
#endif
#ifdef DEBUG_MBUS_MSG_1
mbus_write_message32(0xCC, exec_count);
delay(MBUS_DELAY);
mbus_write_message32(0xCC, read_data_temp_done);
delay(MBUS_DELAY);
mbus_write_message32(0xCC, read_data_temp_data);
delay(MBUS_DELAY);
mbus_write_message32(0xCC, read_data_lux);
delay(MBUS_DELAY);
mbus_write_message32(0xCC, read_data_batadc);
delay(MBUS_DELAY);
#endif
exec_count++;
// Store results in memory; unless buffer is full
if (data_storage_count < DATA_STORAGE_SIZE){
data_storage[data_storage_count] = (read_data_batadc<<16) | read_data_temp_data ;
#ifdef DEBUG_MBUS_MSG_1
mbus_write_message32(0xDD,data_storage_count);
delay(MBUS_DELAY);
mbus_write_message32(0xDD,data_storage[data_storage_count]);
delay(MBUS_DELAY);
#endif
data_storage_count++;
data_storage[data_storage_count] = read_data_lux;
#ifdef DEBUG_MBUS_MSG_1
mbus_write_message32(0xDD,data_storage_count);
delay(MBUS_DELAY);
mbus_write_message32(0xDD,data_storage[data_storage_count]);
delay(MBUS_DELAY);
#endif
radio_tx_count = data_storage_count;
data_storage_count++;
}
// Optionally transmit the data
if (radio_tx_option){
send_radio_data_ppm(0, read_data_temp_done);
delay(RADIO_PACKET_DELAY);
send_radio_data_ppm(0, read_data_temp_data);
delay(RADIO_PACKET_DELAY);
send_radio_data_ppm(0, read_data_lux);
delay(RADIO_PACKET_DELAY);
send_radio_data_ppm(0, read_data_batadc);
}
// Enter long sleep
if(exec_count < SENSING_CYCLE_INIT){
delay(RADIO_PACKET_DELAY);
send_radio_data_ppm(0, 0xABC000+exec_count);
set_wakeup_timer(WAKEUP_PERIOD_CONT_INIT, 0x1, 0x1);
if(exec_count == (SENSING_CYCLE_INIT-1)){
delay(RADIO_PACKET_DELAY);
send_radio_data_ppm(1, 0xFAF000);
}
}else{
set_wakeup_timer(WAKEUP_PERIOD_CONT, 0x1, 0x1);
}
// Make sure Radio is off
if (radio_on){
radio_ready = 0;
radio_power_off();
}
// Restart HRV counter
snail_cnt_start();
// Discharge battery if vbat is too high
if ((read_data_batadc != 0) && (read_data_batadc < bat_discharge_threshold)){
snsv7_r18.ADC_LDO_ADC_LDO_DLY_ENB = 0;
snsv7_r18.ADC_LDO_ADC_LDO_ENB = 0;
snsv7_r18.CDC_LDO_CDC_LDO_DLY_ENB = 0;
snsv7_r18.CDC_LDO_CDC_LDO_ENB = 0;
#ifdef DEBUG_MBUS_MSG_1
mbus_write_message32(0xBB, read_data_batadc);
delay(MBUS_DELAY);
mbus_write_message32(0xBB, bat_discharge_threshold);
delay(MBUS_DELAY);
#endif
}else{
snsv7_r18.ADC_LDO_ADC_LDO_DLY_ENB = 1;
snsv7_r18.ADC_LDO_ADC_LDO_ENB = 1;
snsv7_r18.CDC_LDO_CDC_LDO_DLY_ENB = 1;
snsv7_r18.CDC_LDO_CDC_LDO_ENB = 1;
}
mbus_remote_register_write(SNS_ADDR,18,snsv7_r18.as_int);
delay(MBUS_DELAY);
if ((set_max_exec_count != 0) && (exec_count > (50<<set_max_exec_count))){
// No more measurement required
// Make sure temp sensor is off
sensor_running = 0;
temp_power_off();
operation_sleep_notimer();
}else{
operation_sleep_noirqreset();
}
}else{
// default: // THIS SHOULD NOT HAPPEN
// Reset Temp Sensor
temp_sensor_assert_reset();
temp_power_off();
operation_sleep_notimer();
}
}
static void operation_sns_run(void){
if (Pstack_state == PSTK_IDLE){
wfi_timeout_flag = 0;
meas_count = 0;
Pstack_state = PSTK_RDC_RUN;
RDC_ADDR = 6;
}else if (Pstack_state == PSTK_RDC_RUN){
// Start RDC measurement
wfi_timeout_flag = 0;
if (meas_count == 0){
// Release RDC power gates / isolation
rdc_release_v1p2_pg();
rdc_release_pg();
delay(MBUS_DELAY);
rdc_release_isolate();
// Need delay for osc to stabilize
rdc_osc_enable();
delay(MBUS_DELAY*2);
}
// Use Timer32 as timeout counter
config_timer32(TIMER32_VAL, 1, 0, 0); // 1/10 of MBUS watchdog timer default
// Start RDC
rdc_enable();
// Wait for output
WFI();
// Turn off Timer32
*TIMER32_GO = 0;
Pstack_state = PSTK_RDC_READ;
}else if (Pstack_state == PSTK_RDC_READ){
// Grab RDC Data
if (wfi_timeout_flag){
read_data_rdc = 0xFAFA;
mbus_write_message32(0xFA, 0xFAFAFAFA);
}else{
// Read register
set_halt_until_mbus_rx();
mbus_remote_register_read(RDC_ADDR,0x20,1);
read_data_rdc = *REG1;
set_halt_until_mbus_tx();
}
rdc_data[meas_count] = read_data_rdc;
meas_count++;
// Option to take multiple measurements per wakeup
if (meas_count < RDC_NUM_MEAS){
// Repeat measurement while awake
rdc_disable();
Pstack_state = PSTK_RDC_RUN;
}else{
meas_count = 0;
// Assert RDC isolation & turn off RDC power
rdc_disable();
rdc_osc_disable();
rdc_assert_pg();
RDC_ADDR = 7;
Pstack_state = PSTK_RDC2_RUN;
mbus_write_message32(0xCC, exec_count);
mbus_write_message32(0xC1, read_data_rdc);
}
}else if (Pstack_state == PSTK_RDC2_RUN){
// Start RDC measurement
wfi_timeout_flag = 0;
if (meas_count == 0){
// Release RDC power gates / isolation
rdc_release_v1p2_pg();
rdc_release_pg();
delay(MBUS_DELAY);
rdc_release_isolate();
// Need delay for osc to stabilize
rdc_osc_enable();
delay(MBUS_DELAY*2);
}
// Use Timer32 as timeout counter
config_timer32(TIMER32_VAL, 1, 0, 0); // 1/10 of MBUS watchdog timer default
// Start RDC
rdc_enable();
// Wait for output
WFI();
// Turn off Timer32
*TIMER32_GO = 0;
Pstack_state = PSTK_RDC2_READ;
}else if (Pstack_state == PSTK_RDC2_READ){
// Grab RDC Data
if (wfi_timeout_flag){
read_data_rdc = 0xFAFA;
mbus_write_message32(0xFA, 0xFAFAFAFA);
}else{
// Read register
set_halt_until_mbus_rx();
mbus_remote_register_read(RDC_ADDR,0x20,1);
read_data_rdc = *REG1;
set_halt_until_mbus_tx();
}
rdc_data[meas_count] = read_data_rdc;
meas_count++;
// Option to take multiple measurements per wakeup
if (meas_count < RDC_NUM_MEAS){
// Repeat measurement while awake
rdc_disable();
Pstack_state = PSTK_RDC2_RUN;
}else{
meas_count = 0;
// Assert RDC isolation & turn off RDC power
rdc_disable();
rdc_osc_disable();
rdc_assert_pg();
RDC_ADDR = 8;
Pstack_state = PSTK_RDC3_RUN;
mbus_write_message32(0xCC, exec_count);
mbus_write_message32(0xC2, read_data_rdc);
}
}else if (Pstack_state == PSTK_RDC3_RUN){
// Start RDC measurement
wfi_timeout_flag = 0;
if (meas_count == 0){
// Release RDC power gates / isolation
rdc_release_v1p2_pg();
rdc_release_pg();
delay(MBUS_DELAY);
rdc_release_isolate();
// Need delay for osc to stabilize
rdc_osc_enable();
delay(MBUS_DELAY*2);
}
// Use Timer32 as timeout counter
config_timer32(TIMER32_VAL, 1, 0, 0); // 1/10 of MBUS watchdog timer default
// Start RDC
rdc_enable();
// Wait for output
WFI();
// Turn off Timer32
*TIMER32_GO = 0;
Pstack_state = PSTK_RDC3_READ;
}else if (Pstack_state == PSTK_RDC3_READ){
// Grab RDC Data
if (wfi_timeout_flag){
read_data_rdc = 0xFAFA;
mbus_write_message32(0xFA, 0xFAFAFAFA);
}else{
// Read register
set_halt_until_mbus_rx();
mbus_remote_register_read(RDC_ADDR,0x20,1);
read_data_rdc = *REG1;
set_halt_until_mbus_tx();
}
rdc_data[meas_count] = read_data_rdc;
meas_count++;
// Option to take multiple measurements per wakeup
if (meas_count < RDC_NUM_MEAS){
// Repeat measurement while awake
rdc_disable();
Pstack_state = PSTK_RDC3_RUN;
}else{
meas_count = 0;
// Assert RDC isolation & turn off RDC power
rdc_disable();
rdc_osc_disable();
rdc_assert_pg();
RDC_ADDR = 9;
Pstack_state = PSTK_RDC4_RUN;
mbus_write_message32(0xCC, exec_count);
mbus_write_message32(0xC3, read_data_rdc);
}
}else if (Pstack_state == PSTK_RDC4_RUN){
// Start RDC measurement
wfi_timeout_flag = 0;
if (meas_count == 0){
// Release RDC power gates / isolation
rdc_release_v1p2_pg();
rdc_release_pg();
delay(MBUS_DELAY);
rdc_release_isolate();
// Need delay for osc to stabilize
rdc_osc_enable();
delay(MBUS_DELAY*2);
}
// Use Timer32 as timeout counter
config_timer32(TIMER32_VAL, 1, 0, 0); // 1/10 of MBUS watchdog timer default
// Start RDC
rdc_enable();
// Wait for output
WFI();
// Turn off Timer32
*TIMER32_GO = 0;
Pstack_state = PSTK_RDC4_READ;
}else if (Pstack_state == PSTK_RDC4_READ){
// Grab RDC Data
if (wfi_timeout_flag){
read_data_rdc = 0xFAFA;
mbus_write_message32(0xFA, 0xFAFAFAFA);
}else{
// Read register
set_halt_until_mbus_rx();
mbus_remote_register_read(RDC_ADDR,0x20,1);
read_data_rdc = *REG1;
set_halt_until_mbus_tx();
}
rdc_data[meas_count] = read_data_rdc;
meas_count++;
// Option to take multiple measurements per wakeup
if (meas_count < RDC_NUM_MEAS){
// Repeat measurement while awake
rdc_disable();
Pstack_state = PSTK_RDC4_RUN;
}else{
meas_count = 0;
// Assert RDC isolation & turn off RDC power
rdc_disable();
rdc_osc_disable();
rdc_assert_pg();
Pstack_state = PSTK_IDLE;
mbus_write_message32(0xC4, read_data_rdc);
exec_count++;
// Enter long sleep
set_wakeup_timer(WAKEUP_PERIOD_CONT, 0x1, 0x1);
operation_sleep();
}
}else{
//default: // THIS SHOULD NOT HAPPEN
// Reset RDC
rdc_assert_pg();
rdc_disable();
rdc_osc_disable();
operation_sleep_notimer();
}
}
