void fimg2d_pm_qos_update(struct fimg2d_control *ctrl, enum fimg2d_qos_status status) { #if defined(CONFIG_ARM_EXYNOS_IKS_CPUFREQ) || \ defined(CONFIG_ARM_EXYNOS_MP_CPUFREQ) || \ defined(CONFIG_FIMG2D_USE_BUS_DEVFREQ) struct fimg2d_platdata *pdata; enum fimg2d_qos_level idx; int ret = 0; #ifdef CONFIG_OF pdata = ctrl->pdata; #else pdata = to_fimg2d_plat(ctrl->dev); #endif #endif if (status == FIMG2D_QOS_ON) { if (ctrl->pre_qos_lv != ctrl->qos_lv) { #ifdef CONFIG_FIMG2D_USE_BUS_DEVFREQ idx = ctrl->qos_lv; if (idx == 0) ret = set_hmp_boost(true); pm_qos_update_request(&ctrl->exynos5_g2d_mif_qos, g2d_qos_table[idx].freq_mif); pm_qos_update_request(&ctrl->exynos5_g2d_int_qos, g2d_qos_table[idx].freq_int); fimg2d_debug("idx:%d, freq_mif:%d, freq_int:%d, ret:%d\n", idx, g2d_qos_table[idx].freq_mif, g2d_qos_table[idx].freq_int, ret); #endif #if defined(CONFIG_ARM_EXYNOS_IKS_CPUFREQ) || \ defined(CONFIG_ARM_EXYNOS_MP_CPUFREQ) pm_qos_update_request(&ctrl->exynos5_g2d_cpu_qos, g2d_qos_table[idx].freq_cpu); pm_qos_update_request(&ctrl->exynos5_g2d_kfc_qos, g2d_qos_table[idx].freq_kfc); fimg2d_debug("idx:%d, freq_cpu:%d, freq_kfc:%d\n", idx, g2d_qos_table[idx].freq_cpu, g2d_qos_table[idx].freq_kfc); } #endif } else if (status == FIMG2D_QOS_OFF) { #ifdef CONFIG_FIMG2D_USE_BUS_DEVFREQ pm_qos_update_request(&ctrl->exynos5_g2d_mif_qos, 0); pm_qos_update_request(&ctrl->exynos5_g2d_int_qos, 0); #endif #if defined(CONFIG_ARM_EXYNOS_IKS_CPUFREQ) || \ defined(CONFIG_ARM_EXYNOS_MP_CPUFREQ) pm_qos_update_request(&ctrl->exynos5_g2d_cpu_qos, 0); pm_qos_update_request(&ctrl->exynos5_g2d_kfc_qos, 0); #endif idx = ctrl->qos_lv; if (idx == 0) ret = set_hmp_boost(false); } }
void fimg2d_pm_qos_update_cpu(struct fimg2d_control *ctrl, enum fimg2d_qos_status status) { enum fimg2d_qos_level idx; unsigned long qflags; g2d_spin_lock(&ctrl->qoslock, qflags); if ((ctrl->qos_lv >= G2D_LV0) && (ctrl->qos_lv < G2D_LV_END)) idx = ctrl->qos_lv; else goto err; g2d_spin_unlock(&ctrl->qoslock, qflags); if (status == FIMG2D_QOS_ON) { if (ctrl->pre_qos_lv != ctrl->qos_lv) { #ifdef CONFIG_SCHED_HMP g2d_spin_lock(&ctrl->qoslock, qflags); if (idx == 0 && !ctrl->boost) { set_hmp_boost(true); ctrl->boost = true; fimg2d_debug("turn on hmp booster\n"); } g2d_spin_unlock(&ctrl->qoslock, qflags); #endif pm_qos_update_request(&ctrl->exynos5_g2d_cluster1_qos, g2d_qos_table[idx].freq_cpu); pm_qos_update_request(&ctrl->exynos5_g2d_cluster0_qos, g2d_qos_table[idx].freq_kfc); fimg2d_debug("idx:%d, freq_cpu:%d, freq_kfc:%d\n", idx, g2d_qos_table[idx].freq_cpu, g2d_qos_table[idx].freq_kfc); } } else if (status == FIMG2D_QOS_OFF) { pm_qos_update_request(&ctrl->exynos5_g2d_cluster1_qos, 0); pm_qos_update_request(&ctrl->exynos5_g2d_cluster0_qos, 0); #ifdef CONFIG_SCHED_HMP g2d_spin_lock(&ctrl->qoslock, qflags); if (ctrl->boost) { set_hmp_boost(false); ctrl->boost = false; fimg2d_debug("turn off hmp booster\n"); } g2d_spin_unlock(&ctrl->qoslock, qflags); #endif } return; err: fimg2d_debug("invalid qos_lv:%d\n", ctrl->qos_lv); }
void fimg2d_pm_qos_update(struct fimg2d_control *ctrl, enum fimg2d_qos_status status) { #if defined(CONFIG_ARM_EXYNOS_IKS_CPUFREQ) || \ defined(CONFIG_ARM_EXYNOS_MP_CPUFREQ) || \ defined(CONFIG_FIMG2D_USE_BUS_DEVFREQ) struct fimg2d_platdata *pdata; enum fimg2d_qos_level idx; int ret = 0; unsigned long qflags; #ifdef CONFIG_OF pdata = ctrl->pdata; #else pdata = to_fimg2d_plat(ctrl->dev); #endif #endif g2d_spin_lock(&ctrl->qoslock, qflags); if ((ctrl->qos_lv >= G2D_LV0) && (ctrl->qos_lv < G2D_LV_END)) idx = ctrl->qos_lv; else goto err; g2d_spin_unlock(&ctrl->qoslock, qflags); if (status == FIMG2D_QOS_ON) { if (ctrl->pre_qos_lv != ctrl->qos_lv) { #ifdef CONFIG_FIMG2D_USE_BUS_DEVFREQ if (idx == 0) ret = set_hmp_boost(true); pm_qos_update_request(&ctrl->exynos5_g2d_mif_qos, g2d_qos_table[idx].freq_mif); pm_qos_update_request(&ctrl->exynos5_g2d_int_qos, g2d_qos_table[idx].freq_int); fimg2d_debug("idx:%d, freq_mif:%d, freq_int:%d, ret:%d\n", idx, g2d_qos_table[idx].freq_mif, g2d_qos_table[idx].freq_int, ret); #endif #if defined(CONFIG_ARM_EXYNOS_IKS_CPUFREQ) || \ defined(CONFIG_ARM_EXYNOS_MP_CPUFREQ) pm_qos_update_request(&ctrl->exynos5_g2d_cpu_qos, g2d_qos_table[idx].freq_cpu); pm_qos_update_request(&ctrl->exynos5_g2d_kfc_qos, g2d_qos_table[idx].freq_kfc); fimg2d_debug("idx:%d, freq_cpu:%d, freq_kfc:%d\n", idx, g2d_qos_table[idx].freq_cpu, g2d_qos_table[idx].freq_kfc); } #endif } else if (status == FIMG2D_QOS_OFF) { #ifdef CONFIG_FIMG2D_USE_BUS_DEVFREQ pm_qos_update_request(&ctrl->exynos5_g2d_mif_qos, 0); pm_qos_update_request(&ctrl->exynos5_g2d_int_qos, 0); #endif #if defined(CONFIG_ARM_EXYNOS_IKS_CPUFREQ) || \ defined(CONFIG_ARM_EXYNOS_MP_CPUFREQ) pm_qos_update_request(&ctrl->exynos5_g2d_cpu_qos, 0); pm_qos_update_request(&ctrl->exynos5_g2d_kfc_qos, 0); #endif if (idx == 0) ret = set_hmp_boost(false); } err: fimg2d_debug("invalid qos_lv:%d\n", ctrl->qos_lv); }