static void
mn103iop_finish (struct hw *me)
{
struct mn103iop *io_port;
int i;
io_port = HW_ZALLOC (me, struct mn103iop);
set_hw_data (me, io_port);
set_hw_io_read_buffer (me, mn103iop_io_read_buffer);
set_hw_io_write_buffer (me, mn103iop_io_write_buffer);
/* Attach ourself to our parent bus */
attach_mn103iop_regs (me, io_port);
/* Initialize the i/o port registers. */
for ( i=0; i<NR_PORTS; ++i )
{
io_port->port[i].output = 0;
io_port->port[i].output_mode = 0;
io_port->port[i].control = 0;
io_port->port[i].pin = 0;
}
io_port->port[2].output_mode = 0xff;
io_port->p2ss = 0;
io_port->p4ss = 0x0f;
}
static void
tx3904sio_finish (struct hw *me)
{
struct tx3904sio *controller;
controller = HW_ZALLOC (me, struct tx3904sio);
set_hw_data (me, controller);
set_hw_io_read_buffer (me, tx3904sio_io_read_buffer);
set_hw_io_write_buffer (me, tx3904sio_io_write_buffer);
set_hw_ports (me, tx3904sio_ports);
set_hw_port_event (me, tx3904sio_port_event);
/* Preset defaults */
controller->backend = sio_stdio;
/* Attach ourself to our parent bus */
attach_tx3904sio_regs (me, controller);
/* Initialize to reset state */
tx3904sio_fifo_reset(me, & controller->rx_fifo);
tx3904sio_fifo_reset(me, & controller->tx_fifo);
controller->slsr = controller->sdicr
= controller->sdisr = controller->sfcr
= controller->sbgr = 0;
controller->slcr = 0x40000000; /* set TWUB */
controller->sbgr = 0x03ff0000; /* set BCLK=3, BRD=FF */
controller->poll_event = NULL;
}
static void
tx3904tmr_finish (struct hw *me)
{
struct tx3904tmr *controller;
controller = HW_ZALLOC (me, struct tx3904tmr);
set_hw_data (me, controller);
set_hw_io_read_buffer (me, tx3904tmr_io_read_buffer);
set_hw_io_write_buffer (me, tx3904tmr_io_write_buffer);
set_hw_ports (me, tx3904tmr_ports);
set_hw_port_event (me, tx3904tmr_port_event);
/* Preset clock dividers */
controller->clock_ticks = 1;
controller->ext_ticks = 100;
/* Attach ourself to our parent bus */
attach_tx3904tmr_regs (me, controller);
/* Initialize to reset state */
controller->tcr =
controller->itmr =
controller->ccdr =
controller->pmgr =
controller->wtmr =
controller->tisr =
controller->trr = 0;
controller->cpra = controller->cprb = 0x00FFFFFF;
controller->ff = 0;
controller->last_ticks = controller->roundoff_ticks = 0;
controller->event = NULL;
}
static void
hw_pal_finish (struct hw *hw)
{
/* create the descriptor */
hw_pal_device *hw_pal = HW_ZALLOC (hw, hw_pal_device);
hw_pal->output.status = 1;
hw_pal->output.buffer = '\0';
hw_pal->input.status = 0;
hw_pal->input.buffer = '\0';
set_hw_data (hw, hw_pal);
set_hw_attach_address (hw, hw_pal_attach_address);
set_hw_io_read_buffer (hw, hw_pal_io_read_buffer);
set_hw_io_write_buffer (hw, hw_pal_io_write_buffer);
set_hw_ports (hw, hw_pal_ports);
/* attach ourselves */
do_hw_attach_regs (hw);
/* If so configured, enable polled input */
if (hw_find_property (hw, "poll?") != NULL
&& hw_find_boolean_property (hw, "poll?"))
{
hw_pal->reader = sim_io_poll_read;
}
else
{
hw_pal->reader = sim_io_read;
}
/* tag the periodic timer */
hw_pal->timer.periodic_p = 1;
}
static void
m68hc11sio_finish (struct hw *me)
{
struct m68hc11sio *controller;
controller = HW_ZALLOC (me, struct m68hc11sio);
set_hw_data (me, controller);
set_hw_io_read_buffer (me, m68hc11sio_io_read_buffer);
set_hw_io_write_buffer (me, m68hc11sio_io_write_buffer);
set_hw_ports (me, m68hc11sio_ports);
set_hw_port_event (me, m68hc11sio_port_event);
#ifdef set_hw_ioctl
set_hw_ioctl (me, m68hc11sio_ioctl);
#else
me->to_ioctl = m68hc11sio_ioctl;
#endif
/* Preset defaults. */
controller->backend = sio_stdio;
/* Attach ourself to our parent bus. */
attach_m68hc11sio_regs (me, controller);
/* Initialize to reset state. */
controller->tx_poll_event = NULL;
controller->rx_poll_event = NULL;
controller->tx_char = 0;
controller->tx_has_char = 0;
controller->rx_clear_scsr = 0;
controller->rx_char = 0;
}
static void
mn103tim_finish (struct hw *me)
{
struct mn103tim *timers;
int i;
timers = HW_ZALLOC (me, struct mn103tim);
set_hw_data (me, timers);
set_hw_io_read_buffer (me, mn103tim_io_read_buffer);
set_hw_io_write_buffer (me, mn103tim_io_write_buffer);
set_hw_ports (me, mn103tim_ports);
/* Attach ourself to our parent bus */
attach_mn103tim_regs (me, timers);
/* Initialize the timers */
for ( i=0; i < NR_REG_TIMERS; ++i )
{
timers->reg[i].mode = 0x00;
timers->reg[i].base = 0;
}
for ( i=0; i < NR_TIMERS; ++i )
{
timers->timer[i].event = NULL;
timers->timer[i].div_ratio = 0;
timers->timer[i].start = 0;
}
timers->tm6md0 = 0x00;
timers->tm6md1 = 0x00;
timers->tm6bc = 0x0000;
timers->tm6ca = 0x0000;
timers->tm6cb = 0x0000;
timers->tm6mda = 0x00;
timers->tm6mdb = 0x00;
}
static void
bfin_gptimer_finish (struct hw *me)
{
struct bfin_gptimer *gptimer;
gptimer = HW_ZALLOC (me, struct bfin_gptimer);
set_hw_data (me, gptimer);
set_hw_io_read_buffer (me, bfin_gptimer_io_read_buffer);
set_hw_io_write_buffer (me, bfin_gptimer_io_write_buffer);
set_hw_ports (me, bfin_gptimer_ports);
attach_bfin_gptimer_regs (me, gptimer);
}
static void
nvram_finish (struct hw *me)
{
struct nvram *controller;
controller = HW_ZALLOC (me, struct nvram);
set_hw_data (me, controller);
set_hw_io_read_buffer (me, nvram_io_read_buffer);
set_hw_io_write_buffer (me, nvram_io_write_buffer);
/* Attach ourself to our parent bus. */
attach_nvram_regs (me, controller);
}
static void
bfin_gpio_finish (struct hw *me)
{
struct bfin_gpio *port;
port = HW_ZALLOC (me, struct bfin_gpio);
set_hw_data (me, port);
set_hw_io_read_buffer (me, bfin_gpio_io_read_buffer);
set_hw_io_write_buffer (me, bfin_gpio_io_write_buffer);
set_hw_ports (me, bfin_gpio_ports);
set_hw_port_event (me, bfin_gpio_port_event);
attach_bfin_gpio_regs (me, port);
}
static void
bfin_ctimer_finish (struct hw *me)
{
struct bfin_ctimer *ctimer;
ctimer = HW_ZALLOC (me, struct bfin_ctimer);
set_hw_data (me, ctimer);
set_hw_io_read_buffer (me, bfin_ctimer_io_read_buffer);
set_hw_io_write_buffer (me, bfin_ctimer_io_write_buffer);
set_hw_ports (me, bfin_ctimer_ports);
attach_bfin_ctimer_regs (me, ctimer);
/* Initialize the Core Timer. */
}
static void
bfin_jtag_finish (struct hw *me)
{
struct bfin_jtag *jtag;
jtag = HW_ZALLOC (me, struct bfin_jtag);
set_hw_data (me, jtag);
set_hw_io_read_buffer (me, bfin_jtag_io_read_buffer);
set_hw_io_write_buffer (me, bfin_jtag_io_write_buffer);
attach_bfin_jtag_regs (me, jtag);
/* Initialize the JTAG state. */
jtag->dspid = bfin_model_get_dspid (hw_system (me));
}
static void
bfin_rtc_finish (struct hw *me)
{
struct bfin_rtc *rtc;
rtc = HW_ZALLOC (me, struct bfin_rtc);
set_hw_data (me, rtc);
set_hw_io_read_buffer (me, bfin_rtc_io_read_buffer);
set_hw_io_write_buffer (me, bfin_rtc_io_write_buffer);
set_hw_ports (me, bfin_rtc_ports);
attach_bfin_rtc_regs (me, rtc);
/* Initialize the RTC. */
}
static void
bfin_wdog_finish (struct hw *me)
{
struct bfin_wdog *wdog;
wdog = HW_ZALLOC (me, struct bfin_wdog);
set_hw_data (me, wdog);
set_hw_io_read_buffer (me, bfin_wdog_io_read_buffer);
set_hw_io_write_buffer (me, bfin_wdog_io_write_buffer);
set_hw_ports (me, bfin_wdog_ports);
set_hw_port_event (me, bfin_wdog_port_event);
attach_bfin_wdog_regs (me, wdog);
/* Initialize the Watchdog. */
wdog->ctl = WDDIS;
}
static void
bfin_cec_finish (struct hw *me)
{
struct bfin_cec *cec;
cec = HW_ZALLOC (me, struct bfin_cec);
set_hw_data (me, cec);
set_hw_io_read_buffer (me, bfin_cec_io_read_buffer);
set_hw_io_write_buffer (me, bfin_cec_io_write_buffer);
set_hw_ports (me, bfin_cec_ports);
set_hw_port_event (me, bfin_cec_port_event);
attach_bfin_cec_regs (me, cec);
/* Initialize the CEC. */
cec->imask = IVG_UNMASKABLE_B;
cec->ipend = IVG_RST_B | IVG_IRPTEN_B;
}
static void
m68hc11eepr_finish (struct hw *me)
{
struct m68hc11eepr *controller;
controller = HW_ZALLOC (me, struct m68hc11eepr);
set_hw_data (me, controller);
set_hw_io_read_buffer (me, m68hc11eepr_io_read_buffer);
set_hw_io_write_buffer (me, m68hc11eepr_io_write_buffer);
set_hw_ports (me, m68hc11eepr_ports);
set_hw_port_event (me, m68hc11eepr_port_event);
#ifdef set_hw_ioctl
set_hw_ioctl (me, m68hc11eepr_ioctl);
#else
me->to_ioctl = m68hc11eepr_ioctl;
#endif
attach_m68hc11eepr_regs (me, controller);
}
static void
mn103cpu_finish (struct hw *me)
{
struct mn103cpu *controller;
controller = HW_ZALLOC (me, struct mn103cpu);
set_hw_data (me, controller);
set_hw_io_read_buffer (me, mn103cpu_io_read_buffer);
set_hw_io_write_buffer (me, mn103cpu_io_write_buffer);
set_hw_ports (me, mn103cpu_ports);
set_hw_port_event (me, mn103cpu_port_event);
/* Attach ourself to our parent bus */
attach_mn103cpu_regs (me, controller);
/* Initialize the read-only registers */
controller->pending_level = 7; /* FIXME */
/* ... */
}
static void
bfin_uart_finish (struct hw *me)
{
struct bfin_uart *uart;
uart = HW_ZALLOC (me, struct bfin_uart);
set_hw_data (me, uart);
set_hw_io_read_buffer (me, bfin_uart_io_read_buffer);
set_hw_io_write_buffer (me, bfin_uart_io_write_buffer);
set_hw_dma_read_buffer (me, bfin_uart_dma_read_buffer);
set_hw_dma_write_buffer (me, bfin_uart_dma_write_buffer);
set_hw_ports (me, bfin_uart_ports);
attach_bfin_uart_regs (me, uart);
/* Initialize the UART. */
uart->dll = 0x0001;
uart->lsr = 0x0060;
}
static void
bfin_spi_finish (struct hw *me)
{
struct bfin_spi *spi;
spi = HW_ZALLOC (me, struct bfin_spi);
set_hw_data (me, spi);
set_hw_io_read_buffer (me, bfin_spi_io_read_buffer);
set_hw_io_write_buffer (me, bfin_spi_io_write_buffer);
set_hw_dma_read_buffer (me, bfin_spi_dma_read_buffer);
set_hw_dma_write_buffer (me, bfin_spi_dma_write_buffer);
set_hw_ports (me, bfin_spi_ports);
attach_bfin_spi_regs (me, spi);
/* Initialize the SPI. */
spi->ctl = 0x0400;
spi->flg = 0xFF00;
spi->stat = 0x0001;
}
static void
bfin_ebiu_ddrc_finish (struct hw *me)
{
struct bfin_ebiu_ddrc *ddrc;
ddrc = HW_ZALLOC (me, struct bfin_ebiu_ddrc);
set_hw_data (me, ddrc);
set_hw_io_read_buffer (me, bfin_ebiu_ddrc_io_read_buffer);
set_hw_io_write_buffer (me, bfin_ebiu_ddrc_io_write_buffer);
attach_bfin_ebiu_ddrc_regs (me, ddrc);
/* Initialize the DDRC. */
ddrc->ddrctl0 = 0x098E8411;
ddrc->ddrctl1 = 0x10026223;
ddrc->ddrctl2 = 0x00000021;
ddrc->ddrctl3 = 0x00000003; /* XXX: MDDR is 0x20 ... */
ddrc->ddrque = 0x00001115;
ddrc->rstctl = 0x0002;
}
static void
tx3904irc_finish (struct hw *me)
{
struct tx3904irc *controller;
controller = HW_ZALLOC (me, struct tx3904irc);
set_hw_data (me, controller);
set_hw_io_read_buffer (me, tx3904irc_io_read_buffer);
set_hw_io_write_buffer (me, tx3904irc_io_write_buffer);
set_hw_ports (me, tx3904irc_ports);
set_hw_port_event (me, tx3904irc_port_event);
/* Attach ourself to our parent bus */
attach_tx3904irc_regs (me, controller);
/* Initialize to reset state */
controller->isr = 0x0000ffff;
controller->imr = 0;
controller->ilr[0] =
controller->ilr[1] =
controller->ilr[2] =
controller->ilr[3] = 0;
}
static void
mn103ser_finish (struct hw *me)
{
struct mn103ser *serial;
int i;
serial = HW_ZALLOC (me, struct mn103ser);
set_hw_data (me, serial);
set_hw_io_read_buffer (me, mn103ser_io_read_buffer);
set_hw_io_write_buffer (me, mn103ser_io_write_buffer);
set_hw_ports (me, mn103ser_ports);
/* Attach ourself to our parent bus */
attach_mn103ser_regs (me, serial);
/* If so configured, enable polled input */
if (hw_find_property (me, "poll?") != NULL
&& hw_find_boolean_property (me, "poll?"))
{
serial->reader = sim_io_poll_read;
}
else
{
serial->reader = sim_io_read;
}
/* Initialize the serial device registers. */
for ( i=0; i<NR_SERIAL_DEVS; ++i )
{
serial->device[i].txb = 0;
serial->device[i].rxb = 0;
serial->device[i].status = 0;
serial->device[i].control = 0;
serial->device[i].intmode = 0;
serial->device[i].event = NULL;
}
}
static void
mn103int_finish (struct hw *me)
{
int gid;
struct mn103int *controller;
controller = HW_ZALLOC (me, struct mn103int);
set_hw_data (me, controller);
set_hw_io_read_buffer (me, mn103int_io_read_buffer);
set_hw_io_write_buffer (me, mn103int_io_write_buffer);
set_hw_ports (me, mn103int_ports);
set_hw_port_event (me, mn103int_port_event);
me->to_ioctl = mn103int_ioctl;
/* Attach ourself to our parent bus */
attach_mn103int_regs (me, controller);
/* Initialize all the groups according to their default configuration */
for (gid = 0; gid < NR_GROUPS; gid++)
{
struct mn103int_group *group = &controller->group[gid];
group->trigger = NEGATIVE_EDGE;
group->gid = gid;
if (FIRST_NMI_GROUP <= gid && gid <= LAST_NMI_GROUP)
{
group->enable = 0xf;
group->type = NMI_GROUP;
}
else if (FIRST_LEVEL_GROUP <= gid && gid <= LAST_LEVEL_GROUP)
{
group->enable = 0x0;
group->type = LEVEL_GROUP;
}
else
hw_abort (me, "internal error - unknown group id");
}
}
static void
m68hc11spi_finish (struct hw *me)
{
struct m68hc11spi *controller;
controller = HW_ZALLOC (me, struct m68hc11spi);
set_hw_data (me, controller);
set_hw_io_read_buffer (me, m68hc11spi_io_read_buffer);
set_hw_io_write_buffer (me, m68hc11spi_io_write_buffer);
set_hw_ports (me, m68hc11spi_ports);
set_hw_port_event (me, m68hc11spi_port_event);
#ifdef set_hw_ioctl
set_hw_ioctl (me, m68hc11spi_ioctl);
#else
me->to_ioctl = m68hc11spi_ioctl;
#endif
/* Attach ourself to our parent bus. */
attach_m68hc11spi_regs (me, controller);
/* Initialize to reset state. */
controller->spi_event = NULL;
controller->rx_clear_scsr = 0;
}
static void
bfin_ppi_finish (struct hw *me)
{
struct bfin_ppi *ppi;
const char *color;
ppi = HW_ZALLOC (me, struct bfin_ppi);
set_hw_data (me, ppi);
set_hw_io_read_buffer (me, bfin_ppi_io_read_buffer);
set_hw_io_write_buffer (me, bfin_ppi_io_write_buffer);
set_hw_dma_read_buffer (me, bfin_ppi_dma_read_buffer);
set_hw_dma_write_buffer (me, bfin_ppi_dma_write_buffer);
set_hw_ports (me, bfin_ppi_ports);
attach_bfin_ppi_regs (me, ppi);
/* Initialize the PPI. */
if (hw_find_property (me, "color"))
color = hw_find_string_property (me, "color");
else
color = NULL;
ppi->color = bfin_gui_color (color);
}
static void
m68hc11tim_finish (struct hw *me)
{
struct m68hc11tim *controller;
controller = HW_ZALLOC (me, struct m68hc11tim);
set_hw_data (me, controller);
set_hw_io_read_buffer (me, m68hc11tim_io_read_buffer);
set_hw_io_write_buffer (me, m68hc11tim_io_write_buffer);
set_hw_ports (me, m68hc11tim_ports);
set_hw_port_event (me, m68hc11tim_port_event);
#ifdef set_hw_ioctl
set_hw_ioctl (me, m68hc11tim_ioctl);
#else
me->to_ioctl = m68hc11tim_ioctl;
#endif
/* Preset defaults. */
controller->clock_prescaler = 1;
controller->tcnt_adjust = 0;
/* Attach ourself to our parent bus. */
attach_m68hc11tim_regs (me, controller);
}
static void
bfin_ebiu_sdc_finish (struct hw *me)
{
struct bfin_ebiu_sdc *sdc;
sdc = HW_ZALLOC (me, struct bfin_ebiu_sdc);
set_hw_data (me, sdc);
set_hw_io_read_buffer (me, bfin_ebiu_sdc_io_read_buffer);
set_hw_io_write_buffer (me, bfin_ebiu_sdc_io_write_buffer);
attach_bfin_ebiu_sdc_regs (me, sdc);
sdc->type = hw_find_integer_property (me, "type");
/* Initialize the SDC. */
sdc->sdgctl = 0xE0088849;
sdc->sdbctl = 0x00000000;
sdc->sdrrc = 0x081A;
sdc->sdstat = 0x0008;
/* XXX: We boot with 64M external memory by default ... */
sdc->sdbctl |= EBE | EBSZ_64 | EBCAW_10;
}
struct hw *
hw_create (struct sim_state *sd,
struct hw *parent,
const char *family,
const char *name,
const char *unit,
const char *args)
{
/* NOTE: HW must be allocated using ZALLOC, others use HW_ZALLOC */
struct hw *hw = ZALLOC (struct hw);
/* our identity */
hw->family_of_hw = hw_strdup (hw, family);
hw->name_of_hw = hw_strdup (hw, name);
hw->args_of_hw = hw_strdup (hw, args);
/* a hook into the system */
if (sd != NULL)
hw->system_of_hw = sd;
else if (parent != NULL)
hw->system_of_hw = hw_system (parent);
else
hw_abort (parent, "No system found");
/* in a tree */
if (parent != NULL)
{
struct hw **sibling = &parent->child_of_hw;
while ((*sibling) != NULL)
sibling = &(*sibling)->sibling_of_hw;
*sibling = hw;
hw->parent_of_hw = parent;
}
/* top of tree */
if (parent != NULL)
{
struct hw *root = parent;
while (root->parent_of_hw != NULL)
root = root->parent_of_hw;
hw->root_of_hw = root;
}
/* a unique identifier for the device on the parents bus */
if (parent != NULL)
{
hw_unit_decode (parent, unit, &hw->unit_address_of_hw);
}
/* Determine our path */
if (parent != NULL)
hw->path_of_hw = full_name_of_hw (hw, NULL, 0);
else
hw->path_of_hw = "/";
/* create our base type */
hw->base_of_hw = HW_ZALLOC (hw, struct hw_base_data);
hw->base_of_hw->finished_p = 0;
/* our callbacks */
set_hw_io_read_buffer (hw, panic_hw_io_read_buffer);
set_hw_io_write_buffer (hw, panic_hw_io_write_buffer);
set_hw_dma_read_buffer (hw, passthrough_hw_dma_read_buffer);
set_hw_dma_write_buffer (hw, passthrough_hw_dma_write_buffer);
set_hw_unit_decode (hw, generic_hw_unit_decode);
set_hw_unit_encode (hw, generic_hw_unit_encode);
set_hw_unit_address_to_attach_address (hw, generic_hw_unit_address_to_attach_address);
set_hw_unit_size_to_attach_size (hw, generic_hw_unit_size_to_attach_size);
set_hw_attach_address (hw, passthrough_hw_attach_address);
set_hw_detach_address (hw, passthrough_hw_detach_address);
set_hw_delete (hw, ignore_hw_delete);
/* locate a descriptor */
{
const struct hw_descriptor **table;
for (table = hw_descriptors;
*table != NULL;
table++)
{
const struct hw_descriptor *entry;
for (entry = *table;
entry->family != NULL;
entry++)
{
if (strcmp (family, entry->family) == 0)
{
hw->base_of_hw->descriptor = entry;
break;
}
}
}
if (hw->base_of_hw->descriptor == NULL)
{
hw_abort (parent, "Unknown device `%s'", family);
}
}
/* Attach dummy ports */
create_hw_alloc_data (hw);
create_hw_property_data (hw);
create_hw_port_data (hw);
create_hw_event_data (hw);
create_hw_handle_data (hw);
create_hw_instance_data (hw);
return hw;
}
