void init_idt()
{
u16int i = 0;
// Remap the irq table.
outb(0x20, 0x11);
outb(0xA0, 0x11);
outb(0x21, 0x20);
outb(0xA1, 0x28);
outb(0x21, 0x04);
outb(0xA1, 0x02);
outb(0x21, 0x01);
outb(0xA1, 0x01);
outb(0x21, 0x0);
outb(0xA1, 0x0);
for( i = 0; i < IDT_NUM; ++i){
if(i < 0x10){
kprintf("%d ==> %x\n",i, fun_isr[i]);
set_idt(&(idt[i]),(u32int)(fun_isr[i]), 0x8, 0x8e);
} else {
set_idt(&(idt[i]),(u32int)isr_default,0x8, 0x8e);
}
}
for( i = 0; i < 16; ++i){
set_idt(&(idt[i+32]),(u32int)(fun_irq[i]),0x8, 0x8e);
}
idt_ptr.limit = sizeof(idt_entry_t) * IDT_NUM;
idt_ptr.base = (u32int)&idt[0];
__asm__("lidt %0\t\n"::"m"(idt_ptr));
}
/* setup_syscall ------------------------------------------------------------*/
static void
setup_syscall()
{
/* CAUTION !!! priority of system call segment must be 3 ------------*/
set_idt(VECT_SYSCALL, (unsigned long)intr_syscall,
SEL_K32_C, 0, GT_INTR | 0x60);
set_idt(VECT_APIC, (unsigned long)intr_apic, SEL_K32_C, 0, GT_TRAP);
/* smp timer interrupt ----------------------------------------------*/
set_idt(VECT_SMP_TIMER0,
(unsigned long)intr_smp_timer0, SEL_K32_C, 0, GT_INTR);
set_idt(VECT_SMP_TIMER1,
(unsigned long)intr_smp_timer1, SEL_K32_C, 0, GT_INTR);
}
static void set_idtr(IntrGate idt[], ac_u32 count) {
IdtPtr dp;
dp.limit = (ac_u16)(((ac_uptr)&idt[count] - (ac_uptr)&idt[0] - 1)
& 0xFFFF);
dp.iig = &idt[0];
set_idt(&dp);
}
void set_idtr(void)
{
int i;
for(i = 0; i <= NUM_IDT; i++){
set_idt(&idt[i], (unsigned int)asm_int_ignore, 0x08, 1, 0, 1);
}
// exception
// Div by 0
set_idt(&idt[0x00], (unsigned int)asm_int_div_by_0, 0x08, 1, 0, 1);
set_idt(&idt[0x20], (unsigned int)asm_int_timer0, 0x08, 1, 0, 1);
set_idt(&idt[0x21], (unsigned int)asm_int_keyboard, 0x08, 1, 0, 1);
idtr.size = NUM_IDT * sizeof(GATE_DESCRIPTOR);
idtr.base = (GATE_DESCRIPTOR *)idt;
load_idt();
}
void base_idt_load(void)
{
struct pseudo_descriptor pdesc;
/* Create a pseudo-descriptor describing the GDT. */
pdesc.limit = sizeof(base_idt) - 1;
pdesc.linear_base = kvtolin(&base_idt);
/* Load the IDT. */
set_idt(&pdesc);
}
/* idt_init -----------------------------------------------------------------*/
void
idt_init()
{
short i;
/* set default interrupt handler ------------------------------------*/
for (i = 0 ; i < 256 ; i ++) {
set_idt(i, (unsigned long)intr_default, SEL_K32_C, 0, GT_TRAP);
}
/* please wirte other file. */
#if 1
setup_trap();
setup_irq();
setup_syscall();
#endif
}
}
void sched_init(void)
{
/* 初始化进程控制块指针数组 */
/* nothing.在bss段,已被清零 */
proc[0] = &init_proc.proc;
current = proc[0];
ticks = 0;
/* 设置进程0的ldt和tss描述符 */
set_ldt_desc(0, V_KERNEL_ZONE_START+(unsigned long)&(proc[0]->ldt));
set_tss_desc(0, V_KERNEL_ZONE_START+(unsigned long)&(proc[0]->tss));
/* 装载进程0的ldt和tss选择符，第一次需我们来加载 */
lldt(_LDT(0));
ltr(_TSS(0));
/* 挂载时钟中断处理程序 */
set_idt(INT_R0, timer_int, NR_TIMER_INT);
/* 设置8253定时器芯片 */
out_b(0x43, 0x36);
out_b(0x40, (LATCH & 0xff));
out_b(0x40, ((LATCH>>8) & 0xff));
/* 挂载系统调用处理程序 */
void idt_init() {
idt.size = sizeof(descriptor) - 1;
idt.base = (uint64_t) &descriptor;
for (int i = 0; i < INTERRUPT_COUNT; i++)
descriptor_set(i, (uint64_t) &handler_empty,
INTERRUPT_FLAG_PRESENT | INTERRUPT_FLAG_INT64);
uint8_t errors[] = {8, 10, 11, 12, 13, 14, 17, 30};
for (int i = 0; i < 8; i++)
descriptor_set(errors[i], (uint64_t) &handler_pop,
INTERRUPT_FLAG_PRESENT | INTERRUPT_FLAG_INT64);
set_idt(&idt);
}
void setup_ints(void)
{
for (int i = 0; i != IDT_IRQS; ++i)
irqmask_count[i] = 1;
for (int i = 0; i != IDT_EXCEPTIONS; ++i)
setup_irq(isr_entry[i], i);
idt_ptr.size = sizeof(idt) - 1;
idt_ptr.base = (uintptr_t)idt;
set_idt(&idt_ptr);
extern struct irqchip i8259a;
irqchip = &i8259a;
irqchip_map(irqchip, IDT_EXCEPTIONS);
}
/****************************************************************************
* init_keyboard ---
*
*/
ER
init_keyboard ()
{
INT i;
T_CTSK par_task;
T_CMBF par_msg;
for (i = 0; i < MAX_KEYENTRY - 1; i++)
{
keyentry[i].next = &keyentry[i + 1];
}
keyentry[MAX_KEYENTRY - 1].next = NULL;
freeentry = keyentry;
/* KBD の初期化 --- 8251A の初期化 */
set_idt (INT_KEYBOARD, 0x08, (int)int33_handler, INTERRUPT_DESC, 0);
reset_intr_mask (1);
outb (KEY_COM, 0);
outb (KEY_COM, 0);
outb (KEY_COM, 0);
outb (KEY_COM, 0x40);
outb (KEY_COM, 0x5e);
outb (KEY_COM, 0x3a);
/* busywait (20); */
outb (KEY_COM, 0x32);
/* busywait (20); */
outb (KEY_COM, 0x16);
/* string_shift_to_tron (device_table[id].name); */
shiftkey_code = NORMAL;
par_msg.mbfatr = TA_TFIFO;
par_msg.bufsz = (INT)(sizeof (struct key_entry) * 100);
par_msg.maxmsz = (INT)sizeof (struct key_entry);
cre_mbf (ITRON_KEYBOARD_MBF, &par_msg);
par_task.exinf = 0;
par_task.startaddr = keyboard_task;
par_task.itskpri = 1;
par_task.stksz = PAGE_SIZE;
par_task.addrmap = NULL;
cre_tsk (ITRON_KEYBOARD, &par_task);
sta_tsk (ITRON_KEYBOARD, NULL);
return (E_OK);
}
void pc_reset()
{
int i;
/* Inform BIOS that this is a warm boot. */
*(unsigned short *)phystokv(0x472) = 0x1234;
/* Try to reset using the keyboard controller. */
for (i = 0; i < 100; i++)
{
kb_command(KC_CMD_PULSE & ~KO_SYSRESET);
}
/* If that fails, try the ultimate kludge:
clearing the IDT and causing a "triple fault"
so that the processor is forced to reset itself. */
set_idt(&null_pdesc);
asm("int $3");
}
void reset_x86(void) {
// From [The easiest way to reset i386/x86_64 system]
// (http://www.pagetable.com/?p=140). The original code
// caused an GP fault (exception 13), but this code
// works.
IdtPtr null_idtr;
null_idtr.limit = 0;
null_idtr.iig = 0;
cli();
set_idt(&null_idtr);
intr(3);
// Loop with interrupts off if it doesn't work
while (1) {
hlt();
}
}
void isr_install()
{
set_idt_gate(0 , (uint32)isr0 );
set_idt_gate(1 , (uint32)isr1 );
set_idt_gate(2 , (uint32)isr2 );
set_idt_gate(3 , (uint32)isr3 );
set_idt_gate(4 , (uint32)isr4 );
set_idt_gate(5 , (uint32)isr5 );
set_idt_gate(6 , (uint32)isr6 );
set_idt_gate(7 , (uint32)isr7 );
set_idt_gate(8 , (uint32)isr8 );
set_idt_gate(9 , (uint32)isr9 );
set_idt_gate(10 , (uint32)isr10 );
set_idt_gate(11 , (uint32)isr11 );
set_idt_gate(12 , (uint32)isr12 );
set_idt_gate(13 , (uint32)isr13 );
set_idt_gate(14 , (uint32)isr14 );
set_idt_gate(15 , (uint32)isr15 );
set_idt_gate(16 , (uint32)isr16 );
set_idt_gate(17 , (uint32)isr17 );
set_idt_gate(18 , (uint32)isr18 );
set_idt_gate(19 , (uint32)isr19 );
set_idt_gate(20 , (uint32)isr20 );
set_idt_gate(21 , (uint32)isr21 );
set_idt_gate(22 , (uint32)isr22 );
set_idt_gate(23 , (uint32)isr23 );
set_idt_gate(24 , (uint32)isr24 );
set_idt_gate(25 , (uint32)isr25 );
set_idt_gate(26 , (uint32)isr26 );
set_idt_gate(27 , (uint32)isr27 );
set_idt_gate(28 , (uint32)isr28 );
set_idt_gate(29 , (uint32)isr29 );
set_idt_gate(30 , (uint32)isr30 );
set_idt_gate(31 , (uint32)isr31 );
set_idt();
}
void setup_interrupt()
{
init_pic();
setup_interrupt_handler(idt, DEBUG);
setup_interrupt_handler(idt, NMI);
setup_interrupt_handler(idt, BREAKPOINT);
setup_interrupt_handler(idt, OVERFLOW);
setup_interrupt_handler(idt, BOUND_RANGE_EXCEDD);
setup_interrupt_handler(idt, INVALID_OP);
setup_interrupt_handler(idt, DEVICE_NOT_AVAL);
setup_interrupt_handler(idt, DOUBL_FAULT);
setup_interrupt_handler(idt, COP_SEGMENT);
setup_interrupt_handler(idt, IVALID_TSS);//这里修改了
setup_interrupt_handler(idt, SEGMENT_NOT_PRESETNT);
setup_interrupt_handler(idt, STACK_FAULT);
setup_interrupt_handler(idt, GENERAL_FAULT);
setup_interrupt_handler(idt, PAGE_FAULT);
setup_interrupt_handler(idt, TIMER);
/* set_up int used for usespace application */
set_idt(idt, INT_USER, HW_VC(48), DA_386TGate, 3);
load_idt();
local_irq_enable();
}
void isr_init(){
set_idt(glb_idt + 0, SEG_1, isr0, 0);
set_idt(glb_idt + 1, SEG_1, isr1, 0);
set_idt(glb_idt + 2, SEG_1, isr2, 0);
set_idt(glb_idt + 3, SEG_1, isr3, 0);
set_idt(glb_idt + 4, SEG_1, isr4, 0);
set_idt(glb_idt + 5, SEG_1, isr5, 0);
set_idt(glb_idt + 6, SEG_1, isr6, 0);
set_idt(glb_idt + 7, SEG_1, isr7, 0);
set_idt(glb_idt + 8, SEG_1, isr8, 0);
set_idt(glb_idt + 9, SEG_1, isr9, 0);
set_idt(glb_idt + 10, SEG_1, isr10, 0);
set_idt(glb_idt + 11, SEG_1, isr11, 0);
set_idt(glb_idt + 12, SEG_1, isr12, 0);
set_idt(glb_idt + 13, SEG_1, isr13, 0);
set_idt(glb_idt + 14, SEG_1, isr14, 0);
set_idt(glb_idt + 15, SEG_1, isr15, 0);
set_idt(glb_idt + 16, SEG_1, isr16, 0);
set_idt(glb_idt + 17, SEG_1, isr17, 0);
set_idt(glb_idt + 18, SEG_1, isr18, 0);
set_idt(glb_idt + 19, SEG_1, isr19, 0);
set_idt(glb_idt + 20, SEG_1, isr20, 0);
set_idt(glb_idt + 21, SEG_1, isr21, 0);
set_idt(glb_idt + 22, SEG_1, isr22, 0);
set_idt(glb_idt + 23, SEG_1, isr23, 0);
set_idt(glb_idt + 24, SEG_1, isr24, 0);
set_idt(glb_idt + 25, SEG_1, isr25, 0);
set_idt(glb_idt + 26, SEG_1, isr26, 0);
set_idt(glb_idt + 27, SEG_1, isr27, 0);
set_idt(glb_idt + 28, SEG_1, isr28, 0);
set_idt(glb_idt + 29, SEG_1, isr29, 0);
set_idt(glb_idt + 30, SEG_1, isr30, 0);
set_idt(glb_idt + 31, SEG_1, isr31, 0);
}
}
void debug_init(void)
{
int IndexFieldBuilder::addTerm()
{
index_builder_t * pbuilder = _pIndexBuilder;
if ((NULL == pbuilder)) {
TERR("parameter error: pbuilder %p", pbuilder);
return -1;
}
int32_t ret = 0;
unsigned int base_num = 0;
unsigned int doc_count = 0;
IDX_DISK_TYPE disk_type = TS_IDT_NOT_ZIP;
idict_node_t node = {0L, 0, 0, 0, 0};
full_idx1_unit_t * pind1 = (full_idx1_unit_t*)(&node);
pind1->term_sign = _pLineParse->getSign();
// convert text inverted index to binary inverted index(not-zipped format)
uint32_t useLen = 0;
ret = buildNZipIndex(&base_num, pbuilder->raw_buf, pbuilder->raw_buf_size, useLen);
if (unlikely(ret<=0)) {
TERR("build uncompressed index failed. ret %d, line sign=%lu", ret, pind1->term_sign);
return -1;
}
doc_count = ret;
// determine which format will be store into index2 file
disk_type = set_idt(doc_count, base_num, pbuilder->bitmap_size);
// build and write zip/bitmap index2 according to disk_type
switch(disk_type) {
case TS_IDT_NOT_ZIP:
{
ret = abandonOverflow(pbuilder->raw_buf, doc_count, base_num, useLen);
if(ret < 0) {
TERR("abandon overflow(unzip) error, sign=%lu", node.sign);
return -1;
} else if(ret > 0) {
TERR("idx2 docnum over bit level(unzip), lastNum=%u, line sign=%lu",
doc_count, pind1->term_sign);
}
// add index1 node
pind1->file_num = pbuilder->inverted_fd_num - 1;
pind1->pos = pbuilder->cur_size;
pind1->zip_flag = 0;
pind1->doc_count = doc_count;
pind1->len = useLen;
pind1->not_orig_flag = ( false == _rebuildFlag ) ? 0 : 1;
ret = idx_dict_add(pbuilder->inverted_dict, &node);
if (unlikely(ret<0)) {
TERR("add token %lu to idx1 dict failed. ret %d",
node.sign, ret);
return -1;
}
// write index2
ret = write(pbuilder->inverted_fd[pind1->file_num],
pbuilder->raw_buf, pind1->len);
if (unlikely((unsigned)ret != pind1->len)) {
TERR("write NOT_ZIP index of token %lu to file %d failed. ret %d",
pind1->term_sign, pind1->file_num, ret);
return -1;
}
break;
}
case TS_IDT_BITMAP:
case TS_IDT_ZIP_BITMAP:
{
bitmap_idx1_unit_t * pBitMapIdx = (bitmap_idx1_unit_t*)pind1;
// build bitmap index
memset(pbuilder->final_buf, 0, pbuilder->bitmap_size);
buildBitmapIndex(pbuilder->raw_buf, doc_count, pbuilder->final_buf, pBitMapIdx->max_docId);
// add index1 node to bitmap_dict
pBitMapIdx->doc_count = doc_count;
pBitMapIdx->pos = lseek(pbuilder->bitmap_fd, 0, SEEK_CUR);
pBitMapIdx->not_orig_flag = ( false == _rebuildFlag ) ? 0 : 1;
ret = idx_dict_add(pbuilder->bitmap_dict, &node);
if (unlikely(ret<0)) {
TERR("add token %lu to bitmap idx1 dict failed. ret %d",
node.sign, ret);
return -1;
}
// write bitmap index
ret = write(pbuilder->bitmap_fd, pbuilder->final_buf, pbuilder->bitmap_size);
if (unlikely((unsigned)ret != pbuilder->bitmap_size)) {
TERR("write BITMAP index of token %lu failed. ret %d",
pind1->term_sign, ret);
return -1;
}
// 1. TS_IDT_ZIP_BITMAP no break, go on to build & write zip index
// 2. TS_IDT_BITMAP break，不在保留 zip index
if(disk_type == TS_IDT_BITMAP) break;
}
case TS_IDT_ZIP:
{
ret = abandonOverflow(pbuilder->raw_buf, doc_count, base_num, useLen);
if(ret < 0) {
TERR("abandon overflow(zip) error, sign=%lu", node.sign);
return -1;
} else if(ret > 0) {
TERR("idx2 docnum over bit level(zip), lastNum=%u, line sign=%lu",
doc_count, pind1->term_sign);
}
ret = buildP4DIndex(pbuilder->raw_buf, doc_count, pbuilder->final_buf);
// add index1 node
pind1->file_num = pbuilder->inverted_fd_num - 1;
pind1->pos = pbuilder->cur_size;
pind1->doc_count = doc_count;
pind1->len = ret;
pind1->zip_flag = 2;
pind1->not_orig_flag = ( false == _rebuildFlag ) ? 0 : 1;
ret = idx_dict_add(pbuilder->inverted_dict, &node);
if (unlikely(ret<0)) {
TERR("add token %lu to idx1 dict failed. ret %d",
node.sign, ret);
return -1;
}
// write index2
ret = write(pbuilder->inverted_fd[pind1->file_num],
pbuilder->final_buf, pind1->len);
if (unlikely((unsigned)ret != pind1->len)) {
TERR("write ZIP index of token %lu to file %d failed. ret %d",
pind1->term_sign, pind1->file_num, ret);
return -1;
}
break;
}
default:
{
TERR("wrong IDX_DISK_TYPE %d of token %lu",
disk_type, pind1->term_sign);
return -1;
}
}
// update cur_size
if(disk_type != TS_IDT_BITMAP) {
ret = update_cur_size(pind1->len);
if(unlikely(ret<0)) {
TERR("update file_size of file_no %d failed", pind1->file_num);
return -1;
}
}
return doc_count;
}
/* setup_irq ----------------------------------------------------------------*/
static void
setup_irq()
{
set_idt(VECT_IRQ0, (unsigned long)intr_irq0, SEL_K32_C, 0, GT_INTR);
set_idt(VECT_IRQ1, (unsigned long)intr_irq1, SEL_K32_C, 0, GT_INTR);
set_idt(VECT_IRQ2, (unsigned long)intr_irq2, SEL_K32_C, 0, GT_INTR);
set_idt(VECT_IRQ3, (unsigned long)intr_irq3, SEL_K32_C, 0, GT_INTR);
set_idt(VECT_IRQ4, (unsigned long)intr_irq4, SEL_K32_C, 0, GT_INTR);
set_idt(VECT_IRQ5, (unsigned long)intr_irq5, SEL_K32_C, 0, GT_INTR);
set_idt(VECT_IRQ6, (unsigned long)intr_irq6, SEL_K32_C, 0, GT_INTR);
set_idt(VECT_IRQ7, (unsigned long)intr_irq7, SEL_K32_C, 0, GT_INTR);
set_idt(VECT_IRQ8, (unsigned long)intr_irq8, SEL_K32_C, 0, GT_INTR);
set_idt(VECT_IRQ9, (unsigned long)intr_irq9, SEL_K32_C, 0, GT_INTR);
set_idt(VECT_IRQ10, (unsigned long)intr_irq10, SEL_K32_C, 0, GT_INTR);
set_idt(VECT_IRQ11, (unsigned long)intr_irq11, SEL_K32_C, 0, GT_INTR);
set_idt(VECT_IRQ12, (unsigned long)intr_irq12, SEL_K32_C, 0, GT_INTR);
set_idt(VECT_IRQ13, (unsigned long)intr_irq13, SEL_K32_C, 0, GT_INTR);
set_idt(VECT_IRQ14, (unsigned long)intr_irq14, SEL_K32_C, 0, GT_INTR);
set_idt(VECT_IRQ15, (unsigned long)intr_irq15, SEL_K32_C, 0, GT_INTR);
}
/* setup_trap ---------------------------------------------------------------*/
static void
setup_trap()
{
set_idt(0, (unsigned long)intr_divide, SEL_K32_C, 0, GT_TRAP);
set_idt(1, (unsigned long)intr_singlestep, SEL_K32_C, 0, GT_TRAP);
set_idt(2, (unsigned long)intr_nmi, SEL_K32_C, 0, GT_TRAP);
set_idt(3, (unsigned long)intr_breakpoint, SEL_K32_C, 0, GT_TRAP);
set_idt(4, (unsigned long)intr_overflow, SEL_K32_C, 0, GT_TRAP);
set_idt(5, (unsigned long)intr_bounds, SEL_K32_C, 0, GT_TRAP);
set_idt(6, (unsigned long)intr_opcode, SEL_K32_C, 0, GT_TRAP);
set_idt(7, (unsigned long)intr_copr_not_available, SEL_K32_C,0,GT_TRAP);
set_idt(8, (unsigned long)intr_doublefault, SEL_K32_C, 0, GT_TRAP);
set_idt(9, (unsigned long)intr_copr_seg_overrun, SEL_K32_C, 0, GT_TRAP);
set_idt(10, (unsigned long)intr_tss, SEL_K32_C, 0, GT_TRAP);
set_idt(11,(unsigned long)intr_segment_not_present,SEL_K32_C,0,GT_TRAP);
set_idt(12, (unsigned long)intr_stack, SEL_K32_C, 0, GT_TRAP);
set_idt(13, (unsigned long)intr_general, SEL_K32_C, 0, GT_TRAP);
set_idt(14, (unsigned long)intr_page, SEL_K32_C, 0, GT_TRAP);
set_idt(15, (unsigned long)intr_copr_error, SEL_K32_C, 0, GT_TRAP);
}
int idt_initialize()
{
memset_int(&idts,0,sizeof(struct idt_struct)*NUM_IDT_DESCR);
idt_base.limit = (NUM_IDT_DESCR*sizeof(struct idt_struct))-1;
idt_base.base = (unsigned int)&idts;
//Remap the irq table.
outb(0x20,0x11);
outb(0xA0,0x11);
outb(0x21,0x20);
outb(0xA1,0x28);
outb(0x21,0x04);
outb(0xA1,0x02);
outb(0x21,0x01);
outb(0xA1,0x01);
outb(0x21,0x00);
outb(0xA1,0x00);
set_idt(0, (unsigned int) isr0, 0x08, 0x8E);
set_idt(1, (unsigned int) isr1, 0x08, 0x8E);
set_idt(2, (unsigned int) isr2, 0x08, 0x8E);
set_idt(3, (unsigned int) isr3, 0x08, 0x8E);
set_idt(4, (unsigned int) isr4, 0x08, 0x8E);
set_idt(5, (unsigned int) isr5, 0x08, 0x8E);
set_idt(6, (unsigned int) isr6, 0x08, 0x8E);
set_idt(7, (unsigned int) isr7, 0x08, 0x8E);
set_idt(8, (unsigned int) isr8, 0x08, 0x8E);
set_idt(9, (unsigned int) isr9, 0x08, 0x8E);
set_idt(10, (unsigned int) isr10, 0x08, 0x8E);
set_idt(11, (unsigned int) isr11, 0x08, 0x8E);
set_idt(12, (unsigned int) isr12, 0x08, 0x8E);
set_idt(13, (unsigned int) isr13, 0x08, 0x8E);
set_idt(14, (unsigned int) isr14, 0x08, 0x8E);
set_idt(15, (unsigned int) isr15, 0x08, 0x8E);
set_idt(16, (unsigned int) isr16, 0x08, 0x8E);
set_idt(17, (unsigned int) isr17, 0x08, 0x8E);
set_idt(18, (unsigned int) isr18, 0x08, 0x8E);
set_idt(19, (unsigned int) isr19, 0x08, 0x8E);
set_idt(20, (unsigned int) isr20, 0x08, 0x8E);
set_idt(21, (unsigned int) isr21, 0x08, 0x8E);
set_idt(22, (unsigned int) isr22, 0x08, 0x8E);
set_idt(23, (unsigned int) isr23, 0x08, 0x8E);
set_idt(24, (unsigned int) isr24, 0x08, 0x8E);
set_idt(25, (unsigned int) isr25, 0x08, 0x8E);
set_idt(26, (unsigned int) isr26, 0x08, 0x8E);
set_idt(27, (unsigned int) isr27, 0x08, 0x8E);
set_idt(28, (unsigned int) isr28, 0x08, 0x8E);
set_idt(29, (unsigned int) isr29, 0x08, 0x8E);
set_idt(30, (unsigned int) isr30, 0x08, 0x8E);
set_idt(31, (unsigned int) isr31, 0x08, 0x8E);
set_idt(32, (unsigned int) irq0, 0x08,0x8E);
set_idt(33, (unsigned int) irq1, 0x08,0x8E);
set_idt(34, (unsigned int) irq2, 0x08,0x8E);
set_idt(35, (unsigned int) irq3, 0x08,0x8E);
set_idt(36, (unsigned int) irq4, 0x08,0x8E);
set_idt(37, (unsigned int) irq5, 0x08,0x8E);
set_idt(38, (unsigned int) irq6, 0x08,0x8E);
set_idt(39, (unsigned int) irq7, 0x08,0x8E);
set_idt(40, (unsigned int) irq8, 0x08,0x8E);
set_idt(41, (unsigned int) irq9, 0x08,0x8E);
set_idt(42, (unsigned int) irq10, 0x08,0x8E);
set_idt(43, (unsigned int) irq11, 0x08,0x8E);
set_idt(44, (unsigned int) irq12, 0x08,0x8E);
set_idt(45, (unsigned int) irq13, 0x08,0x8E);
set_idt(46, (unsigned int) irq14, 0x08,0x8E);
set_idt(47, (unsigned int) irq15, 0x08,0x8E);
// Load IDT
asm volatile ("movl %0,%%eax"::"r"(&idt_base):"%eax");
asm volatile ("lidt (%eax)");
}
static void idt_init(){
i_ptr.limit = sizeof(struct w_idte) * 256 -1;
i_ptr.base = (w_uint32)&idt_entries;
zero_mem(&idt_entries, sizeof(struct w_idte) * 256);
/* Remap IRQ table */
out_byte(0x20, 0x11);
out_byte(0xA0, 0x11);
out_byte(0x21, 0x20);
out_byte(0xA1, 0x28);
out_byte(0x21, 0x04);
out_byte(0xA1, 0x02);
out_byte(0x21, 0x01);
out_byte(0xA1, 0x01);
out_byte(0x21, 0x0);
out_byte(0xA1, 0x0);
set_idt( 0, (w_uint32)isr0 , SEG_KERNEL_CODE, 0x8E);
set_idt( 1, (w_uint32)isr1 , SEG_KERNEL_CODE, 0x8E);
set_idt( 2, (w_uint32)isr2 , SEG_KERNEL_CODE, 0x8E);
set_idt( 3, (w_uint32)isr3 , SEG_KERNEL_CODE, 0x8E);
set_idt( 4, (w_uint32)isr4 , SEG_KERNEL_CODE, 0x8E);
set_idt( 5, (w_uint32)isr5 , SEG_KERNEL_CODE, 0x8E);
set_idt( 6, (w_uint32)isr6 , SEG_KERNEL_CODE, 0x8E);
set_idt( 7, (w_uint32)isr7 , SEG_KERNEL_CODE, 0x8E);
set_idt( 8, (w_uint32)isr8 , SEG_KERNEL_CODE, 0x8E);
set_idt( 9, (w_uint32)isr9 , SEG_KERNEL_CODE, 0x8E);
set_idt(10, (w_uint32)isr10, SEG_KERNEL_CODE, 0x8E);
set_idt(11, (w_uint32)isr11, SEG_KERNEL_CODE, 0x8E);
set_idt(12, (w_uint32)isr12, SEG_KERNEL_CODE, 0x8E);
set_idt(13, (w_uint32)isr13, SEG_KERNEL_CODE, 0x8E);
set_idt(14, (w_uint32)isr14, SEG_KERNEL_CODE, 0x8E);
set_idt(15, (w_uint32)isr15, SEG_KERNEL_CODE, 0x8E);
set_idt(16, (w_uint32)isr16, SEG_KERNEL_CODE, 0x8E);
set_idt(17, (w_uint32)isr17, SEG_KERNEL_CODE, 0x8E);
set_idt(18, (w_uint32)isr18, SEG_KERNEL_CODE, 0x8E);
set_idt(19, (w_uint32)isr19, SEG_KERNEL_CODE, 0x8E);
set_idt(20, (w_uint32)isr20, SEG_KERNEL_CODE, 0x8E);
set_idt(21, (w_uint32)isr21, SEG_KERNEL_CODE, 0x8E);
set_idt(22, (w_uint32)isr22, SEG_KERNEL_CODE, 0x8E);
set_idt(23, (w_uint32)isr23, SEG_KERNEL_CODE, 0x8E);
set_idt(24, (w_uint32)isr24, SEG_KERNEL_CODE, 0x8E);
set_idt(25, (w_uint32)isr25, SEG_KERNEL_CODE, 0x8E);
set_idt(26, (w_uint32)isr26, SEG_KERNEL_CODE, 0x8E);
set_idt(27, (w_uint32)isr27, SEG_KERNEL_CODE, 0x8E);
set_idt(28, (w_uint32)isr28, SEG_KERNEL_CODE, 0x8E);
set_idt(29, (w_uint32)isr29, SEG_KERNEL_CODE, 0x8E);
set_idt(30, (w_uint32)isr30, SEG_KERNEL_CODE, 0x8E);
set_idt(31, (w_uint32)isr31, SEG_KERNEL_CODE, 0x8E);
set_idt(32, (w_uint32)irq0, SEG_KERNEL_CODE, 0x8E);
set_idt(33, (w_uint32)irq1, SEG_KERNEL_CODE, 0x8E);
set_idt(34, (w_uint32)irq2, SEG_KERNEL_CODE, 0x8E);
set_idt(35, (w_uint32)irq3, SEG_KERNEL_CODE, 0x8E);
set_idt(36, (w_uint32)irq4, SEG_KERNEL_CODE, 0x8E);
set_idt(37, (w_uint32)irq5, SEG_KERNEL_CODE, 0x8E);
set_idt(38, (w_uint32)irq6, SEG_KERNEL_CODE, 0x8E);
set_idt(39, (w_uint32)irq7, SEG_KERNEL_CODE, 0x8E);
set_idt(40, (w_uint32)irq8, SEG_KERNEL_CODE, 0x8E);
set_idt(41, (w_uint32)irq9, SEG_KERNEL_CODE, 0x8E);
set_idt(42, (w_uint32)irq10, SEG_KERNEL_CODE, 0x8E);
set_idt(43, (w_uint32)irq11, SEG_KERNEL_CODE, 0x8E);
set_idt(44, (w_uint32)irq12, SEG_KERNEL_CODE, 0x8E);
set_idt(45, (w_uint32)irq13, SEG_KERNEL_CODE, 0x8E);
set_idt(46, (w_uint32)irq14, SEG_KERNEL_CODE, 0x8E);
set_idt(47, (w_uint32)irq15, SEG_KERNEL_CODE, 0x8E);
idt_flush(&i_ptr);
}
/* Check if MAGIC is valid and print the Multiboot information structure
pointed by ADDR. */
void
entry (unsigned long magic, unsigned long addr)
{
multiboot_info_t *mbi;
uint8_t* filesystem_address;
/* Clear the screen. */
clear();
/* Am I booted by a Multiboot-compliant boot loader? */
if (magic != MULTIBOOT_BOOTLOADER_MAGIC)
{
printf ("Invalid magic number: 0x%#x\n", (unsigned) magic);
return;
}
/* Set MBI to the address of the Multiboot information structure. */
mbi = (multiboot_info_t *) addr;
/* Print out the flags. */
printf ("flags = 0x%#x\n", (unsigned) mbi->flags);
/* Are mem_* valid? */
if (CHECK_FLAG (mbi->flags, 0))
printf ("mem_lower = %uKB, mem_upper = %uKB\n",
(unsigned) mbi->mem_lower, (unsigned) mbi->mem_upper);
/* Is boot_device valid? */
if (CHECK_FLAG (mbi->flags, 1))
printf ("boot_device = 0x%#x\n", (unsigned) mbi->boot_device);
/* Is the command line passed? */
if (CHECK_FLAG (mbi->flags, 2))
printf ("cmdline = %s\n", (char *) mbi->cmdline);
if (CHECK_FLAG (mbi->flags, 3)) {
int mod_count = 0;
int i;
module_t* mod = (module_t*)mbi->mods_addr;
while(mod_count < mbi->mods_count) {
filesystem_address = (uint8_t*)mod->mod_start;
printf("Module %d loaded at address: 0x%#x\n", mod_count, (unsigned int)mod->mod_start);
printf("Module %d ends at address: 0x%#x\n", mod_count, (unsigned int)mod->mod_end);
printf("First few bytes of module:\n");
for(i = 0; i<16; i++) {
printf("0x%x ", *((char*)(mod->mod_start+i)));
}
printf("\n");
mod_count++;
mod++;
}
}
/* Bits 4 and 5 are mutually exclusive! */
if (CHECK_FLAG (mbi->flags, 4) && CHECK_FLAG (mbi->flags, 5))
{
printf ("Both bits 4 and 5 are set.\n");
return;
}
/* Is the section header table of ELF valid? */
if (CHECK_FLAG (mbi->flags, 5))
{
elf_section_header_table_t *elf_sec = &(mbi->elf_sec);
printf ("elf_sec: num = %u, size = 0x%#x,"
" addr = 0x%#x, shndx = 0x%#x\n",
(unsigned) elf_sec->num, (unsigned) elf_sec->size,
(unsigned) elf_sec->addr, (unsigned) elf_sec->shndx);
}
/* Are mmap_* valid? */
if (CHECK_FLAG (mbi->flags, 6))
{
memory_map_t *mmap;
printf ("mmap_addr = 0x%#x, mmap_length = 0x%x\n",
(unsigned) mbi->mmap_addr, (unsigned) mbi->mmap_length);
for (mmap = (memory_map_t *) mbi->mmap_addr;
(unsigned long) mmap < mbi->mmap_addr + mbi->mmap_length;
mmap = (memory_map_t *) ((unsigned long) mmap
+ mmap->size + sizeof (mmap->size)))
printf (" size = 0x%x, base_addr = 0x%#x%#x\n"
" type = 0x%x, length = 0x%#x%#x\n",
(unsigned) mmap->size,
(unsigned) mmap->base_addr_high,
(unsigned) mmap->base_addr_low,
(unsigned) mmap->type,
(unsigned) mmap->length_high,
(unsigned) mmap->length_low);
}
/* Construct an LDT entry in the GDT */
{
seg_desc_t the_ldt_desc;
the_ldt_desc.granularity = 0;
the_ldt_desc.opsize = 1;
the_ldt_desc.reserved = 0;
the_ldt_desc.avail = 0;
the_ldt_desc.present = 1;
the_ldt_desc.dpl = 0x0;
the_ldt_desc.sys = 0;
the_ldt_desc.type = 0x2;
SET_LDT_PARAMS(the_ldt_desc, &ldt, ldt_size);
ldt_desc_ptr = the_ldt_desc;
lldt(KERNEL_LDT);
}
/* Construct a TSS entry in the GDT */
{
seg_desc_t the_tss_desc;
the_tss_desc.granularity = 0;
the_tss_desc.opsize = 0;
the_tss_desc.reserved = 0;
the_tss_desc.avail = 0;
the_tss_desc.seg_lim_19_16 = TSS_SIZE & 0x000F0000;
the_tss_desc.present = 1;
the_tss_desc.dpl = 0x0;
the_tss_desc.sys = 0;
the_tss_desc.type = 0x9;
the_tss_desc.seg_lim_15_00 = TSS_SIZE & 0x0000FFFF;
SET_TSS_PARAMS(the_tss_desc, &tss, tss_size);
tss_desc_ptr = the_tss_desc;
tss.ldt_segment_selector = KERNEL_LDT;
tss.ss0 = KERNEL_DS;
tss.esp0 = 0x800000;
ltr(KERNEL_TSS);
}
int z = 0;
reset_scr();
//set the IDT
set_idt();
lidt(idt_desc_ptr);
/* Init the PIC */
i8259_init();
/* Initialize devices, memory, filesystem, enable device interrupts on the
* PIC, any other initialization stuff... */
//init paging
init_paging();
//init filesystem
init_filesys(filesystem_address);
//init keyboard
init_keyboard();
//init the rtc
init_rtc();
//init the mouse
init_mouse();
//clear the screen
reset_scr();
// boot_screen();
for(z = 0; z < 3; z++)
{
terminal_init();
}
node* buffer = screens[0];
reset_buf(buffer);
//display the status bar
/* Enable interrupts */
sti();
/* Do not enable the following until after you have set up your
* IDT correctly otherwise QEMU will triple fault and simple close
* without showing you any output */
boot_screen();
//sample mario sound
for(z = 0; z < 500000; z++)
play_sound(1000);
for(z = 0; z < 500000; z++)
play_sound(100);
for(z = 0; z < 500000; z++)
play_sound(900);
for(z = 0; z < 50000; z++)
play_sound(200);
for(z = 0; z < 500000; z++)
play_sound(800);
for(z = 0; z < 500000; z++)
play_sound(300);
for(z = 0; z < 500000; z++)
play_sound(700);
for(z = 0; z < 500000; z++)
play_sound(400);
for(z = 0; z < 500000; z++)
play_sound(600);
for(z = 0; z < 500000; z++)
play_sound(500);
for(z = 0; z < 500000; z++)
play_sound(500);
for(z = 0; z < 500000; z++)
play_sound(1000);
for(z = 0; z < 500000; z++)
play_sound(400);
for(z = 0; z < 500000; z++)
play_sound(300);
for(z = 0; z < 500000; z++)
play_sound(300);
for(z = 0; z < 500000; z++)
play_sound(200);
//boot_screen();
nosound();
reset_scr();
//init PIT for sound, timer
init_pit(0, 100);
/////////////////////////////////////////////////////////////
// void imperial();
status_bar();
/* Execute the first program (`shell') ... */
uint8_t fname[33] = "shell";
execute(fname);
/* We should never get to this point */
//printf("Initial shell halted.");
/* Spin (nicely, so we don't chew up cycles) */
asm volatile(".1: hlt; jmp .1;");
}
int emu_0f(unsigned char *lina)
{
unsigned char *orig_lina = lina;
switch (lina[1]) {
case 0x00: /* lldt, ltr */
{
switch (REG_OPCODE(lina[2])) {
case 2: /* 0F 00 /2 LLDT r/m16 Load segment selector r/m16 into LDTR */
{
u_int addr, is_addr, reg, selector;
trace("lldt\n");
if (!opa.pe) {
set_guest_exc(EXC_UD, 0);
goto exc;
}
if (opa.cpl != 0) {
set_guest_exc(EXC_GP, 0);
goto exc;
}
lina += 2; /* move up to RM byte */
decode_rm16(&addr, &is_addr, ®, &lina);
if (emu_get(is_addr, addr, &selector, 2))
goto exc;
if (load_ldtr(selector))
goto exc;
break;
}
case 3: /* 0F 00 /3 LTR r/m16 Load r/m16 into TR */
{
u_int addr, is_addr, reg;
Bit32u dtr;
trace("ltr\n");
if (!opa.pe) {
set_guest_exc(EXC_UD, 0);
goto exc;
}
if (opa.cpl != 0) {
set_guest_exc(EXC_GP, 0);
goto exc;
}
lina += 2; /* move up to RM byte */
decode_rm16(&addr, &is_addr, ®, &lina);
if (emu_get(is_addr, addr, &dtr, 2))
goto exc;
if (load_tr(dtr))
goto exc;
break;
}
default:
unknown(lina);
}
break;
}
case 0x01: /* invlpg, lgdt, lidt, lmsw */
{
int reg_op = REG_OPCODE(lina[2]);
switch (reg_op) {
case 2: /* lgdt */
case 3: /* lidt */
{
u_int addr, is_addr, reg, limit, base;
lina += 2; /* move up to RM byte */
decode_rm(&addr, &is_addr, ®, &lina);
ASSERT(is_addr);
/* addr now points to the m16&32; lina is at next instr */
if (get_memory(opa.seg, addr, &limit, 2) != 0 ||
get_memory(opa.seg, addr+2, &base, opa.opb==4 ? 4 : 3) != 0)
goto exc;
/* by definition of lgdt/lidt, base is a linear address already. */
if (reg_op == 2) {
set_gdt(base, limit);
} else {
set_idt(base, limit);
}
debug_mem("loaded %cdt from 0x%08x\n", reg_op==2 ? 'g' : 'i', base);
break;
}
case 6: /* 0F 01 /6 LMSW r/m16 Loads r/m16 in msw of CR0 */
{
u_int addr, is_addr, reg, val;
trace("lmsw\n");
if (opa.pe && opa.cpl!=0) {
set_guest_exc(13, 0);
goto exc;
}
lina += 2; /* move up to RM byte */
decode_rm16(&addr, &is_addr, ®, &lina);
if (emu_get(is_addr, addr, &val, 2))
goto exc;
if (vmstate.cr[0] & 1 && !(val & 1))
val |= 1; /* can't clear PE with lmsw */
mov_to_cr(0, val, 0x0000000f); /* only PE, MP, EM, and TS can be affected */
break;
}
case 7: /* invlpg */
{
Bit32u ptr;
debug("invlpg\n");
lina += 2; /* move up to memory operand */
if (opa.opb==4) {
ptr = *(Bit32u*)lina;
} else {
ptr = *(Bit16u*)lina;
}
lina += opa.opb;
if (vmstate.cr[0]&PG_MASK) {
/* Modify a pte with itself. This should have the desired side
effect of flushing that TLB entry. */
sys_self_mod_pte_range(0, 0, /* add no flag bits */
0, /* remove no flag bits */
ptr, 1);
}
break;
}
default:
unknown(lina);
}
break;
}
case 0x06: /* clts 0F 06 */
{
if (opa.cpl!=0) {
set_guest_exc(13, 0);
goto exc;
} else {
vmstate.cr[0] &= ~TS_MASK;
lina += 2;
}
break;
}
case 0x08: /* invd 0F 08 */
case 0x09: /* wbinvd 0F 09 */
{
if (opa.cpl!=0) {
set_guest_exc(13, 0);
goto exc;
} else {
/* will not implement */
lina += 2;
}
break;
}
case 0x0b: /* UD2 */
{
set_guest_exc(6, 0);
goto exc;
}
case 0x20: /* MOV r <- CRx */
{
int cr = REG_OPCODE(lina[2]);
int reg = RM(lina[2]);
ASSERT(cr<5);
set_reg(reg, vmstate.cr[cr], 4);
lina += 3;
break;
}
case 0x21: /* MOV r <- DRx */
{
int dr = REG_OPCODE(lina[2]);
int reg = RM(lina[2]);
set_reg(reg, vmstate.dr[dr], 4);
lina += 3;
break;
}
case 0x22: /* MOV CRx <- r */
{
int cr = REG_OPCODE(lina[2]);
ASSERT(cr<5);
if (opa.pe && opa.cpl!=0) {
set_guest_exc(13, 0);
goto exc;
}
mov_to_cr(cr, get_reg(RM(lina[2]), 4), 0xffffffff);
lina += 3;
break;
}
case 0x23: /* MOV DRx <- r */
{
int dr = REG_OPCODE(lina[2]);
debug("mov dr%d <- r%d\n", dr, RM(lina[2]));
if (opa.pe && opa.cpl!=0) {
set_guest_exc(13, 0);
goto exc;
}
vmstate.dr[dr] = get_reg(RM(lina[2]), 4);
lina += 3;
break;
}
case 0x30: /* wrmsr */
{
int ctr = 0;
if (REG(ecx) == P6MSR_CTRSEL0)
ctr = 0;
else if (REG(ecx) == P6MSR_CTRSEL1)
ctr = 1;
else
unknown(lina); /* only performance counters are implemented */
sys_pctr(ctr==0 ? PCIOCS0 : PCIOCS1, 0, ®(eax));
lina += 2;
break;
}
case 0x32: /* rdmsr */
{
struct pctrst p;
int ctr = 0;
if (REG(ecx) == P6MSR_CTR0)
ctr = 0;
else if (REG(ecx) == P6MSR_CTR1)
ctr = 1;
else
unknown(lina); /* only performance counters are implemented */
sys_pctr(PCIOCRD, 0, &p);
REG(eax) = p.pctr_hwc[ctr];
REG(edx) = p.pctr_hwc[ctr] >> 32;
lina += 2;
break;
}
#if 0
case 0x33: /* rdpmc */
{
struct pctrst p;
/* or cpl!=0 and cr4 ... */
if (REG(ecx)>1) {
set_guest_exc(EXC_GP, 0);
goto exc;
}
sys_pctr(PCIOCRD, 0, &p);
REG(eax) = p.pctr_hwc[REG(ecx)];
REG(edx) = p.pctr_hwc[REG(ecx)] >> 32;
lina += 2;
break;
}
#endif
case 0xa2: /* cpuid */
{
/* cpuid may trap on a Cyrix. I don't care. */
leaveemu(ERR_UNIMPL);
break;
}
case 0xb2: /* lss */
case 0xb4: /* lfs */
case 0xb5: /* lgs */
{
int seg;
if (lina[1]==0xb2) {
seg = REGNO_SS;
} else if (lina[1]==0xb4) {
seg = REGNO_FS;
} else
seg = REGNO_GS;
if (load_far_pointer(&lina, seg))
goto exc;
break;
}
case 0x31: /* rdtsc ... should be enabled in xok */
case 0xc8: /* bswap should not trap */
default:
unknown(lina);
}
REG(eip) += lina-orig_lina;
return 0;
exc:
return -1;
}
/* Can't do this with a loop because we need the address
* of the function names */
void isr_install() {
set_idt_gate(0, (uint32_t)isr0);
set_idt_gate(1, (uint32_t)isr1);
set_idt_gate(2, (uint32_t)isr2);
set_idt_gate(3, (uint32_t)isr3);
set_idt_gate(4, (uint32_t)isr4);
set_idt_gate(5, (uint32_t)isr5);
set_idt_gate(6, (uint32_t)isr6);
set_idt_gate(7, (uint32_t)isr7);
set_idt_gate(8, (uint32_t)isr8);
set_idt_gate(9, (uint32_t)isr9);
set_idt_gate(10, (uint32_t)isr10);
set_idt_gate(11, (uint32_t)isr11);
set_idt_gate(12, (uint32_t)isr12);
set_idt_gate(13, (uint32_t)isr13);
set_idt_gate(14, (uint32_t)isr14);
set_idt_gate(15, (uint32_t)isr15);
set_idt_gate(16, (uint32_t)isr16);
set_idt_gate(17, (uint32_t)isr17);
set_idt_gate(18, (uint32_t)isr18);
set_idt_gate(19, (uint32_t)isr19);
set_idt_gate(20, (uint32_t)isr20);
set_idt_gate(21, (uint32_t)isr21);
set_idt_gate(22, (uint32_t)isr22);
set_idt_gate(23, (uint32_t)isr23);
set_idt_gate(24, (uint32_t)isr24);
set_idt_gate(25, (uint32_t)isr25);
set_idt_gate(26, (uint32_t)isr26);
set_idt_gate(27, (uint32_t)isr27);
set_idt_gate(28, (uint32_t)isr28);
set_idt_gate(29, (uint32_t)isr29);
set_idt_gate(30, (uint32_t)isr30);
set_idt_gate(31, (uint32_t)isr31);
// Remap the PIC
port_byte_out(0x20, 0x11);
port_byte_out(0xA0, 0x11);
port_byte_out(0x21, 0x20);
port_byte_out(0xA1, 0x28);
port_byte_out(0x21, 0x04);
port_byte_out(0xA1, 0x02);
port_byte_out(0x21, 0x01);
port_byte_out(0xA1, 0x01);
port_byte_out(0x21, 0x0);
port_byte_out(0xA1, 0x0);
// Install the IRQs
set_idt_gate(32, (uint32_t)irq0);
set_idt_gate(33, (uint32_t)irq1);
set_idt_gate(34, (uint32_t)irq2);
set_idt_gate(35, (uint32_t)irq3);
set_idt_gate(36, (uint32_t)irq4);
set_idt_gate(37, (uint32_t)irq5);
set_idt_gate(38, (uint32_t)irq6);
set_idt_gate(39, (uint32_t)irq7);
set_idt_gate(40, (uint32_t)irq8);
set_idt_gate(41, (uint32_t)irq9);
set_idt_gate(42, (uint32_t)irq10);
set_idt_gate(43, (uint32_t)irq11);
set_idt_gate(44, (uint32_t)irq12);
set_idt_gate(45, (uint32_t)irq13);
set_idt_gate(46, (uint32_t)irq14);
set_idt_gate(47, (uint32_t)irq15);
set_idt(); // Load with ASM
}