int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id) { u32 idx = ffz(gd->used_laws); if (idx >= FSL_HW_NUM_LAWS) return -1; set_law(idx, addr, sz, id); return idx; }
void init_laws(void) { int i; gd->used_laws = ~((1 << FSL_HW_NUM_LAWS) - 1); for (i = 0; i < num_law_entries; i++) { if (law_table[i].index == -1) set_next_law(law_table[i].addr, law_table[i].size, law_table[i].trgt_id); else set_law(law_table[i].index, law_table[i].addr, law_table[i].size, law_table[i].trgt_id); } return ; }
int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id) { u32 idx; /* we have no LAWs free */ if (gd->used_laws == -1) return -1; /* grab the last free law */ idx = __ilog2(~(gd->used_laws)); if (idx >= FSL_HW_NUM_LAWS) return -1; set_law(idx, addr, sz, id); return idx; }
void init_laws(void) { int i; #if FSL_HW_NUM_LAWS < 32 gd->used_laws = ~((1 << FSL_HW_NUM_LAWS) - 1); #elif FSL_HW_NUM_LAWS == 32 gd->used_laws = 0; #else #error FSL_HW_NUM_LAWS can not be greater than 32 w/o code changes #endif /* * Any LAWs that were set up before we booted assume they are meant to * be around and mark them used. */ for (i = 0; i < FSL_HW_NUM_LAWS; i++) { u32 lawar = in_be32(LAWAR_ADDR(i)); if (lawar & LAW_EN) gd->used_laws |= (1 << i); } #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) /* * in NAND boot we've already parsed the law_table and setup those LAWs * so don't do it again. */ return; #endif for (i = 0; i < num_law_entries; i++) { if (law_table[i].index == -1) set_next_law(law_table[i].addr, law_table[i].size, law_table[i].trgt_id); else set_law(law_table[i].index, law_table[i].addr, law_table[i].size, law_table[i].trgt_id); } return ; }
void initsdram(void) { volatile ccsr_ddr_t *ddr= (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR; int d_init, dbw; volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); unsigned int ddr_size; sys_info_t sysinfo; phys_size_t dram_size = 0; set_law(CONFIG_SYS_NAND_DDR_LAW, 0, LAW_SIZE_1G , LAW_TRGT_IF_DDR_1); out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS); out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG); out_be32(&ddr->cs0_config_2, CONFIG_SYS_DDR_CS0_CONFIG_2); out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3_667); out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0_667); out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1_667); out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2_667); out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1_667); out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2_667); out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL_667); out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL_667); #if defined(CONFIG_P2020) || defined(CONFIG_P2010) out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL); #elif defined(CONFIG_P1020) || defined(CONFIG_P1011) out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | SDRAM_CFG_32_BE); #endif out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL_2); asm("sync;isync"); udelay(500); ddr->sdram_cfg |= 0x80000000; }
void init_laws(void) { int i; #if FSL_HW_NUM_LAWS < 32 gd->used_laws = ~((1 << FSL_HW_NUM_LAWS) - 1); #elif FSL_HW_NUM_LAWS == 32 gd->used_laws = 0; #else #error FSL_HW_NUM_LAWS can not be greater than 32 w/o code changes #endif for (i = 0; i < num_law_entries; i++) { if (law_table[i].index == -1) set_next_law(law_table[i].addr, law_table[i].size, law_table[i].trgt_id); else set_law(law_table[i].index, law_table[i].addr, law_table[i].size, law_table[i].trgt_id); } return ; }
Interpret::Interpret() { Lexer::set_interpret(this); set_lexer(new OpenLexer()); set_law(new SimpleLaw()); }
void init_laws(void) { int i; #if FSL_HW_NUM_LAWS < 32 gd->used_laws = ~((1 << FSL_HW_NUM_LAWS) - 1); #elif FSL_HW_NUM_LAWS == 32 gd->used_laws = 0; #else #error FSL_HW_NUM_LAWS can not be greater than 32 w/o code changes #endif /* * Any LAWs that were set up before we booted assume they are meant to * be around and mark them used. */ for (i = 0; i < FSL_HW_NUM_LAWS; i++) { u32 lawar = in_be32(LAWAR_ADDR(i)); if (lawar & LAW_EN) gd->used_laws |= (1 << i); } #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) /* * in NAND boot we've already parsed the law_table and setup those LAWs * so don't do it again. */ return; #endif for (i = 0; i < num_law_entries; i++) { if (law_table[i].index == -1) set_next_law(law_table[i].addr, law_table[i].size, law_table[i].trgt_id); else set_law(law_table[i].index, law_table[i].addr, law_table[i].size, law_table[i].trgt_id); } #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE /* check RCW to get which port is used for boot */ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; u32 bootloc = in_be32(&gur->rcwsr[6]); /* * in SRIO or PCIE boot we need to set specail LAWs for * SRIO or PCIE interfaces. */ switch ((bootloc & FSL_CORENET_RCWSR6_BOOT_LOC) >> 23) { case 0x0: /* boot from PCIE1 */ set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1); set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1); break; case 0x1: /* boot from PCIE2 */ set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_2); set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_2); break; case 0x2: /* boot from PCIE3 */ set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_3); set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_3); break; case 0x8: /* boot from SRIO1 */ set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_RIO_1); set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_RIO_1); break; case 0x9: /* boot from SRIO2 */ set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_RIO_2); set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_RIO_2); break; default: break; } #endif return ; }