/***************************************** * Configure RS780 registers to power-on default RPR. * POR: Power On Reset * RPR: Register Programming Requirements *****************************************/ static void rs780_por_init(pci_devfn_t nb_dev) { printk(BIOS_INFO, "rs780_por_init\n"); /* ATINB_PCICFG_POR_TABLE, initialize the values for rs780 PCI Config registers */ rs780_por_pcicfg_init(nb_dev); /* ATINB_MCIND_POR_TABLE */ rs780_por_mc_index_init(nb_dev); /* ATINB_MISCIND_POR_TABLE */ rs780_por_misc_index_init(nb_dev); /* ATINB_HTIUNBIND_POR_TABLE */ rs780_por_htiu_index_init(nb_dev); /* ATINB_CLKCFG_PORT_TABLE */ /* rs780 A11 SB Link full swing? */ /* SET NB_MISC_REG01 BIT8 to Enable HDMI, reference CIMX_5_9_3 NBPOR_InitPOR(), * then the accesses to internal graphics IO space 0x60/0x64, are forwarded to * nbconfig:0x60/0x64 */ set_nbmisc_enable_bits(nb_dev, 0x01, ~(1 << 8), (1 << 8)); }
/***************************************** * Compliant with CIM_33's PCIEMiscClkProg *****************************************/ void pcie_config_misc_clk(device_t nb_dev) { u32 reg; //struct bus pbus; /* fake bus for dev0 fun1 */ reg = pci_read_config32(nb_dev, 0x4c); reg |= 1 << 0; pci_write_config32(nb_dev, 0x4c, reg); #if 0 /* TODO: Check the mics clock later. */ if (AtiPcieCfg.Config & PCIE_GFX_CLK_GATING) { /* TXCLK Clock Gating */ set_nbmisc_enable_bits(nb_dev, 0x07, 3 << 0, 3 << 0); set_nbmisc_enable_bits(nb_dev, 0x07, 1 << 22, 1 << 22); set_pcie_enable_bits(nb_dev, 0x11 | PCIE_CORE_INDEX_GFX, (3 << 6) | (~0xf), 3 << 6); /* LCLK Clock Gating */ reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x94); reg &= ~(1 << 16); pci_cf8_conf1.write32(&pbus, 0, 1, 0x94, reg); } if (AtiPcieCfg.Config & PCIE_GPP_CLK_GATING) { /* TXCLK Clock Gating */ set_nbmisc_enable_bits(nb_dev, 0x07, 3 << 4, 3 << 4); set_nbmisc_enable_bits(nb_dev, 0x07, 1 << 22, 1 << 22); set_pcie_enable_bits(nb_dev, 0x11 | PCIE_CORE_INDEX_SB, (3 << 6) | (~0xf), 3 << 6); /* LCLK Clock Gating */ reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x94); reg &= ~(1 << 24); pci_cf8_conf1.write32(&pbus, 0, 1, 0x94, reg); } #endif reg = pci_read_config32(nb_dev, 0x4c); reg &= ~(1 << 0); pci_write_config32(nb_dev, 0x4c, reg); }
void rs780_after_pci_fixup(void) { device_t dev; /* bus0, dev0, fun0; */ dev = _pci_make_tag(0, 0, 0); rs780_enable(dev); #if 1 /* bus0, dev1, APC. */ printk_info("Bus-0, Dev-1, Fun-0.\n"); dev = _pci_make_tag(0, 1, 0); rs780_internal_gfx_init(_pci_make_tag(0,0,0) , _pci_make_tag(0,1,0)); rs780_enable(dev); /* bus0, dev2,3, two GFX */ printk_info("Bus-0, Dev-2, Fun-0\n"); dev = _pci_make_tag(0, 2, 0); rs780_enable(dev); printk_info("Bus-0, Dev-3, Fun-0\n"); dev = _pci_make_tag(0, 3, 0); set_nbmisc_enable_bits(_pci_make_tag(0, 0, 0), 0x0c, 1 << 3,0 << 3); rs780_gfx_3_init(_pci_make_tag(0, 0, 0), dev, 3); /* bus0, dev4-7, four GPPSB */ printk_info("Bus-0, Dev-4, Fun-0\n"); dev = _pci_make_tag(0, 4, 0); rs780_enable(dev); printk_info("Bus-0, Dev-5, Fun-0\n"); dev = _pci_make_tag(0, 5, 0); rs780_enable(dev); printk_info("Bus-0, Dev-6, Fun-0\n"); dev = _pci_make_tag(0, 6, 0); rs780_enable(dev); printk_info("Bus-0, Dev-7, Fun-0\n"); dev = _pci_make_tag(0, 7, 0); rs780_enable(dev); /* bus 0, dev 9,10, GPP */ printk_info("Bus-0, Dev-9, Fun-0\n"); dev = _pci_make_tag(0, 9, 0); rs780_enable(dev); printk_info("Bus-0, Dev-10, Fun-0\n"); dev = _pci_make_tag(0, 10, 0); rs780_enable(dev); /* bus0, dev8, SB */ printk_info("Bus-0, Dev-8, Fun-0\n"); dev = _pci_make_tag(0, 8, 0); rs780_enable(dev); #endif }
void init_gen2(device_t nb_dev, device_t dev, u8 port) { u32 reg, val; /* for A11 (0x89 == 0) */ reg = 0x34; if (port <= 3){ val = 1<<5; }else{ val = 1<<31; if (port >= 9 ) reg = 0x39; } /* todo: check for rev > a11 switch (port) { case 2; reg = 0x34; val = 1<<5; break; case 3: reg = 0x22; val = 1<<6; break; case 4: reg = 0x34; val = 1<<31; break; case 5: case 6: reg = 0x39; val = 1<<31; break; case 7..9: reg = 0x37; val = 1<<port; break; case 10: reg = 0x22; val = 1<<5; break; default: reg = 0; break; } */ set_pcie_enable_bits(dev, 0xA4, 0x1, 0x1); pci_ext_write_config32(nb_dev, dev, 0x88, 0xF0, 1<<2); /* LINK_CRTL2*/ set_nbmisc_enable_bits(nb_dev, reg, val, val); }
/* * nb_lock : * close or hide unsed modules and lock the whole NB registers */ static void nb_lock(void) { pcitag_t nb_dev = _pci_make_tag(0, 0, 0); pcitag_t igfx_dev = _pci_make_tag(1, 5, 0); u32 base; u32 val; /* enable 2D optimization as configured */ if(ati_nb_cfg.gfx_config & (GFX_SP_ENABLE | GFX_UMA_ENABLE)){ if( (!(ati_nb_cfg.ext_config & EXT_DEBUG_GFX32BIT_MODE)) && (ati_nb_cfg.gfx_config & GFX_2D_OPTIMIZATION) ){ base = (_pci_conf_read(igfx_dev, 0x18) & 0xfffffff0) | 0xA0000000; if(base){ /* open memory access */ set_nbcfg_enable_bits(igfx_dev, 0x04, 1 << 1, 1 << 1); /* enable 2D accelerator */ val = *(volatile u32 *)(base | 0x4100); // 0x40FC + 4 ??? val |= 1 << 0; *(volatile u32 *)(base | 0x4100) = val; DEBUG_INFO("NB POST STAGE : nb_lock : 2D enable : address abnormal?\n"); } } } /* enable decode for debug BAR */ if( (ati_nb_cfg.gfx_config & (GFX_SP_ENABLE | GFX_UMA_ENABLE)) && (_pci_conf_read(nb_dev, 0x8C) & (1 << 9)) ){ set_nbcfg_enable_bits(nb_dev, 0x8C, 1 << 10, 1 << 10); }else{ set_nbcfg_enable_bits(nb_dev, 0x8C, 3 << 9, 0 << 9); } /* Hide PM2 bar */ set_nbcfg_enable_bits(nb_dev, 0x4C, 1 << 17, 0 << 17); /* set proper unused index for inderect space */ /* lock the NB */ set_nbmisc_enable_bits(nb_dev, 0x00, (1 << 0) | (1 << 7), (1 << 0) | (1 << 7)); return; }
/* enable CFG access to Dev8, which is the SB P2P Bridge */ void enable_rs780_dev8(void) { set_nbmisc_enable_bits(PCI_DEV(0, 0, 0), 0x00, 1 << 6, 1 << 6); }
static void rs780_por_misc_index_init(pci_devfn_t nb_dev) { /* NB_MISC_IND_WR_EN + IOC_PCIE_CNTL * Block non-snoop DMA request if PMArbDis is set. * Set BMSetDis */ set_nbmisc_enable_bits(nb_dev, 0x0B, ~0xFFFF0000, 0x00000180); set_nbmisc_enable_bits(nb_dev, 0x01, ~0xFFFFFFFF, 0x00000040); /* NBCFG (NBMISCIND 0x0): NB_CNTL - * HIDE_NB_AGP_CAP ([0], default=1)HIDE * HIDE_P2P_AGP_CAP ([1], default=1)HIDE * HIDE_NB_GART_BAR ([2], default=1)HIDE * AGPMODE30 ([4], default=0)DISABLE * AGP30ENCHANCED ([5], default=0)DISABLE * HIDE_AGP_CAP ([8], default=1)ENABLE */ set_nbmisc_enable_bits(nb_dev, 0x00, ~0xFFFF0000, 0x00000506); /* set bit 10 for MSI */ /* NBMISCIND:0x6A[16]= 1 SB link can get a full swing * set_nbmisc_enable_bits(nb_dev, 0x6A, 0ffffffffh, 000010000); * NBMISCIND:0x6A[17]=1 Set CMGOOD_OVERRIDE. */ set_nbmisc_enable_bits(nb_dev, 0x6A, ~0xffffffff, 0x00020000); /* NBMISIND:0x40 Bit[8]=1 and Bit[10]=1 following bits are required to set in order to allow LVDS or PWM features to work. */ set_nbmisc_enable_bits(nb_dev, 0x40, ~0xffffffff, 0x00000500); /* NBMISIND:0xC Bit[13]=1 Enable GSM mode for C1e or C3 with pop-up. */ set_nbmisc_enable_bits(nb_dev, 0x0C, ~0xffffffff, 0x00002000); /* Set NBMISIND:0x1F[3] to map NB F2 interrupt pin to INTB# */ set_nbmisc_enable_bits(nb_dev, 0x1F, ~0xffffffff, 0x00000008); /* * Enable access to DEV8 * Enable setPower message for all ports */ set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 6, 1 << 6); set_nbmisc_enable_bits(nb_dev, 0x0b, 1 << 20, 1 << 20); set_nbmisc_enable_bits(nb_dev, 0x51, 1 << 20, 1 << 20); set_nbmisc_enable_bits(nb_dev, 0x53, 1 << 20, 1 << 20); set_nbmisc_enable_bits(nb_dev, 0x55, 1 << 20, 1 << 20); set_nbmisc_enable_bits(nb_dev, 0x57, 1 << 20, 1 << 20); set_nbmisc_enable_bits(nb_dev, 0x59, 1 << 20, 1 << 20); set_nbmisc_enable_bits(nb_dev, 0x5B, 1 << 20, 1 << 20); set_nbmisc_enable_bits(nb_dev, 0x5D, 1 << 20, 1 << 20); set_nbmisc_enable_bits(nb_dev, 0x5F, 1 << 20, 1 << 20); set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 7, 1 << 7); set_nbmisc_enable_bits(nb_dev, 0x07, 0x000000f0, 0x30); set_nbmisc_enable_bits(nb_dev, 0x01, 0xFFFFFFFF, 0x48); /* Disable bus-master trigger event from SB and Enable set_slot_power message to SB */ set_nbmisc_enable_bits(nb_dev, 0x0B, 0xffffffff, 0x500180); }
void rs780_enable(device_t dev) { device_t nb_dev, sb_dev; int dev_ind; nb_dev = _pci_make_tag(0, 0, 0); sb_dev = _pci_make_tag(0, 8, 0); _pci_break_tag(dev, NULL, &dev_ind, NULL); switch(dev_ind) { case 0: printk_info("enable_pcie_bar3\n"); enable_pcie_bar3(nb_dev); /* PCIEMiscInit */ printk_info("config_gpp_core\n"); config_gpp_core(nb_dev, sb_dev); printk_info("rs780_gpp_sb_init\n"); rs780_gpp_sb_init(nb_dev, sb_dev, 8); /* set SB payload size: 64byte */ printk_info("set sb payload size:64byte\n"); set_pcie_enable_bits(nb_dev, 0x10 | PCIE_CORE_INDEX_GPPSB, 3 << 11, 2 << 11); /* Bus0Dev0Fun1Clock control init, we have to do it here, for dev0 Fun1 doesn't have a vendor or device ID */ //rs780_config_misc_clk(nb_dev); { /* BTDC: NBPOR_InitPOR function. */ u8 temp8; u16 temp16; u32 temp32; /* BTDC: Program NB PCI table. */ printk_info("Program NB PCI table\n"); temp16 = pci_read_config16(nb_dev, 0x04); printk_debug("BTDC: NB_PCI_REG04 = %x.\n", temp16); temp32 = pci_read_config32(nb_dev, 0x84); printk_debug("BTDC: NB_PCI_REG84 = %x.\n", temp32); pci_write_config8(nb_dev, 0x4c, 0x42); temp8 = pci_read_config8(nb_dev, 0x4e); temp8 |= 0x05; pci_write_config8(nb_dev, 0x4e, temp8); temp32 = pci_read_config32(nb_dev, 0x4c); printk_debug("BTDC: NB_PCI_REG4C = %x.\n", temp32); /* BTDC: disable GFX debug. */ printk_info("disable gfx debug\n"); temp8 = pci_read_config8(nb_dev, 0x8d); temp8 &= ~(1<<1); pci_write_config8(nb_dev, 0x8d, temp8); /* BTDC: set temporary NB TOM to 0x40000000. */ //printk_info("set temporary NB TOM to 0xf0000000\n"); //pci_write_config32(nb_dev, 0x90, 0x40000000); //pci_write_config32(nb_dev, 0x90, 0xf0000000); printk_info("set temporary NB TOM to 0xffffffff\n"); pci_write_config32(nb_dev, 0x90, 0xffffffff); /* BTDC: Program NB HTIU table. */ printk_info("Program NB HTIU table\n"); set_htiu_enable_bits(nb_dev, 0x05, 1<<10 | 1<<9, 1<<10|1<<9); set_htiu_enable_bits(nb_dev, 0x06, 1, 0x4203a202); set_htiu_enable_bits(nb_dev, 0x07, 1<<1 | 1<<2, 0x8001); set_htiu_enable_bits(nb_dev, 0x15, 0, 1<<31 | 1<<30 | 1<<27); set_htiu_enable_bits(nb_dev, 0x1c, 0, 0xfffe0000); set_htiu_enable_bits(nb_dev, 0x4b, 1<<11, 1<<11); set_htiu_enable_bits(nb_dev, 0x0c, 0x3f, 1 | 1<<3); set_htiu_enable_bits(nb_dev, 0x17, 1<<1 | 1<<27, 1<<1); set_htiu_enable_bits(nb_dev, 0x17, 0, 1<<30); set_htiu_enable_bits(nb_dev, 0x19, 0xfffff+(1<<31), 0x186a0+(1<<31)); set_htiu_enable_bits(nb_dev, 0x16, 0x3f<<10, 0x7<<10); set_htiu_enable_bits(nb_dev, 0x23, 0, 1<<28); /* BTDC: Program NB MISC table. */ printk_info("set NB MISC table\n"); set_nbmisc_enable_bits(nb_dev, 0x0b, 0xffff, 0x00000180); set_nbmisc_enable_bits(nb_dev, 0x00, 0xffff, 0x00000106); set_nbmisc_enable_bits(nb_dev, 0x51, 0xffffffff, 0x00100100); set_nbmisc_enable_bits(nb_dev, 0x53, 0xffffffff, 0x00100100); set_nbmisc_enable_bits(nb_dev, 0x55, 0xffffffff, 0x00100100); set_nbmisc_enable_bits(nb_dev, 0x57, 0xffffffff, 0x00100100); set_nbmisc_enable_bits(nb_dev, 0x59, 0xffffffff, 0x00100100); set_nbmisc_enable_bits(nb_dev, 0x5b, 0xffffffff, 0x00100100); set_nbmisc_enable_bits(nb_dev, 0x5d, 0xffffffff, 0x00100100); set_nbmisc_enable_bits(nb_dev, 0x5f, 0xffffffff, 0x00100100); set_nbmisc_enable_bits(nb_dev, 0x20, 1<<1, 0); set_nbmisc_enable_bits(nb_dev, 0x37, 1<<11|1<<12|1<<13|1<<26, 0); set_nbmisc_enable_bits(nb_dev, 0x68, 1<<5|1<<6, 1<<5); set_nbmisc_enable_bits(nb_dev, 0x6b, 1<<22, 1<<10); set_nbmisc_enable_bits(nb_dev, 0x67, 1<<26, 1<<14|1<<10); set_nbmisc_enable_bits(nb_dev, 0x24, 1<<28|1<<26|1<<25|1<<16, 1<<29|1<<25); set_nbmisc_enable_bits(nb_dev, 0x38, 1<<24|1<<25, 1<<24); set_nbmisc_enable_bits(nb_dev, 0x36, 1<<29, 1<<29|1<<28); set_nbmisc_enable_bits(nb_dev, 0x0c, 0, 1<<13); set_nbmisc_enable_bits(nb_dev, 0x34, 1<<22, 1<<10); set_nbmisc_enable_bits(nb_dev, 0x39, 1<<10, 1<<30); set_nbmisc_enable_bits(nb_dev, 0x22, 1<<3, 0); set_nbmisc_enable_bits(nb_dev, 0x68, 1<<19, 0); set_nbmisc_enable_bits(nb_dev, 0x24, 1<<16|1<<17, 1<<17); set_nbmisc_enable_bits(nb_dev, 0x6a, 1<<22|1<<23, 1<<17|1<<23); set_nbmisc_enable_bits(nb_dev, 0x35, 1<<21|1<<22, 1<<22); set_nbmisc_enable_bits(nb_dev, 0x01, 0xffffffff, 0x48); /* BTDC: the last two step. */ set_nbmisc_enable_bits(nb_dev, 0x01, 1<<8, 1<<8); set_htiu_enable_bits(nb_dev, 0x2d, 1<<6|1<<4, 1<<6|1<<4); } break; case 1: /* bus0, dev1, APC. */ printk_info("Bus-0, Dev-1, Fun-0.\n"); rs780_internal_gfx_enable(nb_dev,dev); break; case 2: case 3: set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind, (1 ? 0 : 1) << dev_ind); rs780_gfx_init(nb_dev, dev, dev_ind); break; case 4: /* bus0, dev4-7, four GPP */ case 5: case 6: case 7: enable_pcie_bar3(nb_dev); /* PCIEMiscInit */ set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind, (1 ? 0 : 1) << dev_ind); rs780_gpp_sb_init(nb_dev, dev, dev_ind); break; case 8: /* bus0, dev8, SB */ set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 6, (1 ? 0 : 1) << dev_ind); rs780_gpp_sb_init(nb_dev, dev, dev_ind); disable_pcie_bar3(nb_dev); break; case 9: /* bus 0, dev 9,10, GPP */ case 10: enable_pcie_bar3(nb_dev); /* PCIEMiscInit */ set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << (7 + dev_ind), (1 ? 0 : 1) << (7 + dev_ind)); rs780_gpp_sb_init(nb_dev, dev, dev_ind); break; default: printk_debug("unknown dev: %s\n", dev_ind); } }
/***************************************** * Compliant with CIM_33's PCIEGPPInit * nb_dev: * root bridge struct * dev: * p2p bridge struct * port: * p2p bridge number, 4-10 *****************************************/ void sr5650_gpp_sb_init(device_t nb_dev, device_t dev, u32 port) { u32 gpp_sb_sel = 0; struct southbridge_amd_sr5650_config *cfg = (struct southbridge_amd_sr5650_config *)nb_dev->chip_info; printk(BIOS_DEBUG, "gpp_sb_init nb_dev=0x%p, dev=0x%p, port=0x%x\n", nb_dev, dev, port); switch (port) { case 2: case 3: gpp_sb_sel = PCIE_CORE_INDEX_GPP1; break; case 4 ... 7: case 9: case 10: gpp_sb_sel = PCIE_CORE_INDEX_GPP3a; break; case 8: gpp_sb_sel = PCIE_CORE_INDEX_SB; break; case 11: case 12: gpp_sb_sel = PCIE_CORE_INDEX_GPP2; break; case 13: gpp_sb_sel = PCIE_CORE_INDEX_GPP3b; break; } /* Init common Core registers */ set_pcie_enable_bits(dev, 0xB1, 1 << 28 | 1 << 23 | 1 << 20 | 1 << 19, 1 << 28 | 1 << 23 | 1 << 20 | 1 << 19); if (gpp_sb_sel == PCIE_CORE_INDEX_GPP3a) { set_pcie_enable_bits(dev, 0xB1, 1 << 22, 1 << 22); /* 4.3.3.2.3 Step 10: Dynamic Slave CPL Buffer Allocation */ gpp3a_cpl_buf_alloc(nb_dev, dev); } if (gpp_sb_sel == PCIE_CORE_INDEX_GPP1 || gpp_sb_sel == PCIE_CORE_INDEX_GPP2) { gpp12_cpl_buf_alloc(nb_dev, dev); } set_pcie_enable_bits(dev, 0xA1, (1 << 26) | (1 << 24) | (1 << 11), 1 << 11); set_pcie_enable_bits(dev, 0xA0, 0x0000FFF0, 0x6830); // PCIE should not ignore malformed packet error or ATS request set_pcie_enable_bits(dev, 0x70, 1 << 12, 0); //Step 14.1: Advertising Hot Plug Capabilities set_pcie_enable_bits(dev, 0x10, 1 << 4, 1 << 4); //Enable power fault set_pcie_enable_bits(nb_dev, 0xC1 | gpp_sb_sel, 1 << 0, 1 << 0); /* init GPP core */ /* 4.4.2.step13.1. Sets RCB completion timeout to be 200ms */ pci_ext_write_config32(nb_dev, dev, 0x80, 0xF << 0, 0x6 << 0); /* 4.4.2.step13.2. RCB completion timeout on link down to shorten enumeration time. */ set_pcie_enable_bits(dev, 0x70, 1 << 19, 1 << 19); /* 4.4.2.step13.3. Enable slave ordering rules */ set_pcie_enable_bits(nb_dev, 0x20 | gpp_sb_sel, 1 << 8, 0 << 8); /* 4.4.2.step13.4. Sets DMA payload size to 64 bytes. */ set_pcie_enable_bits(nb_dev, 0x10 | gpp_sb_sel, 7 << 10, 4 << 10); /* 4.4.2.step13.5. Set REGS_DLP_IGNORE_IN_L1_EN to ignore DLLPs during L1 so that Tx Clk can be turned off. */ set_pcie_enable_bits(nb_dev, 0x02 | gpp_sb_sel, 1 << 0 | 1 << 8, 1 << 0 | 1 << 8); // add bit 8 from CIMx /* 4.4.2.step13.6. Set REGS_LC_ALLOW_TX_L1_CONTROL to allow TX to prevent LC from going to L1 when there are outstanding completions.*/ set_pcie_enable_bits(dev, 0x02, 1 << 15, 1 << 15); /* 4.4.2.step13.7. Set REGS_LC_DONT_GO_TO_L0S_IF_L1_ARMED to prevent lc to go to from L0 to Rcv_L0s if L1 is armed. */ set_pcie_enable_bits(dev, 0xA1, 1 << 11, 1 << 11); /* 4.4.2.step13.8. CMGOOD_OVERRIDE for all five PCIe cores. */ set_nbmisc_enable_bits(nb_dev, 0x22, 1 << 27, 1 << 27); /* 4.4.2.step13.9. Prevents Electrical Idle from causing a transition from Rcv_L0 to Rcv_L0s. */ set_pcie_enable_bits(dev, 0xB1, 1 << 20, 1 << 20); /* 4.4.2.step13.10. Prevents the LTSSM from going to Rcv_L0s if it has already acknowledged a request to go to L1 but it has not transitioned there yet. */ /* seems the same as step13.7 */ set_pcie_enable_bits(dev, 0xA1, 1 << 11, 1 << 11); /* 4.4.2.step13.11. Transmits FTS before Recovery. */ set_pcie_enable_bits(dev, 0xA3, 1 << 9, 1 << 9); /* 4.4.2.step13.12. Sets TX arbitration algorithm to round robin for PCIE-GPP1, PCIE-GPP2, PCIE-GPP3a and PCIE-GPP3b cores only. */ //if (gpp_sb_sel != PCIE_CORE_INDEX_SB) /* RPR NOT set SB_CORE, BTS set SB_CORE, we comply with BTS */ set_pcie_enable_bits(nb_dev, 0x1C | gpp_sb_sel, 0x7FF, 0x109); /* 4.4.2.step13.13. Sets number of TX Clocks to drain TX Pipe to 0x3.*/ set_pcie_enable_bits(dev, 0xA0, 0xF << 4, 0x3 << 4); /* 4.4.2.step13.14. Lets PI use Electrical Idle from PHY when turning off PLL in L1 at Gen 2 speed instead of Inferred Electrical Idle. NOTE: LC still uses Inferred Electrical Idle. */ set_pcie_enable_bits(nb_dev, 0x40 | gpp_sb_sel, 3 << 14, 2 << 14); /* 4.4.2.step13.15. Turn on rx_fronten_en for all active lanes upon exit from Electrical Idle, rather than being tied to PLL_PDNB. */ set_pcie_enable_bits(nb_dev, 0xC2 | gpp_sb_sel, 1 << 25, 1 << 25); /* 4.4.2.step13.16. Advertises TX L0s and L1 exit latency. TX L0s exit latency to be 100b: 512ns to less than 1us; L1 exit latency to be 011b: 4us to less than 8us. For Hot-Plug Slots: Advertise TX L0s and L1 exit latency. TX L0s exit latency to be 110b: 2us to 4us. L1 exit latency to be 111b: more than 64us.*/ //set_pcie_enable_bits(dev, 0xC1, 0xF << 0, 0xC << 0); /* 0xF for htplg. */ set_pcie_enable_bits(dev, 0xC1, 0xF << 0, 0xF << 0); /* 0xF for htplg. */ /* 4.4.2.step13.17. Always ACK an ASPM L1 entry DLLP to workaround credit control issue on PM_NAK message of SB700 and SB800. */ /* 4.4.4.step13.18. To allow advertising Gen 2 capabilities to Southbridge. */ if (port == 8) { set_pcie_enable_bits(dev, 0xA0, 1 << 23, 1 << 23); set_pcie_enable_bits(nb_dev, 0xC1 | gpp_sb_sel, 1 << 1, 1 << 1); } /* 4.4.2.step13.19. CMOS Option (Gen 2 AUTO-Part 1 - Enabled by Default) */ /* 4.4.2.step13.20. CMOS Option (RC Advertised Gen 2-Part1 - Disabled by Default)*/ set_nbcfg_enable_bits(dev, 0x88, 0xF << 0, 0x2 << 0); /* Disables GEN2 capability of the device. * RPR typo- it says enable but the bit setting says disable. * Disable it here and we enable it later. */ set_pcie_enable_bits(dev, 0xA4, 1 << 0, 1 << 0); /* 4.4.2.step13.21. */ /* 4.4.2.step13.22 */ /* Enable native PME. */ set_pcie_enable_bits(dev, 0x10, 1 << 3, 1 < 3); /* This bit when set indicates that the PCIe Link associated with this port is connected to a slot. */ pci_ext_write_config32(nb_dev, dev, 0x5a, 1 << 8, 1 << 8); /* This bit when set indicates that this slot is capable of supporting Hot-Plug operations. */ set_nbcfg_enable_bits(dev, 0x6C, 1 << 6, 1 << 6); /* Enables flushing of TLPs when Data Link is down. */ set_pcie_enable_bits(dev, 0x20, 1 << 19, 0 << 19); /* 4.4.2.step14. Server Class Hot Plug Feature */ /* 4.4.2 step14.1: Advertising Hot Plug Capabilities */ /* 4.4.2.step14.2: Firmware Upload */ /* 4.4.2.Step14.3: SBIOS Acknowledgment to Firmware of Successful Firmware Upload */ /* step14.4 */ /* step14.5 */ /* skip */ /* CIMx LPC Deadlock workaround - Enable Memory Write Map*/ if (gpp_sb_sel == PCIE_CORE_INDEX_SB) { set_pcie_enable_bits(nb_dev, 0x10 | gpp_sb_sel, 1 << 9, 1 << 9); set_htiu_enable_bits(nb_dev, 0x06, 1 << 26, 1 << 26); } /* This CPL setup requires more than this one register and should be done in gpp_core. * The additional setup is for the different revisions. */ /* CIMx CommonPortInit settings that are not set above. */ pci_ext_write_config32(nb_dev, dev, 0x88, 0xF0, 1 << 0); /* LINK_CRTL2 */ if ( port == 8 ) set_pcie_enable_bits(dev, 0xA0, 0, 1 << 23); /* set automatic Gen2 support, needs mainboard config option as Gen2 can cause issues on some platforms. */ init_gen2(nb_dev, dev, port); set_pcie_enable_bits(dev, 0xA4, 1 << 29, 1 << 29); set_pcie_enable_bits(dev, 0xC0, 1 << 15, 0); set_pcie_enable_bits(dev, 0xA2, 1 << 13, 0); /* Hotplug Support - bit5 + bit6 capable and surprise */ pci_ext_write_config32(nb_dev, dev, 0x6c, 0x60, 0x60); /* Set interrupt pin info 0x3d */ pci_ext_write_config32(nb_dev, dev, 0x3c, 1 << 8, 1 << 8); /* 5.12.9.3 Hotplug step 1 - NB_PCIE_ROOT_CTRL - enable pm irq The RPR is wrong - this is not a PCIEND_P register */ pci_ext_write_config32(nb_dev, dev, 0x74, 1 << 3, 1 << 3); /* 5.12.9.3 step 2 - PCIEP_PORT_CNTL - enable hotplug messages */ if ( port != 8) set_pcie_enable_bits(dev, 0x10, 1 << 2, 1 << 2); /* Not sure about this PME setup */ /* Native PME */ set_pcie_enable_bits(dev, 0x10, 1 << 3, 1 << 3); /* Not set in CIMx */ /* PME Enable */ pci_ext_write_config32(nb_dev, dev, 0x54, 1 << 8, 1 << 8); /* Not in CIMx */ /* 4.4.3 Training for GPP devices */ /* init GPP */ switch (port) { case 2: case 3: case 4: /* GPP_SB */ case 5: case 6: case 7: case 9: /*GPP*/ case 10: case 11: case 12: case 13: /* 4.4.2.step13.5. Blocks DMA traffic during C3 state */ set_pcie_enable_bits(dev, 0x10, 1 << 0, 0 << 0); /* Enabels TLP flushing */ set_pcie_enable_bits(dev, 0x20, 1 << 19, 0 << 19); /* check port enable */ if (cfg->port_enable & (1 << port)) { PcieReleasePortTraining(nb_dev, dev, port); if (!(AtiPcieCfg.Config & PCIE_GPP_COMPLIANCE)) { u8 res = PcieTrainPort(nb_dev, dev, port); printk(BIOS_DEBUG, "PcieTrainPort port=0x%x result=%d\n", port, res); if (res) { AtiPcieCfg.PortDetect |= 1 << port; } } } break; case 8: /* SB */ break; default: break; } /* Re-enable RC ordering logic after training (from CIMx)*/ set_pcie_enable_bits(nb_dev, 0x20 | gpp_sb_sel, 1 << 9, 0); /* Advertising Hot Plug Capabilities */ pci_ext_write_config32(nb_dev, dev, 0x6c, 0x04001B, 0x00001B); /* PCIE Late Init (CIMx late init - Maybe move somewhere else? Later in the coreboot PCI device enum?) */ /* Set Slot Number */ pci_ext_write_config32(nb_dev, dev, 0x6c, 0x1FFF << 19, port << 19); /* Set Slot present 0x5A*/ pci_ext_write_config32(nb_dev, dev, 0x58, 1 << 24, 1 << 24); //PCIE-GPP1 TXCLK Clock Gating In L1 Late Core sttting - Maybe move somewhere else? */ set_pcie_enable_bits(nb_dev, 0x11 | gpp_sb_sel, 0xF << 0, 0x0C << 0); /* Enable powering down PLLs in L1 or L23 Ready states. * Turns off PHY`s RX FRONTEND during L1 when PLL power down is enabled */ set_pcie_enable_bits(nb_dev, 0x40 | gpp_sb_sel, 0x1219, 0x1009); /* 4.4..7.1 TXCLK Gating in L1, Enables powering down TXCLK clock pads on the receive side. */ set_pcie_enable_bits(nb_dev, 0x40 | gpp_sb_sel, 1 << 6, 1 << 6); /* Step 21: Register Locking PCIE Misc. Late Core sttting - Must move somewhere do PciInitLate FIXME */ /* Lock HWInit Register */ //set_pcie_enable_bits(nb_dev, 0x10 | gpp_sb_sel, 1 << 0, 1 << 0); /* Step 27: LCLK Gating */ //EnableLclkGating(dev); /* Set Common Clock */ /* If dev present, set PcieCapPtr+0x10, BIT6); * set dev 0x68,bit 6 * retrain link, set dev, 0x68 bit 5; * wait dev 0x6B bit3 clear */ if (port == 8){ PciePowerOffGppPorts(nb_dev, dev, port); /* , This should be run for all ports that are not hotplug and don't detect devices */ } }
/*********************************************** * 0:00.0 NBCFG : * 0:00.1 CLK : bit 0 of nb_cfg 0x4c : 0 - disable, default * 0:01.0 P2P Internal: * 0:02.0 P2P : bit 2 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 * 0:03.0 P2P : bit 3 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 * 0:04.0 P2P : bit 4 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 * 0:05.0 P2P : bit 5 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 * 0:06.0 P2P : bit 6 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 * 0:07.0 P2P : bit 7 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 * 0:08.0 NB2SB : bit 6 of nbmiscind 0x00 : 0 - disable, default + 32 * 1 * case 0 will be called twice, one is by cpu in hypertransport.c line458, * the other is by rs690. ***********************************************/ void rs690_enable(device_t dev) { device_t nb_dev = 0, sb_dev = 0; int dev_ind; printk(BIOS_INFO, "rs690_enable: dev=%p, VID_DID=0x%x\n", dev, get_vid_did(dev)); nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); if (!nb_dev) { die("rs690_enable: CAN NOT FIND RS690 DEVICE, HALT!\n"); /* NOT REACHED */ } /* sb_dev (dev 8) is a bridge that links to southbridge. */ sb_dev = dev_find_slot(0, PCI_DEVFN(8, 0)); if (!sb_dev) { die("rs690_enable: CAN NOT FIND SB bridge, HALT!\n"); /* NOT REACHED */ } dev_ind = dev->path.pci.devfn >> 3; switch (dev_ind) { case 0: /* bus0, dev0, fun0; */ printk(BIOS_INFO, "Bus-0, Dev-0, Fun-0.\n"); enable_pcie_bar3(nb_dev); /* PCIEMiscInit */ config_gpp_core(nb_dev, sb_dev); rs690_gpp_sb_init(nb_dev, sb_dev, 8); /* set SB payload size: 64byte */ set_pcie_enable_bits(nb_dev, 0x10 | PCIE_CORE_INDEX_GPPSB, 3 << 11, 2 << 11); /* Bus0Dev0Fun1Clock control init, we have to do it here, for dev0 Fun1 doesn't have a vendor or device ID */ rs690_config_misc_clk(nb_dev); break; case 1: /* bus0, dev1 */ printk(BIOS_INFO, "Bus-0, Dev-1, Fun-0.\n"); break; case 2: /* bus0, dev2,3, two GFX */ case 3: printk(BIOS_INFO, "Bus-0, Dev-2,3, Fun-0. enable=%d\n", dev->enabled); set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind, (dev->enabled ? 0 : 1) << dev_ind); if (dev->enabled) rs690_gfx_init(nb_dev, dev, dev_ind); break; case 4: /* bus0, dev4-7, four GPP */ case 5: case 6: case 7: printk(BIOS_INFO, "Bus-0, Dev-4,5,6,7, Fun-0. enable=%d\n", dev->enabled); set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind, (dev->enabled ? 0 : 1) << dev_ind); if (dev->enabled) rs690_gpp_sb_init(nb_dev, dev, dev_ind); break; case 8: /* bus0, dev8, SB */ printk(BIOS_INFO, "Bus-0, Dev-8, Fun-0. enable=%d\n", dev->enabled); set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 6, (dev->enabled ? 1 : 0) << 6); if (dev->enabled) rs690_gpp_sb_init(nb_dev, dev, dev_ind); disable_pcie_bar3(nb_dev); break; default: printk(BIOS_DEBUG, "unknown dev: %s\n", dev_path(dev)); } }