void kgdb_params_early_init(void)
{
if (cpm_uart_nr)
return;
get_from_flat_dt("cpu", "clock-frequency", &ppc_proc_freq);
get_from_flat_dt("cpm", "brg-frequency", &brgfreq);
get_from_flat_dt("soc", "reg", &immrbase);
#ifdef CONFIG_FSL_BOOKE
/* MMU configuration for early access to IMMR and memory */
settlbcam(num_tlbcam_entries - 1, immrbase, immrbase, 0x100000, _PAGE_IO, 0);
settlbcam(0, KERNELBASE, 0, lmb_end_of_DRAM(), _PAGE_KERNEL, 0);
#else
/* Set up BAT for early access to IMMR */
mb();
mtspr(SPRN_DBAT1L, (immrbase & 0xffff0000) | 0x2a);
mtspr(SPRN_DBAT1U, (immrbase & 0xffff0000) | BL_256M << 2 | 2);
mb();
setbat(1, immrbase, immrbase, 0x10000000, _PAGE_IO);
#endif
#ifdef CONFIG_MPC8272_ADS
/* Enable serial ports in BCSR */
clrbits32((u32 *)0xf4500000, BCSR1_RS232_EN1 | BCSR1_RS232_EN2);
#endif
cpm2_reset();
init_ioports();
}
void __init udbg_init_cpm(void)
{
if (cpm_udbg_txdesc) {
#ifdef CONFIG_CPM2
setbat(1, 0xf0000000, 0xf0000000, 1024*1024, PAGE_KERNEL_NCG);
#endif
udbg_putc = udbg_putc_cpm;
}
}
unsigned long __init wii_mmu_mapin_mem2(unsigned long top)
{
unsigned long delta, size, bl;
unsigned long max_size = (256<<20);
/* MEM2 64MB@0x10000000 */
delta = wii_hole_start + wii_hole_size;
size = top - delta;
for (bl = 128<<10; bl < max_size; bl <<= 1) {
if (bl * 2 > size)
break;
}
setbat(4, PAGE_OFFSET+delta, delta, bl, PAGE_KERNEL_X);
return delta + bl;
}
void __init udbg_init_cpm(void)
{
#ifdef CONFIG_PPC_8xx
cpm_udbg_txdesc = (u32 __iomem __force *)
(CONFIG_PPC_EARLY_DEBUG_CPM_ADDR - PHYS_IMMR_BASE +
VIRT_IMMR_BASE);
cpm_udbg_txbuf = (u8 __iomem __force *)
(in_be32(&cpm_udbg_txdesc[1]) - PHYS_IMMR_BASE +
VIRT_IMMR_BASE);
#else
cpm_udbg_txdesc = (u32 __iomem __force *)
CONFIG_PPC_EARLY_DEBUG_CPM_ADDR;
cpm_udbg_txbuf = (u8 __iomem __force *)in_be32(&cpm_udbg_txdesc[1]);
#endif
if (cpm_udbg_txdesc) {
#ifdef CONFIG_CPM2
setbat(1, 0xf0000000, 0xf0000000, 1024*1024, PAGE_KERNEL_NCG);
#endif
udbg_putc = udbg_putc_cpm;
}
}
