Example #1
0
void uart_port_conf(int port)
{
	gpio_t *gpio = (gpio_t *) MMAP_GPIO;

	/* Setup Ports: */
	switch (port) {
	case 0:
		clrbits_be16(&gpio->par_uart,
			~(GPIO_PAR_UART_U0TXD_UNMASK & GPIO_PAR_UART_U0RXD_UNMASK));
		setbits_be16(&gpio->par_uart,
			GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
		break;
	case 1:
		clrbits_be16(&gpio->par_uart,
			~(GPIO_PAR_UART_U1TXD_UNMASK & GPIO_PAR_UART_U1RXD_UNMASK));
		setbits_be16(&gpio->par_uart,
			GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
		break;
	case 2:
		clrbits_8(&gpio->par_dspi,
			~(GPIO_PAR_DSPI_SIN_UNMASK & GPIO_PAR_DSPI_SOUT_UNMASK));
		out_8(&gpio->par_dspi,
			GPIO_PAR_DSPI_SIN_U2RXD | GPIO_PAR_DSPI_SOUT_U2TXD);
		break;
	}
}
Example #2
0
void uart_port_conf(int port)
{
	gpio_t *gpio = (gpio_t *) MMAP_GPIO;

	/* Setup Ports: */
	switch (port) {
	case 0:
		clrbits_be16(&gpio->par_uart,
			GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0);
		setbits_be16(&gpio->par_uart,
			GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0);
		break;
	case 1:
		clrbits_be16(&gpio->par_uart,
			GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3));
		setbits_be16(&gpio->par_uart,
			GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3));
		break;
	case 2:
#ifdef CONFIG_SYS_UART2_ALT1_GPIO
		clrbits_8(&gpio->par_timer, 0xf0);
		setbits_8(&gpio->par_timer,
			GPIO_PAR_TIN3_URXD2 | GPIO_PAR_TIN2_UTXD2);
#elif defined(CONFIG_SYS_UART2_ALT2_GPIO)
		clrbits_8(&gpio->par_feci2c, 0x00ff);
		setbits_8(&gpio->par_feci2c,
			GPIO_PAR_FECI2C_SCL_UTXD2 | GPIO_PAR_FECI2C_SDA_URXD2);
#elif defined(CONFIG_SYS_UART2_ALT3_GPIO)
		clrbits_be16(&gpio->par_ssi, 0x0f00);
		setbits_be16(&gpio->par_ssi,
			GPIO_PAR_SSI_RXD(2) | GPIO_PAR_SSI_TXD(2));
#endif
		break;
	}
}
Example #3
0
int fecpin_setclear(struct eth_device *dev, int setclear)
{
    gpio_t *gpio = (gpio_t *) MMAP_GPIO;
    struct fec_info_s *info = (struct fec_info_s *)dev->priv;

#ifdef CONFIG_MCF5445x
    if (setclear) {
#ifdef CONFIG_SYS_FEC_NO_SHARED_PHY
        if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
            setbits_be16(&gpio->par_feci2c,
                         GPIO_PAR_FECI2C_MDC0_MDC0 |
                         GPIO_PAR_FECI2C_MDIO0_MDIO0);
        else
            setbits_be16(&gpio->par_feci2c,
                         GPIO_PAR_FECI2C_MDC1_MDC1 |
                         GPIO_PAR_FECI2C_MDIO1_MDIO1);
#else
        setbits_be16(&gpio->par_feci2c,
                     GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
#endif

        if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
            setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC0_RMII_GPIO);
        else
            setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC1_RMII_ATA);
    } else {
        clrbits_be16(&gpio->par_feci2c,
                     GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);

        if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
#ifdef CONFIG_SYS_FEC_FULL_MII
            setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC0_MII);
#else
            clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC0_UNMASK);
#endif
        } else {
#ifdef CONFIG_SYS_FEC_FULL_MII
            setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC1_MII);
#else
            clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC1_UNMASK);
#endif
        }
    }
#endif	/* CONFIG_MCF5445x */

#ifdef CONFIG_MCF5441x
    if (setclear) {
        out_8(&gpio->par_fec, 0x03);
        out_8(&gpio->srcr_fec, 0x0F);
        clrsetbits_8(&gpio->par_simp0h, ~GPIO_PAR_SIMP0H_DAT_MASK,
                     GPIO_PAR_SIMP0H_DAT_GPIO);
        clrsetbits_8(&gpio->pddr_g, ~GPIO_PDDR_G4_MASK,
                     GPIO_PDDR_G4_OUTPUT);
        clrbits_8(&gpio->podr_g, ~GPIO_PODR_G4_MASK);

    } else
        clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC_MASK);
#endif
    return 0;
}
Example #4
0
void uart_port_conf(int port)
{
	gpio_t *gpio = (gpio_t *) MMAP_GPIO;

	/* Setup Ports: */
	switch (port) {
	case 0:
		clrbits_be16(&gpio->par_uart,
			GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
		setbits_be16(&gpio->par_uart,
			GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
		break;
	case 1:
		clrbits_be16(&gpio->par_uart,
			GPIO_PAR_UART_U1RXD_MASK | GPIO_PAR_UART_U1TXD_MASK);
		setbits_be16(&gpio->par_uart,
			GPIO_PAR_UART_U1RXD_U1RXD | GPIO_PAR_UART_U1TXD_U1TXD);
		break;
	case 2:
#ifdef CONFIG_SYS_UART2_PRI_GPIO
		clrbits_be16(&gpio->par_uart,
			GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
		setbits_be16(&gpio->par_uart,
			GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
#elif defined(CONFIG_SYS_UART2_ALT1_GPIO)
		clrbits_8(&gpio->par_feci2c,
			GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK);
		setbits_8(&gpio->par_feci2c,
			GPIO_PAR_FECI2C_EMDC_U2TXD | GPIO_PAR_FECI2C_EMDIO_U2RXD);
#endif
		break;
	}
}
Example #5
0
static int serial_mpc8xx_getc(struct udevice *dev)
{
	immap_t	__iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
	cpm8xx_t	__iomem *cpmp = &(im->im_cpm);
	struct serialbuffer	__iomem *rtx;
	unsigned char  c;
	uint rxindex;

	rtx = (struct serialbuffer __iomem *)&cpmp->cp_dpmem[CPM_SERIAL_BASE];

	/* Wait for character to show up. */
	while (in_be16(&rtx->rxbd.cbd_sc) & BD_SC_EMPTY)
		WATCHDOG_RESET();

	/* the characters are read one by one,
	 * use the rxindex to know the next char to deliver
	 */
	rxindex = in_be32(&rtx->rxindex);
	c = in_8(rtx->rxbuf + rxindex);
	rxindex++;

	/* check if all char are readout, then make prepare for next receive */
	if (rxindex >= in_be16(&rtx->rxbd.cbd_datlen)) {
		rxindex = 0;
		setbits_be16(&rtx->rxbd.cbd_sc, BD_SC_EMPTY);
	}
	out_be32(&rtx->rxindex, rxindex);
	return c;
}
Example #6
0
int misc_init_r(void)
{
	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;

#ifdef CONFIG_IDE_LED
	/* Configure PA8 as output port */
	setbits_be16(&immap->im_ioport.iop_padir, PA_8);
	setbits_be16(&immap->im_ioport.iop_paodr, PA_8);
	clrbits_be16(&immap->im_ioport.iop_papar, PA_8);
	setbits_be16(&immap->im_ioport.iop_padat, PA_8); /* turn it off */
#endif
	load_sernum_ethaddr();
	setenv("hw","4k");
	poweron_key();
	return (0);
}
Example #7
0
void ccm_set_flexbus_half_clock(f_bool half)
{
	struct ccm_regs *ccm = (struct ccm_regs *)MMAP_CCM;

	if (half)
		setbits_be16(&ccm->misccr2, 0x02);
	else
		clrbits_be16(&ccm->misccr2, 0x02);
}
Example #8
0
static int read_diag(void)
{
	int diag;
	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;

	clrbits_be16(&immr->im_ioport.iop_pcdir, PC_4);	/* input */
	clrbits_be16(&immr->im_ioport.iop_pcpar, PC_4);	/* gpio */
	setbits_be16(&immr->im_ioport.iop_pcdir, PC_5);	/* output */
	clrbits_be16(&immr->im_ioport.iop_pcpar, PC_4);	/* gpio */
	setbits_be16(&immr->im_ioport.iop_pcdat, PC_5);	/* 1 */
	udelay(500);
	if (in_be16(&immr->im_ioport.iop_pcdat) & PC_4) {
		clrbits_be16(&immr->im_ioport.iop_pcdat, PC_5);/* 0 */
		udelay(500);
		if(in_be16(&immr->im_ioport.iop_pcdat) & PC_4)
			diag = 0;
		else
			diag = 1;
	} else {
		diag = 0;
	}
	clrbits_be16(&immr->im_ioport.iop_pcdir, PC_5);	/* input */
	return (diag);
}
Example #9
0
void clock_enter_limp(int lpdiv)
{
	ccm_t *ccm = (ccm_t *)MMAP_CCM;
	int i, j;

	/* Check bounds of divider */
	if (lpdiv < CLOCK_LPD_MIN)
		lpdiv = CLOCK_LPD_MIN;
	if (lpdiv > CLOCK_LPD_MAX)
		lpdiv = CLOCK_LPD_MAX;

	/* Round divider down to nearest power of two */
	for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ;

	/* Apply the divider to the system clock */
	clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i));

	/* Enable Limp Mode */
	setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
}
Example #10
0
static int serial_mpc8xx_putc(struct udevice *dev, const char c)
{
	immap_t	__iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
	cpm8xx_t	__iomem *cpmp = &(im->im_cpm);
	struct serialbuffer	__iomem *rtx;

	if (c == '\n')
		serial_mpc8xx_putc(dev, '\r');

	rtx = (struct serialbuffer __iomem *)&cpmp->cp_dpmem[CPM_SERIAL_BASE];

	/* Wait for last character to go. */
	out_8(&rtx->txbuf, c);
	out_be16(&rtx->txbd.cbd_datlen, 1);
	setbits_be16(&rtx->txbd.cbd_sc, BD_SC_READY);

	while (in_be16(&rtx->txbd.cbd_sc) & BD_SC_READY)
		WATCHDOG_RESET();

	return 0;
}
Example #11
0
/* initialize higher level parts of CPU like timers */
int cpu_init_r(void)
{
#ifdef CONFIG_MCFFEC
	ccm_t *ccm = (ccm_t *) MMAP_CCM;
#endif
#ifdef CONFIG_MCFRTC
	rtc_t *rtc = (rtc_t *) (CONFIG_SYS_MCFRTC_BASE);
	rtcex_t *rtcex = (rtcex_t *) &rtc->extended;

	out_be32(&rtcex->gocu, CONFIG_SYS_RTC_CNT);
	out_be32(&rtcex->gocl, CONFIG_SYS_RTC_SETUP);

#endif
#ifdef CONFIG_MCFFEC
	if (CONFIG_SYS_FEC0_MIIBASE != CONFIG_SYS_FEC1_MIIBASE)
		setbits_be16(&ccm->misccr, CCM_MISCCR_FECM);
	else
		clrbits_be16(&ccm->misccr, CCM_MISCCR_FECM);
#endif

	return (0);
}
Example #12
0
static inline void power_on_3_3(int slot)
{
	immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
	setbits_be16(&immap->im_ioport.iop_pcdat, 0x0002);
	setbits_be16(&immap->im_ioport.iop_pcdir, 0x0002 | 0x0004);
}
Example #13
0
phys_size_t initdram(int board_type)
{
	u32 dramsize;

#if defined(CONFIG_SERIAL_BOOT)
	/*
	 * Serial Boot: The dram is already initialized in start.S
	 * only require to return DRAM size
	 */
	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
#else
	sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM);
	ccm_t *ccm = (ccm_t *)MMAP_CCM;
	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
	pm_t *pm = (pm_t *) MMAP_PM;
	u32 i;

	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;

	for (i = 0x13; i < 0x20; i++) {
		if (dramsize == (1 << i))
			break;
	}

	out_8(&pm->pmcr0, 0x2E);
	out_8(&gpio->mscr_sdram, 1);

	clrbits_be16(&ccm->misccr2, CCM_MISCCR2_FBHALF);
	setbits_be16(&ccm->misccr2, CCM_MISCCR2_DDR2CLK);

	out_be32(&sdram->rcrcr, 0x40000000);
	out_be32(&sdram->padcr, 0x01030203);

	out_be32(&sdram->cr00, 0x01010101);
	out_be32(&sdram->cr01, 0x00000101);
	out_be32(&sdram->cr02, 0x01010100);
	out_be32(&sdram->cr03, 0x01010000);
	out_be32(&sdram->cr04, 0x00010101);
	out_be32(&sdram->cr06, 0x00010100);
	out_be32(&sdram->cr07, 0x00000001);
	out_be32(&sdram->cr08, 0x01000001);
	out_be32(&sdram->cr09, 0x00000100);
	out_be32(&sdram->cr10, 0x00010001);
	out_be32(&sdram->cr11, 0x00000200);
	out_be32(&sdram->cr12, 0x01000002);
	out_be32(&sdram->cr13, 0x00000000);
	out_be32(&sdram->cr14, 0x00000100);
	out_be32(&sdram->cr15, 0x02000100);
	out_be32(&sdram->cr16, 0x02000407);
	out_be32(&sdram->cr17, 0x02030007);
	out_be32(&sdram->cr18, 0x02000100);
	out_be32(&sdram->cr19, 0x0A030203);
	out_be32(&sdram->cr20, 0x00020708);
	out_be32(&sdram->cr21, 0x00050008);
	out_be32(&sdram->cr22, 0x04030002);
	out_be32(&sdram->cr23, 0x00000004);
	out_be32(&sdram->cr24, 0x020A0000);
	out_be32(&sdram->cr25, 0x0C00000E);
	out_be32(&sdram->cr26, 0x00002004);
	out_be32(&sdram->cr28, 0x00100010);
	out_be32(&sdram->cr29, 0x00100010);
	out_be32(&sdram->cr31, 0x07990000);
	out_be32(&sdram->cr40, 0x00000000);
	out_be32(&sdram->cr41, 0x00C80064);
	out_be32(&sdram->cr42, 0x44520002);
	out_be32(&sdram->cr43, 0x00C80023);
	out_be32(&sdram->cr45, 0x0000C350);
	out_be32(&sdram->cr56, 0x04000000);
	out_be32(&sdram->cr57, 0x03000304);
	out_be32(&sdram->cr58, 0x40040000);
	out_be32(&sdram->cr59, 0xC0004004);
	out_be32(&sdram->cr60, 0x0642C000);
	out_be32(&sdram->cr61, 0x00000642);
	asm("tpf");

	out_be32(&sdram->cr09, 0x01000100);

	udelay(100);
#endif
	return dramsize;
};
Example #14
0
void uart_port_conf(int port)
{
    gpio_t *gpio = (gpio_t *) MMAP_GPIO;
#ifdef CONFIG_MCF5441x
    pm_t *pm = (pm_t *) MMAP_PM;
#endif

    /* Setup Ports: */
    switch (port) {
#ifdef CONFIG_MCF5441x
    case 0:
        /* UART0 */
        out_8(&pm->pmcr0, 24);
        clrbits_8(&gpio->par_uart0,
                  ~(GPIO_PAR_UART0_U0RXD_MASK | GPIO_PAR_UART0_U0TXD_MASK));
        setbits_8(&gpio->par_uart0,
                  GPIO_PAR_UART0_U0RXD_U0RXD | GPIO_PAR_UART0_U0TXD_U0TXD);
        break;
    case 1:
        /* UART1 */
        out_8(&pm->pmcr0, 25);
        clrbits_8(&gpio->par_uart1,
                  ~(GPIO_PAR_UART1_U1RXD_MASK | GPIO_PAR_UART1_U1TXD_MASK));
        setbits_8(&gpio->par_uart1,
                  GPIO_PAR_UART1_U1RXD_U1RXD | GPIO_PAR_UART1_U1TXD_U1TXD);
        break;
    case 2:
        /* UART2 */
        out_8(&pm->pmcr0, 26);
        clrbits_8(&gpio->par_uart2,
                  ~(GPIO_PAR_UART2_U2RXD_MASK | GPIO_PAR_UART2_U2TXD_MASK));
        setbits_8(&gpio->par_uart2,
                  GPIO_PAR_UART2_U2RXD_U2RXD | GPIO_PAR_UART2_U2TXD_U2TXD);
        break;
    case 3:
        /* UART3 */
        out_8(&pm->pmcr0, 27);
        clrbits_8(&gpio->par_dspi0,
                  ~(GPIO_PAR_DSPI0_SIN_MASK | GPIO_PAR_DSPI0_SOUT_MASK));
        setbits_8(&gpio->par_dspi0,
                  GPIO_PAR_DSPI0_SIN_U3RXD | GPIO_PAR_DSPI0_SOUT_U3TXD);
        break;
    case 4:
        /* UART4 */
        out_8(&pm->pmcr1, 24);
        clrbits_8(&gpio->par_uart0,
                  ~(GPIO_PAR_UART0_U0CTS_MASK | GPIO_PAR_UART0_U0RTS_MASK));
        setbits_8(&gpio->par_uart0,
                  GPIO_PAR_UART0_U0CTS_U4TXD | GPIO_PAR_UART0_U0RTS_U4RXD);
        break;
    case 5:
        /* UART5 */
        out_8(&pm->pmcr1, 25);
        clrbits_8(&gpio->par_uart1,
                  ~(GPIO_PAR_UART1_U1CTS_MASK | GPIO_PAR_UART1_U1RTS_MASK));
        setbits_8(&gpio->par_uart1,
                  GPIO_PAR_UART1_U1CTS_U5TXD | GPIO_PAR_UART1_U1RTS_U5RXD);
        break;
    case 6:
        /* UART6 */
        out_8(&pm->pmcr1, 26);
        clrbits_8(&gpio->par_uart2,
                  ~(GPIO_PAR_UART2_U2CTS_MASK | GPIO_PAR_UART2_U2RTS_MASK));
        setbits_8(&gpio->par_uart2,
                  GPIO_PAR_UART2_U2CTS_U6TXD | GPIO_PAR_UART2_U2RTS_U6RXD);
        break;
    case 7:
        /* UART7 */
        out_8(&pm->pmcr1, 27);
        clrbits_8(&gpio->par_ssi0h, ~GPIO_PAR_SSI0H_RXD_MASK);
        clrbits_8(&gpio->par_ssi0l, ~GPIO_PAR_SSI0L_BCLK_MASK);
        setbits_8(&gpio->par_ssi0h, GPIO_PAR_SSI0H_FS_U7TXD);
        setbits_8(&gpio->par_ssi0l, GPIO_PAR_SSI0L_BCLK_U7RXD);
        break;
    case 8:
        /* UART8 */
        out_8(&pm->pmcr0, 28);
        clrbits_8(&gpio->par_cani2c,
                  ~(GPIO_PAR_CANI2C_I2C0SCL_MASK | GPIO_PAR_CANI2C_I2C0SDA_MASK));
        setbits_8(&gpio->par_cani2c,
                  GPIO_PAR_CANI2C_I2C0SCL_U8TXD | GPIO_PAR_CANI2C_I2C0SDA_U8RXD);
        break;
    case 9:
        /* UART9 */
        out_8(&pm->pmcr1, 29);
        clrbits_8(&gpio->par_cani2c,
                  ~(GPIO_PAR_CANI2C_CAN1TX_MASK | GPIO_PAR_CANI2C_CAN1RX_MASK));
        setbits_8(&gpio->par_cani2c,
                  GPIO_PAR_CANI2C_CAN1TX_U9TXD | GPIO_PAR_CANI2C_CAN1RX_U9RXD);
        break;
#endif
#ifdef CONFIG_MCF5445x
    case 0:
        clrbits_8(&gpio->par_uart,
                  GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
        setbits_8(&gpio->par_uart,
                  GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
        break;
    case 1:
#ifdef CONFIG_SYS_UART1_PRI_GPIO
        clrbits_8(&gpio->par_uart,
                  GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
        setbits_8(&gpio->par_uart,
                  GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
#elif defined(CONFIG_SYS_UART1_ALT1_GPIO)
        clrbits_be16(&gpio->par_ssi,
                     ~(GPIO_PAR_SSI_SRXD_UNMASK | GPIO_PAR_SSI_STXD_UNMASK));
        setbits_be16(&gpio->par_ssi,
                     GPIO_PAR_SSI_SRXD_U1RXD | GPIO_PAR_SSI_STXD_U1TXD);
#endif
        break;
    case 2:
#if defined(CONFIG_SYS_UART2_ALT1_GPIO)
        clrbits_8(&gpio->par_timer,
                  ~(GPIO_PAR_TIMER_T3IN_UNMASK | GPIO_PAR_TIMER_T2IN_UNMASK));
        setbits_8(&gpio->par_timer,
                  GPIO_PAR_TIMER_T3IN_U2RXD | GPIO_PAR_TIMER_T2IN_U2TXD);
#elif defined(CONFIG_SYS_UART2_ALT2_GPIO)
        clrbits_8(&gpio->par_timer,
                  ~(GPIO_PAR_FECI2C_SCL_UNMASK | GPIO_PAR_FECI2C_SDA_UNMASK));
        setbits_8(&gpio->par_timer,
                  GPIO_PAR_FECI2C_SCL_U2TXD | GPIO_PAR_FECI2C_SDA_U2RXD);
#endif
        break;
#endif	/* CONFIG_MCF5445x */
    }
}
Example #15
0
static int serial_mpc8xx_probe(struct udevice *dev)
{
	immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
	smc_t __iomem *sp;
	smc_uart_t __iomem *up;
	cpm8xx_t __iomem *cp = &(im->im_cpm);
	struct serialbuffer __iomem *rtx;

	/* initialize pointers to SMC */

	sp = cp->cp_smc + SMC_INDEX;
	up = (smc_uart_t __iomem *)&cp->cp_dparam[PROFF_SMC];
	/* Disable relocation */
	out_be16(&up->smc_rpbase, 0);

	/* Disable transmitter/receiver. */
	clrbits_be16(&sp->smc_smcmr, SMCMR_REN | SMCMR_TEN);

	/* Enable SDMA. */
	out_be32(&im->im_siu_conf.sc_sdcr, 1);

	/* clear error conditions */
	out_8(&im->im_sdma.sdma_sdsr, CONFIG_SYS_SDSR);

	/* clear SDMA interrupt mask */
	out_8(&im->im_sdma.sdma_sdmr, CONFIG_SYS_SDMR);

	/* Use Port B for SMCx instead of other functions. */
	setbits_be32(&cp->cp_pbpar, IOPINS);
	clrbits_be32(&cp->cp_pbdir, IOPINS);
	clrbits_be16(&cp->cp_pbodr, IOPINS);

	/* Set the physical address of the host memory buffers in
	 * the buffer descriptors.
	 */
	rtx = (struct serialbuffer __iomem *)&cp->cp_dpmem[CPM_SERIAL_BASE];
	/* Allocate space for two buffer descriptors in the DP ram.
	 * For now, this address seems OK, but it may have to
	 * change with newer versions of the firmware.
	 * damm: allocating space after the two buffers for rx/tx data
	 */

	out_be32(&rtx->rxbd.cbd_bufaddr, (__force uint)&rtx->rxbuf);
	out_be16(&rtx->rxbd.cbd_sc, 0);

	out_be32(&rtx->txbd.cbd_bufaddr, (__force uint)&rtx->txbuf);
	out_be16(&rtx->txbd.cbd_sc, 0);

	/* Set up the uart parameters in the parameter ram. */
	out_be16(&up->smc_rbase, CPM_SERIAL_BASE);
	out_be16(&up->smc_tbase, CPM_SERIAL_BASE + sizeof(cbd_t));
	out_8(&up->smc_rfcr, SMC_EB);
	out_8(&up->smc_tfcr, SMC_EB);

	/* Set UART mode, 8 bit, no parity, one stop.
	 * Enable receive and transmit.
	 */
	out_be16(&sp->smc_smcmr, smcr_mk_clen(9) | SMCMR_SM_UART);

	/* Mask all interrupts and remove anything pending.
	*/
	out_8(&sp->smc_smcm, 0);
	out_8(&sp->smc_smce, 0xff);

	/* Set up the baud rate generator */
	serial_mpc8xx_setbrg(dev, gd->baudrate);

	/* Make the first buffer the only buffer. */
	setbits_be16(&rtx->txbd.cbd_sc, BD_SC_WRAP);
	setbits_be16(&rtx->rxbd.cbd_sc, BD_SC_EMPTY | BD_SC_WRAP);

	/* single/multi character receive. */
	out_be16(&up->smc_mrblr, CONFIG_SYS_SMC_RXBUFLEN);
	out_be16(&up->smc_maxidl, CONFIG_SYS_MAXIDLE);
	out_be32(&rtx->rxindex, 0);

	/* Initialize Tx/Rx parameters.	*/
	while (in_be16(&cp->cp_cpcr) & CPM_CR_FLG)	/* wait if cp is busy */
		;

	out_be16(&cp->cp_cpcr,
		 mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) | CPM_CR_FLG);

	while (in_be16(&cp->cp_cpcr) & CPM_CR_FLG)	/* wait if cp is busy */
		;

	/* Enable transmitter/receiver.	*/
	setbits_be16(&sp->smc_smcmr, SMCMR_REN | SMCMR_TEN);

	return 0;
}