LRESULT CALLBACK CfgDialogProc(HWND hWnd, UINT msg, WPARAM wp, LPARAM lp) {
switch (msg) {
case WM_INITDIALOG:
cfgcreate(hWnd);
return(FALSE);
case WM_COMMAND:
switch(LOWORD(wp)) {
case IDOK:
cfgupdate(hWnd);
EndDialog(hWnd, IDOK);
break;
case IDCANCEL:
EndDialog(hWnd, IDCANCEL);
break;
case IDC_BASECLOCK:
setclock(hWnd, 0);
return(FALSE);
case IDC_MULTIPLE:
if (HIWORD(wp) == CBN_SELCHANGE) {
UINT val;
val = (UINT)SendDlgItemMessage(hWnd, IDC_MULTIPLE,
CB_GETCURSEL, 0, 0);
if (val < NELEMENTS(mulval)) {
setclock(hWnd, mulval[val]);
}
}
else {
setclock(hWnd, 0);
}
return(FALSE);
default:
return(FALSE);
}
break;
case WM_CLOSE:
PostMessage(hWnd, WM_COMMAND, IDCANCEL, 0);
break;
default:
return(FALSE);
}
return(TRUE);
}
static void
init(Vga* vga, Ctlr* ctlr)
{
int x;
greg[0x15] = 0; /* allow writes to all registers */
if(vga->mode->z > 8)
error("depth %d not supported\n", vga->mode->z);
if(vga->mode->z == 8){
if(vga->linear && (ctlr->flag & Hlinear))
ctlr->flag |= Ulinear;
vga->vmz = 1024*1024;
vga->vmb = 1024*1024;
/* linear mapping - extension regs*/
greg[0x04] = (1<<2); /* enable CRTC bits 16 & 17, 32 bit mode */
greg[0x0b] = 0x15; /* linear addressing, > 256k, sequential addr */
greg[0x28] = 0x90; /* non-interlaced, 256 colors */
/* normal regs */
vga->sequencer[0x04] = 0x0A; /* sequential memory access */
vga->graphics[0x05] = 0x00; /* sequential access, shift out 8 bits at */
/* a time */
vga->attribute[0x10] &= ~(1<<6); /* 1 dot clock per pixel */
vga->crt[0x14] = 0x00;
vga->crt[0x17] = 0xe3; /* always byte mode */
} else {
/* mapped to 0xa0000 - extension regs*/
greg[0x04] = (1<<2); /* enable CRTC bits 16 & 17, 32 bit mode */
greg[0x0b] = 0x01; /* 0xA0000 - 0xAFFFF, planar addressing */
greg[0x28] = 0x80; /* non-interlaced, 16 colors */
}
/* the extension registers have even more overflow bits */
x = 0;
if(vga->mode->vt & (1<<10))
x |= (1<<0);
if(vga->mode->vrs & (1<<10))
x |= (1<<2);
greg[0x16] = x;
x = 0;
if(vga->mode->ht & (1<<(8+3)))
x |= (1<<0);
if(vga->mode->shb & (1<<(8+3)))
x |= (1<<4);
if(vga->mode->ehb & (1<<(6+3)))
x |= (1<<5);
greg[0x17] = x;
if(vga->mode->y > 480)
vga->misc &= 0x3F;
setclock(vga);
ctlr->flag |= Finit;
}
static void cfgcreate(HWND hWnd) {
TCHAR work[32];
UINT val;
SETLISTSTR(hWnd, IDC_BASECLOCK, basecstr);
if (np2cfg.baseclock < AVE(PCBASECLOCK25, PCBASECLOCK20)) {
val = 0;
}
else {
val = 1;
}
SendDlgItemMessage(hWnd, IDC_BASECLOCK, CB_SETCURSEL, val, 0);
SETLISTUINT32(hWnd, IDC_MULTIPLE, mulval);
wsprintf(work, str_u, np2cfg.multiple);
SetDlgItemText(hWnd, IDC_MULTIPLE, work);
if (!milstr_cmp(np2cfg.model, str_VM)) {
val = IDC_MODELVM;
}
else if (!milstr_cmp(np2cfg.model, str_EPSON)) {
val = IDC_MODELEPSON;
}
else {
val = IDC_MODELVX;
}
SetDlgItemCheck(hWnd, val, TRUE);
if (np2cfg.samplingrate < AVE(11025, 22050)) {
val = IDC_RATE11;
}
else if (np2cfg.samplingrate < AVE(22050, 44100)) {
val = IDC_RATE22;
}
else {
val = IDC_RATE44;
}
SetDlgItemCheck(hWnd, val, TRUE);
wsprintf(work, str_u, np2cfg.delayms);
SetDlgItemText(hWnd, IDC_SOUNDBUF, work);
setclock(hWnd, 0);
SetFocus(GetDlgItem(hWnd, IDC_BASECLOCK));
}
void
touser(void *initsp)
{
int rc;
void *kp;
vxproc *vp;
Ureg u;
Ureg *u1;
uchar *addr;
vp = up->pmmu.vxproc;
if(initsp){
/* init: clear register set, setup sp, eip */
memset(vp->cpu, 0, sizeof *vp->cpu);
vp->cpu->reg[ESP] = (ulong)initsp;
vp->cpu->eflags = 0;
vp->cpu->eip = UTZERO+32;
}else{
/* anyone else: registers are sitting at top of kernel stack */
kp = (char*)up->kstack + KSTACK - (sizeof(Ureg) + 2*BY2WD);
u1 = (Ureg*)((char*)kp + 2*BY2WD);
ureg2proc(u1, vp);
}
/*
* User-mode execution loop.
*/
for(;;){
/*
* Optimization: try to fault in code page and stack
* page right now, since we're likely to need them.
*/
if(up->pmmu.us->hi == 0){
fault(vp->cpu->eip, 1);
fault(vp->cpu->reg[ESP], 0);
}
/*
* Let vx32 know whether to allow floating point.
* TODO: Fix vx32 so that you don't need to flush
* on the transition from FPinactive -> FPactive.
*/
if(vp->allowfp != (up->fpstate == FPactive)){
vp->allowfp = (up->fpstate == FPactive);
vxproc_flush(vp);
}
if(traceprocs)
iprint("+vx32 %p %p %s eip=%lux esp=%lux\n",
m, up, up->text, vp->cpu->eip, vp->cpu->reg[ESP]);
setsigsegv(1);
setclock(1);
rc = vxproc_run(vp);
setclock(0);
setsigsegv(0);
if(rc < 0)
panic("vxproc_run: %r");
if(traceprocs)
iprint("-vx32 %p %p %s eip=%lux esp=%lux rc=%#x\n",
m, up, up->text, vp->cpu->eip, vp->cpu->reg[ESP], rc);
/*
* Handle page faults quickly, without proc2ureg, ureg2proc,
* if possible. Otherwise fall back to default trap call.
*/
if(rc == VXTRAP_PAGEFAULT){
int read;
nfaults++;
read = !(vp->cpu->traperr & 2);
addr = (uchar*)(uintptr)vp->cpu->trapva;
if(traceprocs)
print("fault %p read=%d\n", addr, read);
if(isuaddr(addr) && fault(addr - up->pmmu.uzero, read) >= 0)
continue;
print("%ld %s: unhandled fault va=%lux [%lux] eip=%lux\n",
up->pid, up->text,
addr - up->pmmu.uzero, vp->cpu->trapva, vp->cpu->eip);
proc2ureg(vp, &u);
dumpregs(&u);
if(abortonfault)
abort();
}
up->dbgreg = &u;
proc2ureg(vp, &u);
u.trap = rc;
trap(&u);
ureg2proc(&u, vp);
}
}
static void cfgcreate(HWND hWnd) {
TCHAR work[32];
UINT val;
dlgs_setcbitem(hWnd, IDC_BASECLOCK, cpBase, NELEMENTS(cpBase));
if (np2cfg.baseclock < AVE(PCBASECLOCK25, PCBASECLOCK20))
{
val = PCBASECLOCK20;
}
else
{
val = PCBASECLOCK25;
}
dlgs_setcbcur(hWnd, IDC_BASECLOCK, val);
SETLISTUINT32(hWnd, IDC_MULTIPLE, mulval);
wsprintf(work, tchar_u, np2cfg.multiple);
SetDlgItemText(hWnd, IDC_MULTIPLE, work);
if (!milstr_cmp(np2cfg.model, str_VM))
{
val = IDC_MODELVM;
}
else if (!milstr_cmp(np2cfg.model, str_EPSON))
{
val = IDC_MODELEPSON;
}
else
{
val = IDC_MODELVX;
}
SetDlgItemCheck(hWnd, val, TRUE);
if (np2cfg.samplingrate < AVE(11025, 22050))
{
val = IDC_RATE11;
}
else if (np2cfg.samplingrate < AVE(22050, 44100))
{
val = IDC_RATE22;
}
else
{
val = IDC_RATE44;
}
SetDlgItemCheck(hWnd, val, TRUE);
wsprintf(work, tchar_u, np2cfg.delayms);
SetDlgItemText(hWnd, IDC_SOUNDBUF, work);
SetDlgItemCheck(hWnd, IDC_ALLOWRESIZE, np2oscfg.thickframe);
#if !defined(_WIN64)
if (mmxflag & MMXFLAG_NOTSUPPORT)
{
EnableWindow(GetDlgItem(hWnd, IDC_DISABLEMMX), FALSE);
SetDlgItemCheck(hWnd, IDC_DISABLEMMX, TRUE);
}
else
{
SetDlgItemCheck(hWnd, IDC_DISABLEMMX, np2oscfg.disablemmx);
}
#endif
SetDlgItemCheck(hWnd, IDC_COMFIRM, np2oscfg.comfirm);
SetDlgItemCheck(hWnd, IDC_RESUME, np2oscfg.resume);
setclock(hWnd, 0);
SetFocus(GetDlgItem(hWnd, IDC_BASECLOCK));
}
