/**
* Main set up routine.
*/
void
setup(void) {
setup_processor_clocks();
setup_pins();
setup_usart();
setup_dma();
// Enable low and medium level interrupts.
PMIC.CTRL = PMIC_LOLVLEN_bm | PMIC_MEDLVLEN_bm;
/* Enable interrupts. */
sei();
}
wwd_result_t wwd_bus_init( void )
{
wwd_result_t result;
result = WWD_SUCCESS;
host_platform_power_wifi( WICED_FALSE );
host_platform_power_wifi( WICED_TRUE );
setup_pre_wlan_download();
boot_wlan();
/*
* The enabling of SDIO internal clock is done in WLAN firmware.
* Doing many access across AXI-bridge without proper sequencing will lead more instability
*/
setup_dma( );
return result;
}
int do_dma_cp ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
ulong addr, dest, count , tempaddr;
int size;
unsigned int ChannelNo;
struct dma_device_cfg configuration = {
MEMORY_DMA_REQ,
(DMA_WRAP_1|DMA_BURST_8|DMA_SIZE_32|DMA_SG_MODE|DMA_SW_REQ),
Source1,
Destination1,
} ;
if (argc != 4) {
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
}
/* Check for size specification.
*/
if ((size = cmd_get_data_size(argv[0], 4)) < 0)
return 1;
addr = simple_strtoul(argv[1], NULL, 16);
addr += base_address;
dest = simple_strtoul(argv[2], NULL, 16);
dest += base_address;
count = simple_strtoul(argv[3], NULL, 16);
if (count == 0) {
puts ("Zero length ???\n");
return 1;
}
count *= size;
#ifndef CFG_NO_FLASH
/* check if we are copying to Flash */
if ( (addr2info(dest) != NULL)
#ifdef CONFIG_HAS_DATAFLASH
&& (!addr_dataflash(addr))
#endif
) {
int rc;
puts ("Copy to Flash... ");
rc = flash_write ((char *)addr, dest, count);
if (rc != 0) {
flash_perror (rc);
return (1);
}
puts ("done\n");
return 0;
}
#endif
init_dma();
if(addr >= 0xFE000000){
*(volatile unsigned int *)(0xD8330000) = 0x33013301;
*(volatile unsigned int *)(0xD8330008) = 0x10004;
*(volatile unsigned int *)(0xD8330010) = 0x10004;
*(volatile unsigned int *)(0xD8330020) = 0x809;
*(volatile unsigned int *)(0xD8330028) = 0x809;
request_dma(&ChannelNo, "dmacp", I2S_TX_DMA_REQ);
}
else
request_dma(&ChannelNo, "dmacp", MEMORY_DMA_REQ);
if(addr >= 0xFE000000){
configuration.DeviceReqType = I2S_TX_DMA_REQ;
configuration.DefaultCCR = (DMA_WRAP_1|DMA_BURST_8|DMA_SIZE_32|DMA_SG_MODE|DMA_UP_MEMREG_EN|DEVICE_TO_MEM);
tempaddr = addr;
addr = dest;
dest = tempaddr;
}
init_descriptstack(ChannelNo);
setup_dma(ChannelNo, configuration);
//printf("ISR ch%d = %x\n", ChannelNo, pDma_Reg->DMA_ISR);
//printf("IER ch%d = %x\n", ChannelNo, pDma_Reg->DMA_IER);
//printf("CCR ch%d = %x\n", ChannelNo, pDma_Reg->DMA_CCR_CH[ChannelNo]);
//{
// start_dma(ChannelNo, (unsigned long)addr, (unsigned long)dest, count);
// printf("DMA%d : handle irq begin\n", ChannelNo);
// handle_dma_irq(ChannelNo);
// printf("DMA%d : handle irq OK\n", ChannelNo);
/*******************************************
* wait for dma transfer complete and terminal count
********************************************/
// while (1) {
// if (dma_busy(ChannelNo) != 1)
// break;
// }
// printf("DMA%d : no busy\n", ChannelNo);
// while (1) {
// if (dma_complete(ChannelNo) == 0)
// break;
// }
//}
handle_transfer(ChannelNo, (unsigned long)addr, (unsigned long)dest, count);
reset_descriptstack(ChannelNo);
printf("DMA%d : transfer OK\n", ChannelNo);
return 0;
}
static int hd_read_udma(block_dev_t *bdev, char *buffer, size_t count, blkno_t blkno) {
hd_t *hd;
hdc_t *hdc;
int sectsleft;
int nsects;
int result = 0;
char *bufp;
if (count == 0) {
return 0;
}
bufp = (char *) buffer;
hd = (hd_t *) bdev->privdata;
hdc = hd->hdc;
sectsleft = count / SECTOR_SIZE;
while (sectsleft > 0) {
/* Select drive */
ide_select_drive(hd);
/* Wait for controller ready */
result = ide_wait(hdc, HDCS_DRDY, HDTIMEOUT_DRDY);
if (result != 0) {
result = -EIO;
break;
}
/* Calculate maximum number of sectors we can transfer */
if (sectsleft > 256) {
nsects = 256;
} else {
nsects = sectsleft;
}
if (nsects > MAX_DMA_XFER_SIZE / SECTOR_SIZE) {
nsects = MAX_DMA_XFER_SIZE / SECTOR_SIZE;
}
/* Prepare transfer */
result = 0;
hdc->dir = HD_XFER_DMA;
hdc->active = hd;
hd_setup_transfer(hd, blkno, nsects);
/* Setup DMA */
setup_dma(hdc, bufp, nsects * SECTOR_SIZE, BM_CR_WRITE);
/* Start read */
outb(HDCMD_READDMA, hdc->iobase + HDC_COMMAND);
start_dma(hdc);
/* Stop DMA channel and check DMA status */
result = stop_dma(hdc);
if (result < 0) {
break;
}
/* Check controller status */
if (hdc->status & HDCS_ERR) {
result = -EIO;
break;
}
/* Advance to next */
sectsleft -= nsects;
bufp += nsects * SECTOR_SIZE;
}
/* Cleanup */
hdc->dir = HD_XFER_IDLE;
hdc->active = NULL;
return result == 0 ? count : result;
}
