static void test_ivshmem_pair(void)
{
IVState state1, state2, *s1, *s2;
char *data;
int i;
setup_vm(&state1);
s1 = &state1;
setup_vm(&state2);
s2 = &state2;
data = g_malloc0(TMPSHMSIZE);
/* host write, guest 1 & 2 read */
memset(tmpshmem, 0x42, TMPSHMSIZE);
read_mem(s1, 0, data, TMPSHMSIZE);
for (i = 0; i < TMPSHMSIZE; i++) {
g_assert_cmpuint(data[i], ==, 0x42);
}
read_mem(s2, 0, data, TMPSHMSIZE);
for (i = 0; i < TMPSHMSIZE; i++) {
g_assert_cmpuint(data[i], ==, 0x42);
}
/* guest 1 write, guest 2 read */
memset(data, 0x43, TMPSHMSIZE);
write_mem(s1, 0, data, TMPSHMSIZE);
memset(data, 0, TMPSHMSIZE);
read_mem(s2, 0, data, TMPSHMSIZE);
for (i = 0; i < TMPSHMSIZE; i++) {
g_assert_cmpuint(data[i], ==, 0x43);
}
/* guest 2 write, guest 1 read */
memset(data, 0x44, TMPSHMSIZE);
write_mem(s2, 0, data, TMPSHMSIZE);
memset(data, 0, TMPSHMSIZE);
read_mem(s1, 0, data, TMPSHMSIZE);
for (i = 0; i < TMPSHMSIZE; i++) {
g_assert_cmpuint(data[i], ==, 0x44);
}
cleanup_vm(s1);
cleanup_vm(s2);
g_free(data);
}
static void test_ivshmem_single(void)
{
IVState state, *s;
uint32_t data[1024];
int i;
setup_vm(&state);
s = &state;
/* initial state of readable registers */
g_assert_cmpuint(in_reg(s, INTRMASK), ==, 0);
g_assert_cmpuint(in_reg(s, INTRSTATUS), ==, 0);
g_assert_cmpuint(in_reg(s, IVPOSITION), ==, 0);
/* trigger interrupt via registers */
out_reg(s, INTRMASK, 0xffffffff);
g_assert_cmpuint(in_reg(s, INTRMASK), ==, 0xffffffff);
out_reg(s, INTRSTATUS, 1);
/* check interrupt status */
g_assert_cmpuint(in_reg(s, INTRSTATUS), ==, 1);
/* reading clears */
g_assert_cmpuint(in_reg(s, INTRSTATUS), ==, 0);
/* TODO intercept actual interrupt (needs qtest work) */
/* invalid register access */
out_reg(s, IVPOSITION, 1);
in_reg(s, DOORBELL);
/* ring the (non-functional) doorbell */
out_reg(s, DOORBELL, 8 << 16);
/* write shared memory */
for (i = 0; i < G_N_ELEMENTS(data); i++) {
data[i] = i;
}
write_mem(s, 0, data, sizeof(data));
/* verify write */
for (i = 0; i < G_N_ELEMENTS(data); i++) {
g_assert_cmpuint(((uint32_t *)tmpshmem)[i], ==, i);
}
/* read it back and verify read */
memset(data, 0, sizeof(data));
read_mem(s, 0, data, sizeof(data));
for (i = 0; i < G_N_ELEMENTS(data); i++) {
g_assert_cmpuint(data[i], ==, i);
}
cleanup_vm(s);
}
int main()
{
void *v;
int i;
printf("starting sieve\n");
test_sieve("static", static_data, STATIC_SIZE);
setup_vm();
test_sieve("mapped", static_data, STATIC_SIZE);
for (i = 0; i < 3; ++i) {
v = vmalloc(VSIZE);
test_sieve("virtual", v, VSIZE);
vfree(v);
}
return 0;
}
int main(int ac, char **av)
{
unsigned long i;
unsigned int pkey = 0x2;
unsigned int pkru_ad = 0x10;
unsigned int pkru_wd = 0x20;
if (!(cpuid_indexed(7, 0).c & (1 << X86_FEATURE_PKU))) {
printf("PKU not enabled\n");
return report_summary();
}
setup_vm();
setup_alt_stack();
set_intr_alt_stack(14, pf_tss);
wrmsr(MSR_EFER, rdmsr(MSR_EFER) | EFER_LMA);
for (i = 0; i < USER_BASE; i += PAGE_SIZE) {
*get_pte(phys_to_virt(read_cr3()), phys_to_virt(i)) &= ~PT_USER_MASK;
*get_pte(phys_to_virt(read_cr3()), phys_to_virt(i)) |= ((unsigned long)pkey << PTE_PKEY_BIT);
invlpg((void *)i);
}
for (i = USER_BASE; i < 2 * USER_BASE; i += PAGE_SIZE) {
*get_pte(phys_to_virt(read_cr3()), phys_to_virt(i)) &= ~USER_BASE;
*get_pte(phys_to_virt(read_cr3()), phys_to_virt(i)) |= ((unsigned long)pkey << PTE_PKEY_BIT);
invlpg((void *)i);
}
write_cr4(read_cr4() | X86_CR4_PKE);
write_cr3(read_cr3());
init_test();
set_cr0_wp(1);
write_pkru(pkru_ad);
test = 21;
report("write to supervisor page when pkru is ad and wp == 1", pf_count == 0 && test == 21);
init_test();
set_cr0_wp(0);
write_pkru(pkru_ad);
test = 22;
report("write to supervisor page when pkru is ad and wp == 0", pf_count == 0 && test == 22);
init_test();
set_cr0_wp(1);
write_pkru(pkru_wd);
test = 23;
report("write to supervisor page when pkru is wd and wp == 1", pf_count == 0 && test == 23);
init_test();
set_cr0_wp(0);
write_pkru(pkru_wd);
test = 24;
report("write to supervisor page when pkru is wd and wp == 0", pf_count == 0 && test == 24);
init_test();
write_pkru(pkru_wd);
set_cr0_wp(0);
USER_VAR(test) = 25;
report("write to user page when pkru is wd and wp == 0", pf_count == 0 && test == 25);
init_test();
write_pkru(pkru_wd);
set_cr0_wp(1);
USER_VAR(test) = 26;
report("write to user page when pkru is wd and wp == 1", pf_count == 1 && test == 26 && save == 25);
init_test();
write_pkru(pkru_ad);
(void)USER_VAR(test);
report("read from user page when pkru is ad", pf_count == 1 && save == 26);
// TODO: implicit kernel access from ring 3 (e.g. int)
return report_summary();
}
